A low-power double-edge trigger with low blocking glitch based on tfet, module
By designing a TFET-based low-power dual-edge flip-flop with blocking glitches, and employing a C-cell structure and a unique latch structure, the problems of signal contention and glitches in TFET flip-flops are solved, achieving low-power and high-speed flip-flop performance.
Patent Information
- Application Number
- CN202310132496.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-02-08
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2043-02-08
AI Technical Summary
Existing TFET-type flip-flop circuits suffer from problems such as signal contention, susceptibility to glitches, and high power consumption. In particular, in signal transmission of digital integrated circuits, power consumption caused by glitches accounts for 20% to 70% of the total power consumption.
Design a low-power dual-edge flip-flop based on TFET with blocking glitches. It employs an input stage circuit, a latch circuit, and an output stage circuit. It utilizes a C-cell structure to avoid the forward bias PIN current caused by the transmission gate, and uses a unique latch structure to avoid signal competition and block redundant transitions caused by glitches.
It effectively avoids the forward bias PIN current problem caused by the use of TFET transmission gates in traditional flip-flops, reduces power consumption, increases speed, blocks redundant transitions caused by glitch signals, and significantly reduces clock power consumption and static power consumption.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of circuit, and particularly relates to a blocking glitch low-power double-edge flip-flop based on TFET, a module, a timing circuit, and a large-scale digital integrated circuit adopting the corresponding timing circuit. BACKGROUND
[0002] The advent of integrated circuits is one of the important factors to promote the progress of the modern information age, and brings great changes to human daily production and life. In 1960, Kahng et al. proposed a metal-oxide-semiconductor field effect transistor (MOSFET), since then the integrated circuit industry has ushered in a rapid development stage following Moore's Law. With the progress of technology, the size of MOSFET is continuously reduced, and the chip integration is continuously increased. However, with the improvement of circuit performance, a series of problems are also brought, such as the short channel effect is getting more and more serious, the leakage current is increasing, and the static power consumption is also significantly increasing. When the transistor size enters the manufacturing process below 65 nm, the static power consumption has far exceeded the dynamic power consumption of the circuit.
[0003] Tunnel field effect transistor (TFET) is considered to be the most promising new low-power device to replace MOSFET. Compared with MOSFET, TFET device works with band-to-band tunneling mechanism, and is not limited by the carrier Boltzmann distribution, so TFET device has a lower subthreshold swing. At the same time, TFET device has extremely low leakage current and larger current switching ratio, and in the case of low voltage, TFET device can still effectively reduce the static power consumption. However, the different source-drain doping of TFET makes TFET have unidirectional conductivity, which may produce a positive bias P-I-N current that is not controlled by the gate. Especially for the flip-flop structure based on the transmission gate design, it will seriously affect the data stability.
[0004] Studies have shown that for digital integrated circuits, the power consumption of the timing circuit accounts for about 30% to 60% of the total power consumption. In the design of timing circuit, the clock system is mainly composed of clock tree circuit and timing unit. Flip-flop and latch are important components of timing logic unit, so the design of low-power flip-flop plays a very key role in reducing the power consumption of the entire digital integrated circuit. However, in the signal transmission of digital integrated circuit, there are often a large number of glitch signals. When the input signal glitches are transmitted to the circuit, it will cause the redundant jump of the internal nodes of the circuit to produce additional power loss, and even affect the normal work of the circuit. The power consumption caused by these glitch signals accounts for about 20% to 70% of the total power consumption. SUMMARY
[0005] In order to solve the problems of signal competition, being easily affected by glitch signal, high device power consumption and the like in the existing TFET type flip-flop circuit, the application provides a blocking glitch low-power double-edge flip-flop based on TFET, a module, a timing circuit and a large-scale digital integrated circuit using the corresponding timing circuit.
[0006] The application achieves the technical solutions as follows:
[0007] The blocking glitch low-power double-edge flip-flop based on TFET comprises an input stage circuit, a latch circuit and an output stage circuit.
[0008] The input stage circuit comprises an input port of a clock signal CLK and an input port of a control signal D. The input stage circuit generates two inverted clock signals CLK1 and CLK2 according to the input clock signal CLK. The input stage circuit further generates two intermediate signals A0 and B0 according to the input control signal D and the clock signals CLK1 and CLK2.
[0009] The latch circuit is composed of a first latch unit and a second latch unit which are completely identical. Each latch unit is composed of 4 PTFET transistors and 4 NTFET transistors. The first latch unit is composed of P4, P5, P6, P7, N4, N5, N6 and N7. The circuit connection relationship is as follows: the source of P4 is connected to a power supply, the gate is connected to the intermediate signal A0, and the drain is connected to the sources of P5, P6 and P7. The source of N7 is connected to ground, the gate is connected to the intermediate signal A0, and the drain is connected to the sources of N4, N5 and N6. The drains of P5, P6, N4 and N5 are connected to serve as a common node A. The gates of P5 and N4 are connected and connected to the clock signal CLK1. The gates of P6 and N5 are connected and connected to the control signal D. The drains of P7 and N6 are connected and serve as a common node QB. The gates of P7 and N6 are connected and serve as a common node Q.
[0010] The second latch unit is composed of P8, P9, P10, P11, N8, N9, N10 and N11 which are connected in sequence according to the corresponding order of P4, P5, P6, P7, N4, N5, N6 and N7. Among them, the gates of P9 and N8 in the second latch unit are connected to the clock signal CLK2, and the gates of P8 and N11 are connected to the intermediate signal B0.
[0011] The output stage circuit shares P4 and N11 in the latch circuit, and further comprises PTFET transistor P12, NTFET transistor N12, and an inverter INV5. The source of P12 is connected to the drain of P4; the drains of P12 and N12 and the input of INV5 are connected to a common node QB; the output of INV5 is connected to a common node Q; the source of N12 is connected to the drain of N11; the gate of P12 is connected to intermediate signal B0; and the gate of N12 is connected to intermediate signal A0.
[0012] As a further improvement of the application, the input stage circuit is composed of four inverters INV1, INV2, INV3, INV4, three PTFET transistors P1, P2, P3, and three NTFET transistors N1, N2, N3. The circuit connection relationship is as follows:
[0013] The input of INV1 is a clock signal CLK input port, the output of INV1 outputs clock signal CLK1 and is connected to the input of INV2 and the gates of P2 and N1. The output of INV2 outputs clock signal CLK2 and is connected to the gates of P3 and N2. The source of P1 is connected to a power supply, the gate of P1 is connected to the gate of N3 and is a control signal D input port; the drain of P1 is electrically connected to the sources of P2 and P3. The source of N3 is connected to a ground, the drain of N3 is electrically connected to the sources of N1 and N2; the drains of P2 and N1 and the input of INV3 are connected and are a common node A. The drains of P3 and N2 and the input of INV4 are connected and are a common node B; finally, intermediate signal A0 is output from the output of INV3, and intermediate signal B0 is output from the output of INV4.
[0014] As a further improvement of the application, in the input stage circuit, P1, P2, N1, N3 and P1, P3, N2, N3 all constitute C cell structures; further, (1) when clock signal CLK1 is the same as the potential of the input control signal D, node A outputs the inverse signal of D; when clock signal CLK1 is different from the potential of the input control signal D, nodes A and A0 can form a self-latching structure to keep data stable.
[0015] (2) when clock signal CLK2 is the same as the potential of the input control signal D, node B outputs the inverse signal of D; when clock signal CLK2 is different from the potential of the input control signal D, nodes B and B0 can form a self-latching structure to keep data stable.
[0016] As a further improvement of the present application, in the latch circuit, P4, P5, P6, N4, N5, N7 constitute a LA latch structure. P8, P9, P10, N8, N9, N11 constitute a LB latch structure. P4, P7, P8, P11, N6, N7, N10, N11 constitute a LC latch structure. The latch structures LA, LB, LC are used to make the intermediate nodes A, B, QB form a self-latch, and can also avoid signal competition between the C unit driving and the latch.
[0017] As a further improvement of the present application, in the output stage circuit, P4, P12, N12, N11 constitute a C unit structure, and make the C unit drive output when the signals A0 and B0 are at the same potential, and the final output result Q is fed back to the latch structure LC; when the potentials of the signals A0 and B0 are different, the potentials of the latches QB and Q are kept stable.
[0018] Further, the present application also includes a double-edge trigger module packaged by the aforementioned TFET-based blocking glitch low-power double-edge trigger circuit. The pins of the double-edge trigger module include: a power supply pin, a ground pin, a clock pin, a control pin, and an output pin.
[0019] The power supply pin is used to connect a power supply VDD. The ground pin is used to connect a ground VSS. The clock pin is used to connect a clock signal CLK. The control pin is used to connect a control signal D. The output pin is used to output a trigger signal Q generated according to the clock signal CLK and the control signal D.
[0020] The present application also includes a timing circuit which uses the aforementioned double-edge trigger module as a basic trigger element.
[0021] The present application also includes a digital integrated circuit which uses the aforementioned double-edge trigger module as a basic trigger element required in a timing circuit.
[0022] In the technical solution provided by the present application, the latch circuit can also be used as an independent component. The latch circuit provided by the present application is composed of four PTFET transistors P4, P5, P6, P7 and four NTFET transistors N4, N5, N6, N7. The circuit connection relationship is as follows: the source of P4 is connected to a power supply, the gate is connected to a signal A0, and the drain is connected to the sources of P5, P6, and P7; the source of N7 is connected to a ground, the gate is connected to a signal A0, and the drain is connected to the sources of N4, N5, and N6; the drains of P5, P6, N4, and N5 are connected as a common node A; the gates of P5 and N4 are connected and connected to a clock signal CLK1, the gates of P6 and N5 are connected and connected to a control signal D; the drains of P7 and N6 are connected and serve as a common node QB; and the gates of P7 and N6 are connected and serve as a common node Q.
[0023] Meanwhile, the application also includes a latch circuit for a double-edge trigger, which is composed of 8 PTFET transistors and 8 NTFET transistors. The latch circuit includes a first latch unit and a second latch unit, which have the same circuit structure.
[0024] In the first latch unit, P4, P5, P6, P7, N4, N5, N6 and N7 are included, and the circuit connection relationship is as follows: the source of P4 is connected to a power supply, the gate is connected to a signal A0, and the drain is connected to the sources of P5, P6 and P7; the source of N7 is connected to a ground, the gate is connected to the signal A0, and the drain is connected to the sources of N4, N5 and N6; the gates of P5 and N4 are connected and connected to a clock signal CLK1, the gates of P6 and N5 are connected and connected to a control signal D; the drains of P7 and N6 are connected and serve as a common node QB; and the gates of P7 and N6 are connected and serve as a common node Q.
[0025] In the same order and circuit connection relationship, the second latch unit is composed of P8, P9, P10, P11, N8, N9, N10 and N11; the gates of P9 and N8 are connected to the clock signal CLK2, and the gates of P8 and N11 are connected to the signal B0.
[0026] The technical solution provided by the application has the following beneficial effects:
[0027] The application designs a new double-edge trigger based on TFET, and C units are used as input and output levels in the double-edge trigger product, so that the problem of positive bias P-I-N current caused by the use of TFET transmission gate in the traditional trigger can be effectively avoided.
[0028] In the circuit designed in the application, based on the unique latch structure in the designed latch circuit, signal competition phenomenon does not occur between the C unit driving and the latch circuit. Meanwhile, the double-edge trigger provided by the application can effectively block the redundant jump caused by glitches, and the performance of the trigger product in speed, power consumption and other aspects is obviously improved. DETAILED DESCRIPTION
[0029] The accompanying drawings are used to provide a further understanding of the application, and constitute a part of the specification, together with the embodiments of the application, to explain the application, and do not constitute a limitation on the application. In the drawings:
[0030] Figure 1 FIG. 1 is a functional diagram of a double-edge trigger based on TFET and blocking glitches with low power consumption provided in Embodiment 1 of the application.
[0031] Figure 2The detailed circuit diagram of the TFET-based blocking glitch low-power double-edge trigger provided in Embodiment 1 of the present application is provided, and the latch circuit is divided according to different latch structures.
[0032] Figure 3 The module structure schematic diagram of the double-edge trigger module provided in Embodiment 1 of the present application is provided.
[0033] Figure 4 The simulation waveform diagram of the product in the present embodiment under the condition of no glitch of input signal in the performance test stage is provided.
[0034] Figure 5 The simulation waveform diagram of the product in the present embodiment under the condition of glitch of input signal in the performance test stage is provided.
[0035] Figure 6 The circuit connection diagram of the data selection type double-edge trigger MUX circuit used in the performance test stage is provided.
[0036] Figure 7 The circuit connection diagram of the C cell type double-edge trigger LG_C circuit used in the performance test stage is provided.
[0037] Figure 8 The circuit connection diagram of the explicit pulse type double-edge trigger E_Pulse circuit used in the performance test stage is provided.
[0038] Figure 9 The circuit connection diagram of the implicit pulse type double-edge trigger IP_C circuit used in the performance test stage is provided.
[0039] Figure 10 The circuit connection diagram of the implicit pulse type double-edge trigger FN_C circuit used in the performance test stage is provided.
[0040] Figure 11 The circuit connection diagram of the single-phase clock type double-edge trigger SSPC circuit used in the performance test stage is provided. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.
[0042] Embodiment 1
[0043] The present embodiment provides a TFET-based blocking glitch low-power double-edge trigger. As shown in FIG. 1, the double-edge trigger comprises a TFET-based latch circuit 1 and a TFET-based clocked inverter circuit 2. Figure 1 and Figure 2As shown, the trigger is composed of twelve PTFET transistors P1-P12, twelve NTFET transistors N1-N12 and five inverters INV1-INV5. According to the functional division, the blocking glitch low-power double-edge trigger includes an input stage circuit, a latch circuit and an output stage circuit three parts. The latch circuit is composed of three parts.
[0044] The input stage circuit is composed of four inverters INV1, INV2, INV3, INV4, three PTFET transistors P1, P2, P3, and three NTFET transistors N1, N2, N3. The latch circuit is composed of eight PTFET transistors and eight NTFET transistors, respectively P4, P5, P6, P7, P8, P9, P10, P11, and N4, N5, N6, N7, N8, N9, N10, N11. The output stage circuit is composed of P4, N11, P12, N12 and INV5. Among them, the latch circuit and the output stage circuit share devices P4 and N11.
[0045] Please combine Figure 2 The complete circuit connection relationship of the TFET-based blocking glitch low-power double-edge trigger provided in the embodiment is as follows:
[0046] The signal input end D is electrically connected with the gate of the PTFET transistor P1, the gate of the NTFET transistor N3, the gate of the PTFET transistor P6, the gate of the NTFET transistor N5, the gate of the PTFET transistor P10 and the gate of the NTFET transistor N9.
[0047] The clock signal CLK is electrically connected with the input end of the inverter INV1; the output end of the inverter INV1 is electrically connected with the input end of the inverter INV2, the gate of the PTFET transistor P2, the gate of the NTFET transistor N1, the gate of the PTFET transistor P5 and the gate of the NTFET transistor N4; the output end of the inverter INV2 is electrically connected with the gate of the PTFET transistor P3, the gate of the NTFET transistor N2, the gate of the PTFET transistor P9 and the gate of the NTFET transistor N8.
[0048] The source of the PTFET transistor P1 is electrically connected to a power supply, and the drain of the PTFET transistor P1 is electrically connected to the source of the PTFET transistor P2, the source of the PTFET transistor P3; the drain of the PTFET transistor P2 is electrically connected to the input terminal of the inverter INV3, the drain of the NTFET transistor N1, the drain of the PTFET transistor P5, the drain of the PTFET transistor P6, the drain of the NTFET transistor N4, the drain of the NTFET transistor N5; the drain of the PTFET transistor P3 is electrically connected to the input terminal of the inverter INV4, the drain of the NTFET transistor N2, the drain of the PTFET transistor P9, the drain of the PTFET transistor P10, the drain of the NTFET transistor N8, the drain of the NTFET transistor N9. The source of the NTFET transistor N1 is electrically connected to the source of the NTFET transistor N2, the drain of the NTFET transistor N3; the source of the NTFET transistor N3 is grounded.
[0049] The output terminal of the inverter INV3 is electrically connected to the gate of the PTFET transistor P4, the gate of the NTFET transistor N7, the gate of the NTFET transistor N12; the output terminal of the inverter INV4 is electrically connected to the gate of the PTFET transistor P8, the gate of the NTFET transistor N11, the gate of the PTFET transistor P12.
[0050] The source of the PTFET transistor P4 is electrically connected to a power supply, and the drain of the PTFET transistor P4 is electrically connected to the source of the PTFET transistor P5, the source of the PTFET transistor P6, the source of the PTFET transistor P7, the source of the PTFET transistor P12.
[0051] The gate of the PTFET transistor P7 is electrically connected to the output terminal of the inverter INV5, the gate of the NTFET transistor N6, the gate of the PTFET transistor P11, the gate of the NTFET transistor N10, and the drain of the PTFET transistor P7 is electrically connected to the input terminal of the inverter INV5, the drain of the NTFET transistor N6, the drain of the PTFET transistor P11, the drain of the NTFET transistor N10, the drain of the PTFET transistor P12, the drain of the NTFET transistor N12.
[0052] The source of NTFET transistor N6 is electrically connected to the sources of NTFET transistors N4 and N5, and the drain of NTFET transistor N7. The source of NTFET transistor N7 is grounded. The source of PTFET transistor P8 is electrically connected to the power supply, and the drain of PTFET transistor P8 is electrically connected to the sources of PTFET transistors P9, P10, and P11. The source of NTFET transistor N10 is electrically connected to the sources of NTFET transistors N8, N9, N12, and N11. The source of NTFET transistor N11 is grounded.
[0053] like Figure 2 As shown, in the latch circuit, P4, P5, P6, N4, N5, and N7 constitute the LA latch structure; P8, P9, P10, N8, N9, and N11 constitute the LB latch structure; and P4, P7, P8, P11, N6, N7, N10, and N11 constitute the LC latch structure. In addition to forming self-latches for intermediate nodes A, B, and QB, the latch structures LA, LB, and LC can also prevent signal contention between the C unit drive and the latch.
[0054] Combination Figure 2 As can be seen, the circuit structure of the TFET-based blocking glitch low-power dual-edge flip-flop proposed in this embodiment uses a C-cell structure for the input stage, avoiding the use of transmission gates. When the clock signal CLK1 is at the same potential as the input signal D, the output of node A is the inverted signal of D. When the clock signal CLK1 is at a different potential than the input signal D, the pull-up transistors composed of PTFET transistors P5 and P6 and the pull-down transistors composed of NTFET transistors N4 and N5 remain constantly on, so nodes A and A0 can form a self-latch structure to maintain data stability. When the clock signal CLK1 is again at the same potential as the input signal D, the latch structure LA can avoid the signal competition problem between the input and the latch, effectively improving speed and reducing power consumption.
[0055] Similarly, when the clock signal CLK2 is at the same potential as the input signal D, the B output is the inverse signal of D, and the principle of the latch structure LB is similar to that of LA. Therefore, the inverse signals A0 and B0 of A and B can store the level values of the input signal D under different clocks, respectively. The output stage also adopts the C cell structure, and drives the C cell to output when the signals A0 and B0 are at the same potential. The final output result Q is fed back to the latch structure LC, which can latch the potentials of QB and Q when the potentials of A0 and B0 are different, thereby keeping the data stable. The pull-up and pull-down tubes of the latch structure LC are controlled by the signals A0 and B0, so there is no signal competition phenomenon in the output stage and the latch structure LC.
[0056] In addition, since the input stage of the device in the embodiment adopts the C cell structure, the intermediate nodes A and B will only jump when the clock signal and the input signal D have the same level. Therefore, when the input signal contains multiple groups of glitch signals, the intermediate node A will jump to high level when the first glitch occurs, but subsequent glitch signals will not cause additional redundant jumps. Therefore, during the stable high and low level period of the clock signal CLK, no matter how many glitch interferences there are, the intermediate nodes A and B will at most jump once. At the same time, since the output stage of the double-edge trigger in the embodiment also adopts the C cell structure, the jump of the intermediate nodes A and B will not affect the output result Q.
[0057] In summary, the double-edge trigger based on the TFET provided in the embodiment adopts the C cell to transmit data, avoids the positive bias P-I-N current problem caused by the transmission gate, overcomes the signal competition phenomenon that may exist in the traditional device, and effectively blocks the redundant jumps caused by the glitch signals in the transmission signal. Furthermore, the device has very outstanding performance in terms of speed and power consumption, and the clock power consumption and static power consumption of the trigger are significantly lower than those of the conventional device.
[0058] In particular, the trigger product provided in the embodiment can be used as a basic element in a timing circuit or a large-scale digital integrated circuit containing a timing circuit, and is completely packaged inside the integrated circuit. It can also be used as a double-edge trigger functional module that can work independently. Figure 3 As shown in FIG. 6, when used as a double-edge trigger module, the pins of the module include a power supply pin, a ground pin, a clock pin, a control pin, and an output pin.
[0059] The power supply pin is used to connect the power supply VDD. The ground pin is used to connect the ground VSS. The clock pin is used to connect the clock signal CLK. The control pin is used to connect the control signal D. The output pin is used to output a trigger signal Q generated according to the clock signal CLK and the control signal D.
[0060] Furthermore, the latch circuit in this embodiment can also be used independently of the dual-edge flip-flop provided in this embodiment. For example, in other solutions, those skilled in the art can make appropriate adjustments to the input and output stage circuits based on the type of flip-flop provided in this embodiment. This allows for further improvement of the flip-flop's other performance characteristics while ensuring its power consumption, delay, and stability.
[0061] Performance test
[0062] To verify the performance of the TFET-based low-power dual-edge flip-flop with blocking glitches designed in this embodiment, engineers used a TFET device model with a channel length of 20nm to simulate the scheme and a control group in Cadence software, and tested the performance parameters of the flip-flop. The test content is as follows:
[0063] I. Burr-blocking performance test
[0064] In this embodiment, timing simulations of the trigger are performed under both no-glitch and glitch-containing input signals. The simulation conditions are: Corner: TT; Temperature: 27℃; VDD: 0.6V; Time: 100ns; Clock: 10ns; Switch activity α: 20%.
[0065] During the experiment, when the provided input signal is free of glitches, the simulation waveform of the double-edge trigger provided in this embodiment is as follows: Figure 4 As shown. When glitches exist in the input signal, the simulation waveform of the double-edge trigger in this embodiment is as follows. Figure 5 As shown. Analysis Figure 4 As can be seen, the device provided in this embodiment can effectively sample the input signal D at the rising and falling edges of the clock and output the signal Q, thereby realizing the function of a double-edge flip-flop.
[0066] Further analysis Figure 5The signal in the middle can be found that when the input signal D has a glitch, (for example, two sets of glitch signals are generated between 20ns to 40ns, and each set of glitch signals consists of two glitches) because the input stage adopts a C cell structure, only when the clock signal and the input signal D have the same level, the middle nodes A and B will jump. When the first glitch occurs, the input signal D and the clock signal CLK generate the same CLK1 potential, the middle node A jumps to high level; therefore, the second glitch signal will not cause additional redundant jumps. Therefore, during the stable high and low level of the clock signal CLK, no matter how many glitches interfere, the middle nodes A, B will at most only have a signal jump. In addition, considering that the output stage of the circuit of the embodiment also adopts a C cell structure, the jump of the middle nodes A, B will not affect the output result Q. This shows that the double-edge trigger provided by the embodiment can effectively block the redundant jump caused by the glitch, and reduce the power consumption of the circuit.
[0067] II. Control test
[0068] As shown above, the circuit design scheme provided by the embodiment can significantly reduce the power consumption of the TFET-based double-edge trigger, and improve the speed of the device. In order to more clearly verify the performance improvement of the device, the circuit of the present case is taken as the experimental group (Proposed), and a plurality of existing typical double-edge triggers are also selected as the control group for comparison test, to verify the difference between the performance of the embodiment scheme and the existing scheme.
[0069] Among them, the control group 1 is a data selection type double-edge trigger MUX circuit, hereinafter referred to as MUX, and the circuit diagram is as shown in Figure 6 The control group 2 is a C cell type double-edge trigger LG_C circuit, hereinafter referred to as LG_C, and the circuit diagram is as shown in Figure 7 The control group 3 is an explicit pulse type double-edge trigger E_Pulse circuit, hereinafter referred to as E_Pulse, and the circuit diagram is as shown in Figure 8 The control group 4 is an implicit pulse type double-edge trigger IP_C circuit, hereinafter referred to as IP_C, and the circuit diagram is as shown in Figure 9 The control group 5 is an implicit pulse type double-edge trigger FN_C circuit, hereinafter referred to as FN_C, and the circuit diagram is as shown in Figure 10 The control group 6 is a single-phase clock type double-edge trigger SSPC circuit, hereinafter referred to as SSPC, and the circuit diagram is as shown in Figure 11
[0070] In the control test, the performance test results of the devices of the present case and the control groups are as shown in Table 1:
[0071] Table 1: Performance comparison of double-edge triggers of experimental group and control group
[0072]
[0073] Analyzing the data in the above table, it can be found that in the circuit provided in the embodiment, although the number of transistors of the circuit is increased by 12.6% compared with the average of the prior art, the hold time is increased by 25.8% compared with the average. However, the critical time parameter D-Q delay of the flip-flop is reduced by 9.8% compared with the average, so the circuit provided in the embodiment has a certain improvement in speed.
[0074] In the above test data, the clock power consumption refers to the power consumption generated by the clock driving circuit when the input signal D is constant. It can be seen from the data in the above table that the clock power consumption of the circuit provided in the embodiment is reduced by 67.3% compared with the average. The static power consumption is reduced by 15.3% compared with the average of the prior art.
[0075] In particular, the average power consumption of the circuit provided in the embodiment is significantly reduced compared with the conventional scheme at different switching frequencies α. When the typical value of the switching frequency α is 20%, the average power consumption is reduced by 54.7% compared with the average of the prior art, and the performance improvement is very prominent.
[0076] In addition, the circuit provided in the embodiment also has good performance of blocking glitch signals. When the input signal has glitch interference, the power consumption of the embodiment is reduced by 46.3% compared with the average of the prior art.
[0077] The power-delay product PDP is a comprehensive index for measuring the speed and power consumption of the flip-flop. The simulation data in the table shows that the PDP performance of the circuit provided in the embodiment is reduced by 61.3% compared with the average of the prior art.
[0078] In summary: Through the simulation data above, it can be shown that the circuit provided in the embodiment has good performance in speed, power consumption and power-delay product.
[0079] The above only describes the preferred embodiments of the present application and should not be used to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims
1. A low-power dual-edge flip-flop with blocking glitch based on TFET, characterized in that, It includes: The input stage circuit includes a clock signal CLK input port and a control signal D input port; The input stage circuit generates two inverted clock signals CLK1 and CLK2 based on the input clock signal CLK; the input stage circuit also generates two intermediate signals A0 and B0 based on the input control signal D and the clock signals CLK1 and CLK2. The latch circuit consists of identical first and second latch units, each composed of four PTFET transistors and four NTFET transistors. The first latch unit comprises PTFET transistors P4, P5, P6, and P7 and NTFET transistors N4, N5, N6, and N7, connected as follows: the source of P4 is connected to the power supply, the gate to the intermediate signal A0, and the drain is connected to the sources of P5, P6, and P7; the source of N7 is grounded, the gate to the intermediate signal A0, and the drain is connected to the sources of N4, N5, and N6; the drains of P5, P6, N4, and N5 are connected as a common node A; the gates of P5 and N4 are connected... The clock signal CLK1 is connected in parallel. The gates of P6 and N5 are connected and connected to the control signal D. The drains of P7 and N6 are connected and serve as a common node QB. The gates of P7 and N6 are connected and serve as a common node Q. The second latch unit is composed of PTFET transistors P8, P9, P10, P11 and NTFET transistors N8, N9, N10, N11 connected in the order corresponding to P4, P5, P6, P7, N4, N5, N6, N7. The gates of P9 and N8 are connected to the clock signal CLK2, and the gates of P8 and N11 are connected to the intermediate signal B0. The drains of P9, P10, N8, and N9 are connected and serve as a common node B. The output stage circuit shares P4 and N11 in the latch circuit, and also includes PTFET transistor P12, NTFET transistor N12, and an inverter INV5; wherein, the source of P12 is connected to the drain of P4; the drains of P12 and N12 and the input of INV5 are connected to a common node QB, and the output of INV5 is connected to a common node Q; the source of N12 is connected to the drain of N11; the gate of P12 is connected to the intermediate signal B0, and the gate of N12 is connected to the intermediate signal A0.
2. The TFET-based low-power dual-edge flip-flop with blocking glitches as described in claim 1, characterized in that: The input stage circuit consists of four inverters INV1, INV2, INV3, and INV4, three PTFET transistors P1, P2, and P3, and three NTFET transistors N1, N2, and N3; the circuit connection is as follows: The input terminal of INV1 serves as the clock signal CLK input port. The output terminal of INV1 outputs the clock signal CLK1 and is connected to the input terminal of INV2, as well as the gates of P2 and N1. The output terminal of INV2 outputs the clock signal CLK2 and is connected to the gates of P3 and N2. The source of P1 is connected to the power supply, and the gate of P1 is connected to the gate of N3 and serves as the input port of the control signal D. The drain of P1 is electrically connected to the source of P2 and P3. The source of N3 is grounded, and the drain of N3 is electrically connected to the source of N1 and N2. The drains of P2 and N1 are connected to the input terminal of INV3 and serve as a common node A. The drains of P3 and N2 are connected to the input terminal of INV4 and serve as a common node B. Finally, the output terminal of INV3 outputs the intermediate signal A0, and the output terminal of INV4 outputs the intermediate signal B0.
3. The TFET-based low-power dual-edge flip-flop with blocking glitches as described in claim 2, characterized in that: In the input stage circuit, P1, P2, N1, N3 and P1, P3, N2, N3 all constitute a C-cell structure; thus, the following is achieved: i. When the clock signal CLK1 is at the same potential as the input control signal D, node A outputs the inverted signal of D; when the clock signal CLK1 is at a different potential than the input control signal D, nodes A and A0 form a self-latch structure to maintain data stability. ii. When the clock signal CLK2 is at the same potential as the input control signal D, node B outputs the inverse signal of D; when the clock signal CLK2 is at a different potential than the input control signal D, nodes B and B0 can form a self-locking structure to maintain data stability.
4. The TFET-based low-power dual-edge flip-flop with blocking glitches as described in claim 3, characterized in that: In the latch circuit, P4, P5, P6, N4, N5, and N7 constitute the LA latch structure; P8, P9, P10, N8, N9, and N11 constitute the LB latch structure; and P4, P7, P8, P11, N6, N7, N10, and N11 constitute the LC latch structure. The latch structures LA, LB, and LC are used to enable intermediate nodes A, B, and QB to form self-latches and to avoid signal contention between the C unit drive and the latch.
5. The TFET-based low-power dual-edge flip-flop with blocking glitch as described in claim 4, characterized in that: In the output stage circuit, P4, P12, N12, and N11 form a C-cell structure, which enables the C-cell to output when signals A0 and B0 are at the same potential, and the final output result Q is fed back to the latch structure LC; when signals A0 and B0 are at different potentials, the potentials of QB and Q are latched to keep the data stable.
6. A double-edge trigger module, characterized in that, It is packaged as a TFET-based low-power dual-edge flip-flop with blocking glitch as described in any one of claims 1-5, wherein the pins of the dual-edge flip-flop module include: The power supply pin is used to connect to the power supply VDD. Ground pin, used to ground VSS; Clock pin, which is used to connect to the clock signal CLK; The control pin is used to connect the control signal D; The output pin is used to output a trigger signal Q generated based on the clock signal CLK and the control signal D.
7. A sequential circuit, characterized in that, It uses the double-edge trigger module as described in claim 6 as the basic trigger element.
8. A digital integrated circuit, characterized in that, It uses the double-edge trigger module as described in claim 6 as the basic trigger element required in the timing circuit.
9. A latching circuit, characterized in that: It is the first latching unit in the TFET-based blocking glitch low-power dual-edge flip-flop as described in any one of claims 1-5, which is composed of four PTFET transistors P4, P5, P6, P7 and four NTFET transistors N4, N5, N6, N7; the circuit connection is as follows: the source of P4 is connected to the power supply, the gate is connected to the signal A0, and the drain is connected to the source of P5, P6, P7; the source of N7 is grounded, the gate is connected to the signal A0, and the drain is connected to the source of N4, N5, N6; the drains of P5, P6, N4, N5 are connected as a common node A; the gates of P5 and N4 are connected and connected to the clock signal CLK1, the gates of P6 and N5 are connected and connected to the control signal D; the drains of P7 and N6 are connected and connected as a common node QB; the gates of P7 and N6 are connected and connected as a common node Q.
10. A latching circuit for a double-edge flip-flop, characterized in that: It is the latch circuit in the TFET-based blocking glitch low-power double-edge flip-flop as described in any one of claims 1-5, which is composed of 8 PTFET transistors and 8 NTFET transistors; the latch circuit includes a first latch unit and a second latch unit with completely identical circuit structures; The first latch unit consists of P4, P5, P6, P7, N4, N5, N6, and N7, with the following circuit connections: the source of P4 is connected to the power supply, the gate is connected to signal A0, and the drain is connected to the sources of P5, P6, and P7; the source of N7 is grounded, the gate is connected to signal A0, and the drain is connected to the sources of N4, N5, and N6; the drains of P5, P6, N4, and N5 are connected as a common node A; the gates of P5 and N4 are connected and connected to the clock signal CLK1; the gates of P6 and N5 are connected and connected to the control signal D; the drains of P7 and N6 are connected as a common node QB; and the gates of P7 and N6 are connected as a common node Q. Following the same order and circuit connection, the second latch unit consists of P8, P9, P10, P11, N8, N9, N10, and N11; the gates of P9 and N8 are connected to the clock signal CLK2, and the gates of P8 and N11 are connected to the signal B0.