A partially interleaved high-speed successive approximation-pipeline analog-to-digital converter

Abstract

The application relates to a partially-interleaved high-speed successive approximation-pipelined analog-to-digital converter, which comprises a plurality of intermediate-stage pipeline modules, a final-stage analog-to-digital converter and a redundant-bit digital coding circuit. The intermediate-stage pipeline modules are connected in series and used for collecting analog differential input signals and outputting quantized digital codes and amplified residual error signals. Each intermediate-stage pipeline module comprises two sub-stage analog-to-digital converters and a residual error amplifier. The final-stage analog-to-digital converter is connected with the last residual error amplifier and used for receiving the amplified residual error signals and outputting quantized digital codes. The input ends of the redundant-bit digital coding circuit are connected with each sub-stage analog-to-digital converter and the final-stage analog-to-digital converter respectively, and the redundant-bit digital coding circuit is used for receiving the digital codes and converting and outputting binary digital codes corresponding to the analog differential input signals. The application solves the waiting time problem of amplification and sampling through multiplexing of the residual error amplifier, saves hardware cost and circuit power consumption, and greatly improves work efficiency.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital conversion, specifically relating to a partially interleaved high-speed successive approximation-pipeline analog-to-digital converter. Background Technology

[0002] Thanks to the continuous shrinking of integrated circuit process dimensions, digital circuits are becoming increasingly faster. Successive Approximation Register (SAR) analog-to-digital converters (ADCs), lacking numerous analog modules, exhibit excellent adaptability to advanced processes, resulting in significantly improved operating speeds. However, in some high-precision applications, SAR ADCs, lacking analog amplification units to reduce noise levels, do not perform as well as pipelined ADCs. Therefore, for high-speed, high-precision applications, the SAR-pipelined ADC circuit has emerged.

[0003] Successive approximation-pipelined analog-to-digital converters (ADCs) are hybrid ADCs combining pipelined ADCs and successive approximation ADCs. Their traditional structure consists of a sample-and-hold circuit, intermediate sub-pipelined stages, a back-end successive approximation ADC, and a redundant bit digital error correction block. Each intermediate sub-pipelined stage comprises a successive approximation ADC and an inter-stage residual amplifier. However, existing successive approximation-pipelined ADC circuits have high hardware overhead and overall power consumption. Furthermore, due to the time conflict caused by the sequential execution of intermediate stage amplification and sampling in the sub-ADCs, their operating speed urgently needs improvement. Summary of the Invention

[0004] This invention provides a partially interleaved high-speed successive approximation-pipeline analog-to-digital converter, comprising multiple intermediate-stage pipeline modules, a final-stage analog-to-digital converter, and a redundant-bit digital encoding circuit, wherein...

[0005] The multiple intermediate-stage pipeline modules are connected in series. These modules acquire analog differential input signals, quantize the signals to generate a residual signal and a quantized digital code, amplify the residual signal, and output the quantized digital code and the amplified residual signal. Each intermediate-stage pipeline module includes a first sub-stage analog-to-digital converter (ADC), a second sub-stage ADC, a first control switch, a second control switch, a third control switch, a fourth control switch, and a residual amplifier. The first control switch is connected between the first sub-stage ADC and the residual amplifier; the second control switch is connected between the first sub-stage ADC and the redundant bit digital encoding circuit; the third control switch is connected between the second sub-stage ADC and the residual amplifier; and the fourth control switch is connected between the second sub-stage ADC and the redundant bit digital encoding circuit. The output of the residual amplifier in the preceding intermediate-stage pipeline module is connected to the inputs of the first and second sub-stage ADCs in the following intermediate-stage pipeline module.

[0006] The input terminal of the final stage analog-to-digital converter is connected to the output terminal of the last residual amplifier. The final stage analog-to-digital converter is used to receive the amplified residual signal, quantize the amplified residual signal, and output the quantized digital code.

[0007] The input terminal of the redundant bit digital encoding circuit is connected to the output terminal of each first sub-stage analog-to-digital converter, the output terminal of each second sub-stage analog-to-digital converter, and the output terminal of the final stage analog-to-digital converter, respectively. It is used to receive quantized digital codes from each intermediate stage pipeline module and the final stage analog-to-digital converter, and output all the received quantized digital codes after encoding conversion.

[0008] In one embodiment of the present invention, a front-end sample-and-hold circuit is further included. The output terminal of the front-end sample-and-hold circuit is respectively connected to the input terminal of the first sub-stage analog-to-digital converter and the input terminal of the second sub-stage analog-to-digital converter in the first intermediate stage pipeline module. The circuit is used to acquire analog differential input signals and output the analog differential input signals as the signal source of the plurality of intermediate stage pipeline modules.

[0009] In one embodiment of the present invention, the first sub-stage analog-to-digital converter, the second sub-stage analog-to-digital converter, and the final stage analog-to-digital converter have the same structure.

[0010] In one embodiment of the present invention, the first sub-stage analog-to-digital converter, the second sub-stage analog-to-digital converter, and the final stage analog-to-digital converter are all successive approximation analog-to-digital converters.

[0011] In one embodiment of the present invention, the front-end sample-and-hold circuit is a bootstrap switch type sample-and-hold circuit.

[0012] In one embodiment of the invention, in each intermediate-stage pipeline module,

[0013] After the first sub-stage analog-to-digital converter completes quantization, the first control switch and the second control switch are turned on, and the third control switch and the fourth control switch are turned off, according to a preset timing control.

[0014] When the first sub-stage analog-to-digital converter completes transmitting the generated residual signal to the residual amplifier and the generated binary digital code to the redundant bit digital encoding circuit, the first control switch and the second control switch are turned off, and the third control switch and the fourth control switch are turned on, according to the preset timing control.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0016] 1. The partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided by this invention achieves parallel processing in the time domain by multiplexing the same residual amplifier in the intermediate stage pipeline module and controlling the first and second sub-stage analog-to-digital converters to alternately sample and quantize voltage signals. This solves the problem of time waiting between intermediate stage amplification and sampling in the entire successive approximation-pipeline analog-to-digital converter. Therefore, more time can be allocated to the inter-stage amplification stage and the sampling stage in the same conversion cycle, realizing the operation of dual-channel time-domain interleaving and greatly improving the working efficiency.

[0017] 2. The partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided by this invention, compared with the traditional dual-channel successive approximation analog-to-digital converter, effectively reduces the overall circuit area and power consumption by multiplexing the same residual amplifier and front-end sample-and-hold circuit in the first and second sub-stage analog-to-digital converters. This saves the hardware overhead caused by using other high-speed technologies such as one-step multi-bit, and greatly reduces the time-domain interleaving error caused by non-ideal factors such as clock skew and channel mismatch. At the same time, by using the same intermediate-stage pipeline module, the quantization bit depth of each intermediate-stage pipeline module is the same, which reduces the complexity of circuit design and improves the reproducibility of circuit modules.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram of another partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the working timing of an intermediate-level pipeline module provided in an embodiment of the present invention;

[0022] Figure 4 This is a timing comparison diagram of the traditional single-channel successive approximation-pipeline analog-to-digital converter and the partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided by this invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0024] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0025] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0026] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0027] Example 1

[0028] Please see Figure 1 , Figure 1 This is a schematic diagram of a partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided in an embodiment of the present invention. The successive approximation-pipeline analog-to-digital converter is used to convert analog differential input signals into analog digital information. The analog differential input signals are a pair of fully differential input signals of equal magnitude and opposite phase, used to characterize analog voltage signals.

[0029] The successive approximation-pipelined analog-to-digital converter (ADC) includes multiple intermediate-stage pipeline modules 20, a final-stage ADC 30, and a redundant-bit digital encoding circuit 40. Specifically, the multiple intermediate-stage pipeline modules 20 are connected in series. These modules are used to acquire analog differential input signals, quantize the signals to generate a residual signal and a quantized digital code, amplify the residual signal, and output the quantized digital code and the amplified residual signal. Further, each intermediate-stage pipeline module 20 includes a first sub-Analog-to-Digital Converter (Sub-ADC) 200, a second sub-ADC 201, a first control switch, a second control switch, a third control switch, a fourth control switch, and a residual amplifier (RA) 202. Specifically, a first control switch is connected between the first sub-stage analog-to-digital converter 200 and the residual amplifier 202, and a second control switch is connected between the first sub-stage analog-to-digital converter 200 and the redundant bit digital encoding circuit 40. When the first and second control switches are turned on, the first sub-stage analog-to-digital converter 200 performs sampling and quantization. Specifically, the first sub-stage analog-to-digital converter 200 acquires the analog differential input signal, quantizes the analog differential input signal after sampling, and then generates the quantized binary digital code and residual signal. The first sub-stage analog-to-digital converter 200 outputs the quantized binary digital code to the redundant bit digital encoding circuit 40 and outputs the generated residual signal to the residual amplifier 202, thus completing the quantization. Subsequently, the residual amplifier 202 amplifies the received residual signal and outputs the amplified residual signal to the next intermediate stage pipeline module 20, completing the amplification process of the residual amplifier 202. The second sub-stage analog-to-digital converter 201 has the same circuit connection structure and function as the first sub-stage analog-to-digital converter 200. Specifically, the third control switch is connected between the second sub-stage analog-to-digital converter 201 and the residual amplifier 202, and the fourth control switch is connected between the second sub-stage analog-to-digital converter 201 and the redundant bit digital encoding circuit 40.

[0030] The output of the residual amplifier 202 in the preceding intermediate stage pipeline module 20 is connected to the input of the first sub-stage analog-to-digital converter 200 and the second sub-stage analog-to-digital converter 201 in the following intermediate stage pipeline module 20. The output of the residual amplifier 202 in the last intermediate stage pipeline module 20 is connected to the final stage analog-to-digital converter 30. The multiple intermediate stage pipeline modules 20 perform the above quantization and amplification processes sequentially according to the order of their connection. The following intermediate stage pipeline module 20 receives the residual signal output by the preceding intermediate stage pipeline module 20 and quantizes and amplifies the received residual signal. Each intermediate stage pipeline module 20 outputs the quantized binary digital code to the redundant bit digital encoding circuit 40. The last residual amplifier 202 outputs the amplified residual signal to the final stage analog-to-digital converter 30.

[0031] Furthermore, the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201, and the final stage analog-to-digital converter 30 have the same structure and all use existing analog-to-digital converters.

[0032] Furthermore, the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201, and the final stage analog-to-digital converter 30 are all successive approximation analog-to-digital converters. The residual amplifier 202 adopts an existing circuit structure. In this embodiment, the residual amplifier 202 is a ring amplifier.

[0033] In each intermediate-stage pipeline module 20, the first to fourth control switches are turned on and off alternately in a timing sequence, enabling the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201, and the residual amplifier 202 to complete the acquisition-quantization-amplification process in parallel. This achieves a dual-channel time-domain interleaving working mode, which greatly improves working efficiency. The following describes the dual-channel time-domain interleaving working mode of the present invention.

[0034] In each intermediate-stage pipeline module 20, the first sub-stage analog-to-digital converter (ADC) 200 and the second sub-stage ADC 201 alternately sample the analog differential input signal and perform quantization alternately after sampling. Specifically, in the first intermediate-stage pipeline module 20, the first sub-stage ADC 200 acquires the analog differential input signal of the first cycle and performs quantization. After quantization, a binary digital code is generated. According to a preset timing sequence, the first and second control switches are simultaneously turned on, while the third and fourth control switches are turned off. The first sub-stage ADC 200 transmits the generated residual signal to the residual amplifier 202, and the first sub-stage ADC 200 transmits the generated binary digital code to the redundant bit digital encoding circuit 40. At this point, sampling by the second-stage analog-to-digital converter 201 is also complete. The second-stage analog-to-digital converter 201 performs quantization. When the second-stage analog-to-digital converter 201 completes quantization, the first-stage analog-to-digital converter 200 transmits the generated residual signal to the residual amplifier 202 and the generated binary digital code to the redundant bit digital encoding circuit 40. According to the preset timing control, the first and second control switches are closed, and the third and fourth control switches are opened. The residual signal generated by the second-stage analog-to-digital converter 201 is output to the residual amplifier 202, and the binary digital code of the second-stage analog-to-digital converter 201 is transmitted to the redundant bit digital encoding circuit 40. All subsequent cycles repeat the above operations. The operating mode of other intermediate-stage pipeline modules 20 is the same as that of the first intermediate-stage pipeline module 20, except that there is a one-cycle delay compared to the previous intermediate-stage pipeline module 20.

[0035] The pipelined analog-to-digital converter provided in this embodiment achieves dual-channel parallel processing in the time domain by multiplexing the same residual amplifier in the intermediate stage pipeline module and controlling the first sub-stage analog-to-digital converter 200 and the second sub-stage analog-to-digital converter 201 to alternately sample and quantize signals. This solves the problem of time waiting between intermediate stage amplification and sampling in the entire successive approximation-pipelined analog-to-digital converter. Therefore, more time can be allocated to the inter-stage amplification stage and the sampling stage in the same conversion cycle, realizing dual-channel time-domain interleaving and greatly improving work efficiency.

[0036] The input terminal of the final stage analog-to-digital converter 30 is connected to the last residual amplifier 202. The final stage analog-to-digital converter 30 is used to receive the amplified residual signal output from the last residual amplifier 202, quantize the amplified residual signal, and output the quantized digital code.

[0037] The input terminals of the redundant bit digital encoding circuit 40 are respectively connected to the output terminals of each first-stage analog-to-digital converter 200, each second-stage analog-to-digital converter 201, and the final-stage analog-to-digital converter 30. The output terminal of the redundant bit digital encoding circuit 40 is the output terminal of this interleaved high-speed successive approximation-pipeline analog-to-digital converter. The redundant bit digital encoding circuit 40 is used to receive the quantized digital codes from each first-stage analog-to-digital converter 200, each second-stage analog-to-digital converter 201, and the final-stage analog-to-digital converter 30, and to encode and convert all the received quantized digital codes to output a multi-bit binary digital code. This multi-bit binary digital code corresponds to the analog differential input signal. In this embodiment, the redundant bit digital encoding circuit 40 adopts an existing circuit structure.

[0038] In this embodiment, the interleaved high-speed successive approximation-pipeline analog-to-digital converter includes two intermediate-stage pipeline modules 20, a final-stage analog-to-digital converter 30, and a redundant bit digital encoding circuit 40. The two intermediate-stage pipeline modules 20 are a first intermediate-stage pipeline module and a second intermediate-stage pipeline module. The first intermediate-stage pipeline module acquires the analog differential input signal, quantizes the signal to generate a residual signal and a quantized D1-bit digital code, amplifies the residual signal, and outputs it to the second intermediate-stage pipeline module. The second intermediate-stage pipeline module quantizes and amplifies the received residual signal again to generate a quantized D2-bit digital code and outputs the amplified residual signal. The final-stage analog-to-digital converter 30 receives the amplified residual signal output from the second intermediate-stage pipeline module, quantizes it, and simultaneously generates a quantized D3-bit digital code. The redundant bit digital encoding circuit 40 receives the D1 bit digital code, the D2 bit digital code, and the D3 bit digital code, and outputs the D1+D2+D3-2 bit digital code after encoding conversion. In this embodiment, the number of quantized bits output by each intermediate stage pipeline module 20 and the final stage analog-to-digital converter 30 is the same, that is, the values ​​of D1, D2, and D3 are all the same.

[0039] This embodiment provides a partially interleaved high-speed successive approximation-pipelined analog-to-digital converter (ADC). Each intermediate-stage pipeline module 20 employs a two-channel time-domain interleaving operation, with parallel amplification between the two channels. This enables the reuse of the residual amplifier and achieves a dual-channel parallel sampling-quantization-amplification operation. Compared to traditional dual-channel successive approximation ADCs, this improves efficiency while effectively reducing overall circuit area and power consumption, saving the hardware overhead associated with using multi-step technology. Furthermore, by designing multiple intermediate-stage pipeline modules 20, the quantization bit depth of each pipeline sub-stage ADC is made identical, reducing circuit design complexity and improving the reproducibility of the circuit modules.

[0040] Example 2

[0041] Please see Figure 2 , Figure 2 This is a schematic diagram of another partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided by an embodiment of the present invention. Based on the first embodiment, this partially interleaved high-speed successive approximation-pipeline analog-to-digital converter further includes a front-end sample-and-hold circuit (S / H) 10. The output terminal of the front-end sample-and-hold circuit 10 is connected to the input terminal of the first sub-stage analog-to-digital converter 200 and the input terminal of the second sub-stage analog-to-digital converter 201 of the first intermediate stage pipeline module 20, respectively. The front-end sample-and-hold circuit 10 is used to acquire analog differential input signals and output the acquired analog differential input signals to the first intermediate stage pipeline module 20 as the signal source of the intermediate stage pipeline module 20.

[0042] The circuit structure of the front-end sample-and-hold circuit 10 is an existing circuit structure. In this embodiment, the front-end sample-and-hold circuit 10 is a bootstrap switch type sample-and-hold circuit. The partially interleaved high-speed successive approximation-pipeline analog-to-digital converter provided in this embodiment can acquire and hold analog differential input signals through the front-end sample-and-hold circuit 10. The analog differential input signals are stable during the holding phase. Therefore, the stable analog differential input signals are output to the intermediate pipeline module 20, reducing the sampling error caused by clock deviation in the intermediate pipeline module 20. This greatly reduces the time-domain interleaving error caused by non-ideal factors such as clock deviation and channel mismatch.

[0043] Please see Figure 3 , Figure 3 This is a schematic diagram of the working timing of an intermediate-stage pipeline module provided in an embodiment of the present invention. From the outside of the pipeline stage, each intermediate-stage pipeline module 20 is represented as a two-phase clock working mode. Because a partial time-domain interleaving technique is used, the time domain of the sampling phase of the second sub-stage analog-to-digital converter 201 is merged with the time domain of the amplification phase of the first sub-stage analog-to-digital converter 200, so that the working mode of each intermediate-stage pipeline module 20 only switches between the sampling / amplification phase and the quantization phase. Compared with the traditional working mode of switching between three phases of sampling, amplification, and quantization, the working efficiency is improved.

[0044] Furthermore, it can be seen from the overall working timing of the first-stage intermediate pipeline module 20 that the first-stage analog-to-digital converter 200, the second-stage analog-to-digital converter 201, and the residual amplifier 202 sample, quantize, and amplify through a partial time-domain interleaving technique. This achieves the effect of parallel amplification of the residual signals output by the first-stage analog-to-digital converter 200 and the second-stage analog-to-digital converter 201 through the residual amplifier 202, thus realizing the multiplexing of the residual amplifier 202.

[0045] Please see Figure 4 , Figure 4 This is a timing comparison diagram between a traditional single-channel successive approximation-pipelined analog-to-digital converter (ADC) and a partially interleaved high-speed successive approximation-pipelined ADC provided by this invention. The traditional single-channel successive approximation-pipelined ADC operates in three phase-switching modes: sampling, amplification, and quantization. After quantization is completed in the intermediate pipeline module, its capacitor array needs to wait for a period of time to amplify the differential signal, thus preventing direct sampling. In contrast, the partially interleaved high-speed successive approximation-pipelined ADC provided by this invention uses partial time-domain interleaving technology. One channel in the intermediate pipeline module amplifies the differential signal after quantization, while the other channel simultaneously samples the signal. This saves the waiting time for the amplification phase and achieves time-domain merging of the sampling and amplification phases. Therefore, compared to the traditional single-channel structure, it saves one-third of the operating time, significantly improving device efficiency.

[0046] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A partially interleaved high-speed successive approximation-pipelined analog-to-digital converter, characterized by, The application relates to an analog-to-digital conversion circuit, comprising a plurality of intermediate-stage pipeline modules (20), a final-stage analog-to-digital converter (30) and a redundant-bit digital encoding circuit (40), wherein, the plurality of intermediate-stage pipeline modules (20) are connected in series, the plurality of intermediate-stage pipeline modules (20) are used for collecting analog differential input signals, quantizing the analog differential input signals, generating residual error signals and quantized digital codes, amplifying the residual error signals, and outputting the quantized digital codes and the amplified residual error signals, wherein each intermediate-stage pipeline module (20) comprises a first sub-stage analog-to-digital converter (200), a second sub-stage analog-to-digital converter (201), a first control switch, a second control switch, a third control switch, a fourth control switch and a residual error amplifier (202), the first control switch is connected between the first sub-stage analog-to-digital converter (200) and the residual error amplifier (202), the second control switch is connected between the first sub-stage analog-to-digital converter (200) and the redundant-bit digital encoding circuit (40), the third control switch is connected between the second sub-stage analog-to-digital converter (201) and the residual error amplifier (202), and the fourth control switch is connected between the second sub-stage analog-to-digital converter (201) and the redundant-bit digital encoding circuit (40); the output end of the residual error amplifier (202) in a previous intermediate-stage pipeline module (20) is connected to the input end of the first sub-stage analog-to-digital converter (200) and the input end of the second sub-stage analog-to-digital converter (201) in a subsequent intermediate-stage pipeline module (20); the input end of the final-stage analog-to-digital converter (30) is connected to the output end of the last residual error amplifier (202), the final-stage analog-to-digital converter (30) is used for receiving the amplified residual error signals, quantizing the amplified residual error signals, and outputting quantized digital codes; the input end of the redundant-bit digital encoding circuit (40) is connected to the output end of each first sub-stage analog-to-digital converter (200), the output end of each second sub-stage analog-to-digital converter (201) and the output end of the final-stage analog-to-digital converter (30), the redundant-bit digital encoding circuit (40) is used for receiving quantized digital codes from each intermediate-stage pipeline module (20) and the final-stage analog-to-digital converter (30), and outputting all the received quantized digital codes after encoding conversion; in each intermediate-stage pipeline module (20), when the first sub-stage analog-to-digital converter (200) completes quantization, the first control switch and the second control switch are opened, and the third control switch and the fourth control switch are closed according to a preset timing sequence; when the first sub-stage analog-to-digital converter (200) completes transmission of the generated residual error signals to the residual error amplifier (202) and transmission of the generated binary digital codes to the redundant-bit digital encoding circuit (40), the first control switch and the second control switch are closed, and the third control switch and the fourth control switch are opened according to the preset timing sequence.

2. The partially interleaved successive approximation-register analog-to-digital converter of claim 1, wherein, The front-end sample-and-hold circuit (10) is connected to the input terminals of the first (200) and second (201) sub-stage analog-to-digital converters in the first intermediate-stage pipeline module (20) for collecting an analog differential input signal and outputting the analog differential input signal as a signal source of the plurality of intermediate-stage pipeline modules (20).

3. The partially interleaved successive approximation-register analog-to-digital converter of claim 1, wherein, The first (200), second (201) and final-stage (30) analog-to-digital converters are identical in structure.

4. The partially interleaved successive approximation-register analog-to-digital converter of claim 3, wherein, The first (200), second (201) and final-stage (30) analog-to-digital converters are successive approximation type analog-to-digital converters.

5. The partially interleaved successive approximation-register analog-to-digital converter of claim 2, wherein, The front-end sample-and-hold circuit (10) is a bootstrap switch type sample-and-hold circuit.

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