Parallel Interleaving System and Method for Multi-path Convolutional Coding

Abstract

This invention discloses a parallel interleaving system and method for multi-channel convolutional coding. The technical solution includes: a convolutional coding module sending generated multi-channel coded data and two punctured valid flag signals; an interleaving write address generation module sending two generated interleaving write addresses; a ping-pong read / write gating module sending generated ping-pong read / write gating signals and gating the coded data and interleaving write addresses; performing an interleaving write operation; an interleaving read address generation module sending multi-channel interleaving read addresses; gating the interleaving read addresses; performing an interleaving read operation and sending interleaved data; using dual-port RAM for synchronously switched interleaving read / write operations; and the system stopping operation. This invention reduces the complexity of convolutional coding and has the advantages of low complexity, low clock speed, high throughput, and high reliability.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and further relates to the field of communication digital signal processing technology, specifically a parallel interleaving system and method for multi-path convolutional coding. This invention can be used to design a parallel interleaving system for convolutional coding error correction in channel coding error correction. Background Technology

[0002] In communication systems, interleaving is generally a subsequent process to convolutional coding. The traditional convolutional coding process is as follows: one data stream is fed into a convolutional encoder, which outputs two encoded data streams, A and B. These two streams are then punctured, converted from parallel to serial, and merged into a single data stream. Multiple data streams generated by a multi-channel encoder are fed into a parallel interleaver. The operating frequency required for one serial data stream is twice that of two serial data streams. In traditional convolutional coding, the puncturing operation introduces parallel-to-serial conversion, requiring two clock cycles, which increases the maximum clock requirement. In scenarios with limited clock frequency, the system cannot function properly. This invention improves the convolutional coding process and also introduces new requirements for the parallel interleaving process.

[0003] TP-Link Technologies Co., Ltd. disclosed a data parallel interleaving method in its patent application "A Data Parallel Interleaving Method, Terminal Device and Computer Storage Medium" (Application Date: March 12, 2020, Application No. CN 202010169762.X; Publication No.: CN111478750A). The method disclosed in this patent application determines the ROM1 storing the RAM write address, the ROM2 storing the RAM read enable pattern, and the data parallel information corresponding to the processing unit through configuration information. During data writing, each bit of the input data with a maximum input parallelism of n is stored in different RAMs within the same clock cycle. Furthermore, the storage is based on the maximum output parallelism k as the basic storage unit, so that during reading, each group of output data is read sequentially according to the starting address of ROM2. Finally, according to the required output parallelism OV of the output data, OV bits of valid data are extracted from each group of output data, completing the data parallel interleaving. The drawback of this method is that it can only store one bit of data within the same clock cycle, which is insufficient to meet the input requirements of the convolutional coding data stream during the interleaving process. The system disclosed in TP-Link's patent application includes a ROM1 for determining the write address of the storage RAM, a ROM2 for storing the RAM read enable pattern, and a processing unit consisting of two RAM groups forming a ping-pong structure. After the total amount of data written is reached, the system writes the input data obtained from the second processing unit into the other RAM group of the ping-pong structure. If the input data to the first processing unit has not been completely read before the second processing unit finishes writing its input data, the system stops writing the input data to the second processing unit. A drawback of this patent application is that the ping-pong structure introduces a data write waiting problem when the input data to the first unit has not been completely read, increasing data flow latency. For a single-channel high-speed encoded data stream, buffering the input data is required, which increases system complexity and fails to meet high throughput requirements. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of the existing technology by providing a low-clock-rate, high-throughput parallel interleaving system and method for multi-path convolutional coding. This invention solves the low-clock-rate, high-throughput interleaving problem at the system level by improving existing convolutional coding and parallel interleaving methods.

[0005] The specific approach to achieving the objective of this invention is as follows: The convolutional coding method of this invention generates two punctured valid flag signals, and the interleaving method generates interleaving write addresses based on the punctured valid flag signals, avoiding the parallel-to-serial conversion structure and reducing the system's maximum clock requirement. The interleaving method of this invention uses a dual-port ROM to generate the interleaving read address and a dual-port RAM to perform interleaving read and write operations. It can write or read up to two bits of data within the same clock cycle, increasing the maximum number of data that can be written or read within the same clock cycle, thus meeting the input requirements of the convolutional coding data stream during interleaving. The interleaving system of this invention uses ping-pong read / write gating signals to select data and addresses, constructing two sets of structurally identical interleaving operation unit groups. Each set of interleaving operation unit groups can independently meet the write and read requirements. The two sets of interleaving operation unit groups synchronously alternate, performing continuous read and write operations without waiting or buffering for a single high-speed encoded data stream, thus meeting high-throughput interleaving requirements.

[0006] The parallel interleaving system of this invention includes a convolutional coding module, an interleaving write address generation module, an interleaving read address generation module, two sets of interleaving operation unit groups, and a ping-pong read / write gating module. All modules are developed using a graphical approach; wherein:

[0007] The convolutional coding module includes N conv There is one convolutional encoder and one puncturing module. Each convolutional encoder encodes data according to the system encoding rules to obtain two encoded data channels, A and B. One convolutional encoder is randomly selected, and its corresponding A and B encoded data channels are sent to the valid identifier module. The encoded data of all convolutional encoders are sent to the ping-pong read / write gating module. The puncturing module is used to mark the valid punctured data after puncturing the A and B encoded data channels respectively. The two valid identifier signals are sent to the interleaving write address generation module.

[0008] The interleaved write address generation module is used to generate two parallel interleaved write addresses after receiving two puncture valid flag signals, A and B, during the clock cycles when the puncture valid flag signals A and B are at a high level. The interleaved write address corresponding to the puncture valid flag signal A is accumulated starting from 0, and is accumulated once every high-level clock cycle, accumulating 2 interleaved write addresses at a time; the interleaved write address corresponding to the puncture valid flag signal B is accumulated starting from 1, and is accumulated once every high-level clock cycle, accumulating 2 interleaved write addresses at a time; the two interleaved write addresses are then sent to the ping-pong read / write gating module.

[0009] The ping-pong read / write gating module is activated upon receiving multi-channel encoded data. At this time, the system's maximum write time is used as the read / write cycle, and two ping-pong read / write gating signals, X and Y, are generated simultaneously. In the first read / write cycle, channel X is in the write cycle and channel Y is in the read cycle. In the next read / write cycle, channel X is in the read cycle and channel Y is in the write cycle, thus achieving signal selection and repetition control until the system stops operating. The X and Y ping-pong read / write gating signals within the read / write cycle are sent to the interleaved read address generation module. The X ping-pong read / write gating signal within the read / write cycle is sent to a set of interleaving operation units, and the Y ping-pong read / write gating signal within the read / write cycle is sent to another set of interleaving operation units. The interleaving operation unit, upon receiving encoded data and an interleaving write address, only sends the interleaving write address and encoded data to the interleaving operation unit group in the write cycle, and outputs two interleaving write addresses and multiple encoded data to each interleaving operation unit in the interleaving operation unit group; upon receiving an interleaving read address, only sends the interleaving read address to the interleaving operation unit group in the read cycle, and distributes different two interleaving read addresses to different interleaving operation units in each interleaving operation group; the two groups of multiple interleaved data generated by the two groups of interleaving operation unit groups are combined into one group of multiple interleaved data; the ping-pong read / write gating module outputs the combined multiple interleaved data in parallel, completing one interleaving operation;

[0010] The interleaved read address generation module includes N ROM Each dual-port address ROM is used to generate the ROM read address for the first time after receiving the X and Y channel strobe control signals in the first read cycle. This generation occurs once per read / write cycle, generating two ROM read addresses each time. The first ROM address starts at address 0 and is incremented by 2 addresses per clock cycle. The second ROM address starts at address 1 and is incremented by 2 addresses per clock cycle. Each dual-port address ROM, based on the same two ROM addresses, reads the interleaved read addresses initialized according to the system interleaving formula and stored in the dual-port address ROM in parallel. These multiple interleaved read addresses are then sent to the ping-pong read / write strobe module.

[0011] The interleaving operation unit includes N RAM Each dual-port RAM is used to write different two-way encoded data to each dual-port RAM within the same interleaving operation unit within a write cycle after receiving two-way interleaving write addresses and multi-way encoded data, according to the same two-way interleaving write addresses. For different interleaving operation units within the same group, at the same time as the write operations of the aforementioned interleaving operation units, a write operation is performed on each of their respective dual-port RAMs, with the same address and encoded data as the aforementioned interleaving operation unit write operations. Within a read cycle, the interleaving read address is arithmetically shifted left by N. bit The bits are used to obtain the RAM read address, where N bit=log2 N RAM N RAM This indicates the number of dual-port RAMs in the interleaving operation unit; during the read cycle, for each dual-port RAM in the same interleaving operation unit, two interleaved data streams are read out according to the same two RAM read addresses; during the read cycle, the remainder obtained by performing a modulo operation on the number of convolutional encoders using the received interleaved read addresses is output, and the two interleaved data streams read from the dual-port RAM corresponding to the remainder are output; each interleaving operation unit sends its generated two interleaved data streams to the ping-pong read / write gating module; the encoded data in the interleaving operation unit group controlled by the X-channel ping-pong read / write gating signals is cleared.

[0012] The specific steps of the parallel interleaving method of the present invention include the following:

[0013] Step 1: Send the generated multi-channel encoded data and two puncture valid indicator signals:

[0014] Step 1.1: Each convolutional encoder in the convolutional coding module encodes data according to the system coding rules to obtain two encoded data paths, A and B.

[0015] Step 1.2: Randomly select a convolutional encoder and send its corresponding A and B encoded data to the valid identifier module;

[0016] Step 1.3: Send all the encoded data from the convolutional encoders into the ping-pong read / write gating module;

[0017] Step 1.4: The puncturing module in the convolutional coding module performs puncturing operations on the A and B encoded data respectively and marks the valid punctured data as valid; the two valid mark signals are sent to the interleaving write address generation module.

[0018] Step 2, send the two interleaved write address generated based on the punch valid flag signal:

[0019] Step 2.1: After receiving the A and B puncture valid flag signals, the interleaving write address generation module generates two parallel interleaving write addresses during the clock cycles when the A and B puncture valid flag signals are at a high level. The interleaving write address corresponding to the A puncture valid flag signal is incremented starting from 0, and is incremented once every high-level clock cycle, accumulating 2 interleaving write addresses at a time. The interleaving write address corresponding to the B puncture valid flag signal is incremented starting from 1, and is incremented once every high-level clock cycle, accumulating 2 interleaving write addresses at a time.

[0020] Step 2.2: The interleaved write address generation module sends the two interleaved write addresses to the ping-pong read / write gating module;

[0021] Step 3: Send the generated ping-pong read / write strobe signal and select the strobe-encoded data and the interleaved write address:

[0022] Step 3.1: Upon receiving multi-channel encoded data, the ping-pong read / write gating module starts up. At this time, the maximum write time of the system is used as the read / write cycle, and two ping-pong read / write gating signals, X and Y, are generated simultaneously. In the first read / write cycle, X is in the write cycle and Y is in the read cycle. In the next read / write cycle, X is in the read cycle and Y is in the write cycle. This signal selection and repetition control is achieved until the system stops operating.

[0023] Step 3.2: Send the X and Y channel ping-pong read / write strobe signals during the read / write cycle to the interleaved read address generation module;

[0024] Step 3.3: Send the X-channel ping-pong read / write strobe signal during the read / write cycle to one set of interleaving operation units, and send the Y-channel ping-pong read / write strobe signal during the read / write cycle to another set of interleaving operation units.

[0025] Step 3.4: After receiving the encoded data and the interleaving write address, the ping-pong read / write gating module only sends the interleaving write address and encoded data to the interleaving operation unit group that is in the write cycle, and outputs two interleaving write addresses and multiple encoded data to each interleaving operation unit in the interleaving operation unit group.

[0026] Step 4: Perform interleaved write operations using dual-port RAM:

[0027] Step 4.1: In the write cycle after receiving the two-way interleaving write address and the multi-way encoded data, the interleaving operation unit in the interleaving operation unit group controlled by the X-way ping-pong read / write strobe signal writes different two-way encoded data to each dual-port RAM in the same interleaving operation unit according to the same two-way interleaving write address; for different interleaving operation units in the same group, at the same time as the above interleaving operation unit write operation, they perform the same write operation on their respective dual-port RAM with the same address and the same encoded data as the above interleaving operation unit write operation.

[0028] Step 5: Send the multi-interleaved read address generated using the dual-port ROM:

[0029] Step 5.1 After receiving the first read cycle of the X and Y channel strobe control signals, the ROM read address is generated for the first time. It is generated once per read / write cycle, and two ROM read addresses are generated each time. The initial address of the first ROM address is 0, and it is incremented once per clock cycle, with 2 ROM addresses incremented at a time. The initial address of the second ROM address is 1, and it is incremented once per clock cycle, with 2 ROM addresses incremented at a time.

[0030] Step 5.2 Each dual-port address ROM in the interleaving read address generation module reads out the interleaving read address initialized and stored in the dual-port address ROM according to the system interleaving formula in parallel on two separate paths, based on the same two ROM addresses.

[0031] Step 5.3 The interleaved read address generation module sends the multi-interleaved read addresses to the ping-pong read / write gating module;

[0032] Step 6: Select and interleave the address according to the ping-pong read / write strobe signal:

[0033] After receiving the interleaved read address, the Ping-Pong read / write gating module only sends the interleaved read address to the interleaved operation unit group that is in the read cycle, and distributes different two-way interleaved read addresses to different interleaved operation units in each interleaved operation group.

[0034] Step 7: Perform interleaved read operations using dual-port RAM and send the combined interleaved data:

[0035] Step 7.1: The interleaving operation unit in the interleaving operation unit group, controlled by the X-channel ping-pong read / write strobe signal, performs an arithmetic left shift N of the interleaving read address during the read cycle. bit The bits are used to obtain the RAM read address, where N bit =log2 N RAM N RAM Indicates the number of dual-port RAMs in the interleaving operation unit;

[0036] Step 7.2: The interleaving operation unit in the interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal reads out two interleaved data channels respectively in the same interleaving operation unit for each dual-port RAM in the same interleaving operation unit according to the same two RAM read addresses during the read cycle.

[0037] Step 7.3: The interleaving operation unit in the interleaving operation unit group controlled by the X-channel ping-pong read / write gating signal outputs the two interleaved data read from the dual-port RAM corresponding to the remainder obtained by performing a modulo operation on the number of convolutional encoders using the received interleaved read address during the read cycle; each interleaving operation unit sends its generated two interleaved data to the ping-pong read / write gating module.

[0038] Step 7.4: Clear the encoded data in the interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal;

[0039] Step 7.5: The ping-pong read / write gating module combines the two sets of multi-channel interleaved data generated by the two sets of interleaving operation units into one set of multi-channel interleaved data; the ping-pong read / write gating module outputs the combined multi-channel interleaved data in parallel, completing one interleaving operation;

[0040] Step 8: Perform interleaved read / write operations with synchronous switching using dual-port RAM.

[0041] Step 8.1: The interleaving operation unit group controlled by the Y-channel ping-pong read / write strobe signal is in a write cycle and synchronously executes the interleaving write operation described in step 4 within one read / write cycle;

[0042] Step 8.2: The interleaving operation unit group controlled by the Y-channel ping-pong read / write strobe signal switches to the read cycle in the next read / write cycle and performs the operation described in step 7.

[0043] Step 8.3: The interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal switches to the write cycle in the next read / write cycle and synchronously executes the operation described in step 4 within one read / write cycle;

[0044] Step 9, the system stops working:

[0045] When the convolutional coding module stops generating data, the system stops working after performing the operation described in step 7 on the last interleaving operation unit group containing uninterleaved data.

[0046] Compared with the prior art, the present invention has the following advantages:

[0047] First, the method of the present invention generates two puncture valid identifier signals and generates an interleaved write address based on the puncture valid identifier signals, which avoids parallel-to-serial conversion and overcomes the disadvantage of high clock speed caused by the parallel-to-serial conversion required by traditional convolutional coding methods, thereby reducing the complexity of convolutional coding methods.

[0048] Secondly, the method of the present invention uses dual-port ROM to generate interleaved read addresses and dual-port RAM to perform interleaved read and write operations, so that up to two bits of data can be written or read in the same clock cycle. This overcomes the shortcomings of the traditional parallel interleaving method, which can only store one bit of data in the same clock cycle and cannot adapt to the two-way output of convolutional coding. This makes the method of the present invention meet the input requirements of convolutional coding data stream.

[0049] Third, the system of the present invention uses ping-pong read / write strobe signals to select data and addresses, and constructs two sets of interleaving operation unit groups with identical structures. Each set of interleaving operation unit groups can independently meet the write and read requirements. The two sets of interleaving operation unit groups alternate synchronously and continuously read and write without waiting or buffering for a single high-speed encoded data stream. This overcomes the disadvantage of the ping-pong structure used in traditional interleaving systems, which has the problem of data writing waiting when the input data to be read in the first unit has not yet been read. This enables the system of the present invention to meet the high throughput requirements of the system.

[0050] Third, the system of the present invention, through the above modifications to the convolutional coding method and the interleaving method, enables the entire system to be driven by only one low-speed operating clock, meeting the system's low clock requirements and effectively improving the system's reliability. Attached Figure Description

[0051] Figure 1 This is a block diagram of the overall structure of the system of the present invention;

[0052] Figure 2 This is a timing block diagram for generating the A and B interleaved write addresses in this invention;

[0053] Figure 3 This is a timing block diagram for generating the X and Y channel ping-pong read / write strobe signals of the present invention;

[0054] Figure 4 This is a timing block diagram for ROM address generation in this invention;

[0055] Figure 5 This is a structural block diagram of the interleaving operation unit of the system of the present invention;

[0056] Figure 6 This is a schematic diagram illustrating the correspondence between the remainder and the output result of the dual-port RAM in this invention.

[0057] Figure 7 This is an overall flowchart of the method of the present invention;

[0058] Figure 8 This is a mapping diagram of the interleaved read address distribution method of the present invention; Detailed Implementation

[0059] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] The digital modulation scheme of this invention is 64QAM, and the interleaving depth is 512. With a fixed number of hardware modules, this invention has backward compatibility by enabling each sub-module. For example, a hardware module structure supporting 64QAM digital modulation can also implement BPSK, QPSK, and 16QAM interleaving operations by enabling each sub-module. This invention is easily scalable by increasing the number of hardware modules. If support for 256QAM is required, it can be achieved simply by increasing the number of hardware modules.

[0061] Reference Figure 1 The system of the present invention will be described in further detail below.

[0062] The system of this invention includes a convolutional coding module, an interleaving write address generation module, an interleaving read address generation module, two sets of interleaving operation unit groups, and a ping-pong read / write gating module. All modules are developed using a graphical approach. Among them:

[0063] The convolutional coding module includes six convolutional encoders and one punching module. Each convolutional encoder encodes data according to the system's encoding rules, obtaining two encoded data streams, A and B. Convolutional encoder 0 is selected, and its corresponding A and B encoded data streams are sent to the valid flag module. The 12 encoded data streams from the six convolutional encoders are sent to the ping-pong read / write gating module. The punching module is used to mark the valid punched data after punching the A and B encoded data streams. The two valid flag signals are sent to the interleaved write address generation module.

[0064] The interleaving write address generation module is used to, upon receiving the A and B puncture valid flag signals, such as Figure 2 As shown, during the clock cycles when the puncture valid flag signals A and B are high, two parallel interleaved write addresses are generated. The interleaved write address corresponding to the puncture valid flag signal A is... Figure 2 The A-channel interleaving write address is incremented starting from 0, accumulating once per high-level clock cycle, with each increment being 2 interleaving write addresses; the B-channel punch valid flag signal corresponds to the interleaving write address... Figure 2 The B-channel interleaved write address is incremented starting from 1, and is incremented once every high-level clock cycle, with a total increment of 2 interleaved write addresses; the two interleaved write addresses are then sent to the ping-pong read / write gating module.

[0065] The ping-pong read / write gating module is used to start upon receiving multi-channel encoded data. At this time, the reference... Figure 3 The system uses the maximum write time as the read / write cycle and generates two ping-pong read / write strobe signals, X and Y. In the first read / write cycle, X is in the write cycle and Y is in the read cycle. In the next read / write cycle, X is in the read cycle and Y is in the write cycle, thus achieving signal selection and repetition control until the system stops operating. The X and Y ping-pong read / write strobe signals within the read / write cycle are sent to the interleaved read address generation module. The X ping-pong read / write strobe signals within the read / write cycle are sent to one set of interleaving operation units, and the Y ping-pong read / write strobe signals within the read / write cycle are sent to another set of interleaving operation units. Upon receiving encoded data and the interleaved write address, only the interleaved write address and encoded data are sent to the interleaved operation unit group in the write cycle. Each interleaved operation unit in the interleaved operation unit group outputs two interleaved write addresses and multiple encoded data. Upon receiving the interleaved read address, only the interleaved read address is sent to the interleaved operation unit group in the read cycle, as per reference. Figure 7Different two-way interleaving read addresses are distributed to different interleaving operation units in each interleaving operation group. The two sets of multi-way interleaved data generated by the two sets of interleaving operation units are combined into one set of multi-way interleaved data; the ping-pong read / write gating module outputs the combined multi-way interleaved data in parallel, completing one interleaving operation.

[0066] The interleaved read address generation module includes three dual-port address ROMs, used to, after receiving the first read cycle of the X and Y channel strobe control signals, refer to... Figure 4 The ROM read address generation begins for the first time and continues once per read / write cycle. Each cycle generates two ROM read addresses: the first ROM address starts at address 0 and increments by two addresses per clock cycle; the second ROM address starts at address 1 and increments by two addresses per clock cycle. For each dual-port address ROM, based on the same two ROM addresses, the interleaved read addresses initialized according to the system interleaving formula and stored in the dual-port address ROM are read out in parallel via two separate paths. These multiple interleaved read addresses are then sent to the ping-pong read / write gating module.

[0067] The interleaving operation unit, referenced Figure 5 It contains six dual-port RAMs. During a write cycle after receiving two interleaved write addresses and multi-channel encoded data, it writes different two-channel encoded data to each dual-port RAM within the same interleaving operation unit, using the same two-channel interleaved write address. For different interleaving operation units within the same group, at the same time as the write operations of the aforementioned interleaving operation units, it performs write operations on its respective dual-port RAMs with the same address and encoded data as the write operations of the aforementioned interleaving operation units. During a read cycle, the RAM read address is obtained by arithmetic left shifting the interleaved read address by 3 bits, where N... bit =log2 N RAM N RAM This indicates the number of dual-port RAMs in the interleaving operation unit; within a read cycle, for each dual-port RAM within the same interleaving operation unit, two interleaved data streams are read out using the same two RAM read addresses. (Reference) Figure 6 The received interleaving read address is used to perform a modulo operation on the number of convolutional encoders. In terms of hardware implementation techniques, taking a digital modulation order of 64 as an example, the interleaving read address is denoted as Addr_Rd. The lower 3 bits of the interleaving read address, i.e., Addr_Rd[2:0], are taken as the remainder. Then, based on the remainder, the two interleaved data streams read from the corresponding dual-port RAM are selected from the six dual-port RAMs. Each interleaving operation unit sends its two generated interleaved data streams to the ping-pong read / write gating module. The encoded data in the interleaving operation unit group controlled by the X-channel ping-pong read / write gating signal is cleared.

[0068] Reference Figure 7 The implementation steps of the embodiments of the method of the present invention will be further described below.

[0069] Step 1: Send the generated 12-channel encoded data and two-channel punch valid indicator signals.

[0070] Step 1.1: Each convolutional encoder in the convolutional coding module encodes data according to the system's encoding rules, obtaining two encoded data streams, A and B; the number of convolutional encoders N... conv =log2X, where X represents the digital modulation order; N is the number of encoded data channels. coded The number of convolutional encoders, N conv Twice; taking a digital modulation order X equal to 64 as an example, the number of convolutional encoders N conv Equals 6, number of encoded data paths N coded It equals 12.

[0071] Step 1.2: Randomly select a convolutional encoder and send its corresponding A and B encoded data to the valid identifier module. Different convolutional encoders have the same punching rules, so only one convolutional encoder needs to be randomly selected. Generally, convolutional encoder 0 can be selected.

[0072] Step 1.3: Send the 12 channels of encoded data generated by the 6 convolutional encoders into the ping-pong read / write gating module;

[0073] Step 1.4: The puncturing module in the convolutional coding module marks the valid punctured data after puncturing the A and B encoded data respectively. By performing the valid marking operation, the operation of converting the two punctured data from parallel to serial is avoided in the traditional puncturing process. The two valid marking signals are sent to the interleaving and writing address generation module.

[0074] Step 2: Send the two interleaved write addresses generated based on the punch valid flag signal.

[0075] Step 2.1, after receiving the A and B puncture valid flag signals, the interleaving write address generation module refers to... Figure 2 During the clock cycles when the puncture valid flag signals A and B are high, two parallel interleaved write addresses are generated. The interleaved write address corresponding to the puncture valid flag signal A corresponds to... Figure 2 The A-channel interleaving write address is incremented starting from 0, accumulating once per high-level clock cycle, with each increment being 2 interleaving write addresses; the B-channel punch valid flag signal corresponds to the interleaving write address... Figure 2 The B-channel interleaved write address is incremented starting from 1, and is incremented once every high-level clock cycle, with a total increment of 2 interleaved write addresses per cycle.

[0076] Step 2.2: The interleaved write address generation module sends the two interleaved write addresses to the ping-pong read / write gating module.

[0077] Step 3: Send the generated ping-pong read / write strobe signal and select the strobe-encoded data and the interleaved write address:

[0078] Step 3.1: Upon receiving multi-channel encoded data, the ping-pong read / write gating module starts up. (Refer to...) Figure 3 At this point, the system's maximum write time is used as the read / write cycle. Simultaneously, two ping-pong read / write strobe signals, X and Y, are generated. In the first read / write cycle, X is in the write cycle and Y is in the read cycle. In the next read / write cycle, X is in the read cycle and Y is in the write cycle, thus achieving signal selection and repetition control until the system stops operating. In the first read / write cycle, since no encoded data is pre-written in the interleaving operation unit, the interleaving read operation within the read cycle is meaningless; only the interleaving write operation of the write cycle needs to be performed. In the last read / write cycle, since the end of the encoded data has already been pre-written in the previous read / write cycle, the write cycle within this cycle is meaningless; only the interleaving read operation of the read cycle needs to be performed. In the other read / write cycles excluding the first and last ones, X and Y switch synchronously for continuous read / write, which can adapt to the requirements of high-throughput data streams.

[0079] Under the control of the ping-pong read / write strobe signal, all modules in the write cycle cooperate to complete the interleaved write process, and all modules in the read cycle cooperate to complete the interleaved read process. The system operation steps are exactly the same in different write cycles and in different read cycles.

[0080] The number of interleaving operation units N in the two groups of interleaving operation units unit They are equal, both equal to the number of convolutional encoders N. conv Half of that. Figure 8 As shown, the number of interleaving operation units N unit It equals 3.

[0081] Step 3.2: Send the X and Y channel ping-pong read / write strobe signals during the read / write cycle to the interleaved read address generation module.

[0082] Step 3.3: Send the X-channel ping-pong read / write strobe signal during the read / write cycle to one set of interleaving operation units, and send the Y-channel ping-pong read / write strobe signal during the read / write cycle to another set of interleaving operation units.

[0083] Step 3.4: After receiving the encoded data and the interleaving write address, the ping-pong read / write gating module only sends the interleaving write address and encoded data to the interleaving operation unit group that is in the write cycle, and outputs two interleaving write addresses and 12 encoded data to each interleaving operation unit in the interleaving operation unit group.

[0084] Step 4: Use dual-port RAM to perform interleaved write operations.

[0085] Step 4.1: Within the write cycle after receiving two interleaving write addresses and 12 coded data, the interleaving operation units in the interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal write different coded data to each dual-port RAM within the same interleaving operation unit, using the same two-channel interleaving write addresses. For different interleaving operation units in the same group, at the same time as the above interleaving operation unit's write operation, they perform write operations on their respective dual-port RAMs with the same addresses and coded data as the above interleaving operation unit's write operation. After the interleaving write operation is completed, each dual-port RAM stores the merged coded data of channels A and B, and the six dual-port RAMs store the coded data corresponding to the six convolutional encoders. All dual-port RAMs within the same interleaving operation unit constitute a complete coded dataset. Different interleaving operation units store the same complete coded dataset.

[0086] Step 5: Send the multi-interleaved read address generated using the dual-port ROM.

[0087] Step 5.1: After receiving the X and Y channel strobe control signals in the first read cycle, the ROM read address begins to be generated for the first time, and is generated once per read / write cycle. (Refer to...) Figure 4 Each time, two ROM read addresses are generated. The first ROM address starts at 0 and is incremented once per clock cycle, with a total increment of 2 ROM addresses. The second ROM address starts at 1 and is incremented once per clock cycle, with a total increment of 2 ROM addresses.

[0088] Step 5.2 In each dual-port address ROM of the interleaving read address generation module, based on the same two ROM addresses, the interleaving read addresses initialized and stored in the dual-port address ROM according to the system interleaving formula are read out in parallel on two separate paths; the data depth D of each dual-port address ROM is... data It is the interlacing depth D interweave Twice the number of address ROMs N ROM The number of convolutional encoders, N conv Half of; Number of parallel interleaved read addresses N addr The number of address ROMs, N ROM Twice that; taking 64QAM digital modulation and an interleaving depth of 512 as an example, the data depth D of each dual-port address ROM in this module is...data Equals 1024, the number of address ROMs N ROM An equal value of 3 generates 6 parallel interleaved addresses.

[0089] Step 5.3 The interleaved read address generation module sends the 6 interleaved read addresses to the ping-pong read / write gating module.

[0090] Step 6: Select and interleave the address according to the ping-pong read / write strobe signal.

[0091] After receiving the interleaved read address, the ping-pong read / write gating module only sends the interleaved read address to the interleaved operation unit group that is in the read cycle, and distributes different two interleaved read addresses to different interleaved operation units in each interleaved operation group. (Reference) Figure 8 After distribution, the two interleaving read addresses received by each interleaving operation unit and the two interleaving read addresses read by each dual-port ROM are paired.

[0092] Step 7: Use dual-port RAM to perform interleaved read operations and send the combined interleaved data.

[0093] Step 7.1: The interleaving operation unit in the interleaving operation unit group, controlled by the X-channel ping-pong read / write strobe signal, performs an arithmetic left shift N of the interleaving read address during the read cycle. bit The bits are used to obtain the RAM read address, where N bit =log2 N RAM N RAM This indicates the number of dual-port RAMs in the interleaving operation unit; in this embodiment of the invention, the digital modulation order is 64, therefore N bit It equals 3.

[0094] Step 7.2: The interleaving operation unit in the interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal reads out two interleaved data channels respectively according to the same two-channel RAM read address in each dual-port RAM in the same interleaving operation unit during the read cycle; the three interleaving operation units generate six interleaved data channels.

[0095] Step 7.3: The interleaving operation unit in the interleaving operation unit group, controlled by the X-channel ping-pong read / write strobe signal, outputs the remainder obtained by performing a modulo operation on the number of convolutional encoders using the received interleaving read addresses within the read cycle, corresponding to the two interleaved data read from the dual-port RAM. (Reference) Figure 6The received interleaving read address is used to perform a modulo operation on the number of convolutional encoders. In terms of hardware implementation techniques, taking a digital modulation order of 64 as an example, the interleaving read address is denoted as Addr_Rd. The lower 3 bits of the interleaving read address, i.e., Addr_Rd[2:0], are taken as the remainder. Then, based on the remainder, the two interleaved data channels read from the dual-port RAM corresponding to the remainder are selected from the six dual-port RAMs. Each interleaving operation unit sends its two generated interleaved data channels into the ping-pong read / write gating module.

[0096] Step 7.4: Clear the encoded data in the interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal.

[0097] Step 7.5: The ping-pong read / write gating module combines the two sets of 6-channel interleaved data generated by the two sets of interleaving operation units into one set of 6-channel interleaved data; the ping-pong read / write gating module outputs the combined 6-channel interleaved data in parallel, completing one interleaving operation.

[0098] Step 8: Use dual-port RAM to perform synchronous switching interleaved read and write operations.

[0099] Step 8.1: The interleaving operation unit group controlled by the Y-channel ping-pong read / write strobe signal is in a write cycle and synchronously executes the interleaving write operation described in step 4 within one read / write cycle.

[0100] Step 8.2: The interleaving operation unit group controlled by the Y-channel ping-pong read / write strobe signal switches to the read cycle in the next read / write cycle and performs the operation described in step 7.

[0101] Step 8.3: The interleaving operation unit group controlled by the X-channel ping-pong read / write strobe signal switches to the write cycle in the next read / write cycle and synchronously executes the operation described in step 4 within one read / write cycle.

[0102] Step 9: The system stops working.

[0103] When the convolutional coding module stops generating data, the system stops working after performing the operation described in step 7 on the last interleaving operation unit group containing uninterleaved data.

Claims

1. A parallel interleaving system for multi-path convolutional encoding, comprising a convolutional encoding module, an interleaving write address generation module, an interleaving read address generation module, two groups of interleaving operation unit groups, characterized in that, It also includes ping-pong read-write gating module, all modules are developed in graphical way; wherein: The convolutional encoding module comprises N conv convolutional encoders and a puncturing module, wherein each convolutional encoder encodes according to a system encoding rule to obtain two-channel encoded data A and B; a convolutional encoder is randomly selected, and the corresponding two-channel encoded data A and B are sent to a valid identification module; the encoded data of all convolutional encoders are sent to a ping-pong read-write gating module; the puncturing module is used for valid identification of effective punctured data after puncturing operation on the two-channel encoded data A and B; two-channel valid identification signals are sent to an interleaving write address generation module; The interleaving write address generation module is used for generating two parallel interleaving write addresses after receiving the A and B two-punch Valid identification signals, and the interleaving write addresses corresponding to the A two-punch Valid identification signals are accumulated from 0, once every high-level clock cycle, and two interleaving write addresses are accumulated at a time; the interleaving write addresses corresponding to the B two-punch Valid identification signals are accumulated from 1, once every high-level clock cycle, and two interleaving write addresses are accumulated at a time; and the two interleaving write addresses are sent to the ping-pong read-write gating module; The ping-pong read-write gating module is used for starting after receiving the multiple encoding data, at this time, the maximum write time of the system is taken as the read-write cycle, and the X and Y two-ping-pong read-write gating signals are generated, in the first read-write cycle, the X road is in the write cycle, and the Y road is in the read cycle, in the next read-write cycle, the X road is in the read cycle, and the Y road is in the write cycle, so as to realize the reciprocal control of the signal gating, until the system stops operating; the X and Y two-ping-pong read-write gating signals in the read-write cycle are sent to the interleaving read address generation module; the X two-ping-pong read-write gating signal in the read-write cycle is sent to a group of interleaving operation units, and the Y two-ping-pong read-write gating signal in the read-write cycle is sent to another group of interleaving operation units; after receiving the encoding data and the interleaving write address, only the interleaving operation unit group in the write cycle is sent to the interleaving write address and the encoding data, and two interleaving write addresses and multiple encoding data are output for each interleaving operation unit in the interleaving operation unit group; after receiving the interleaving read address, only the interleaving operation unit group in the read cycle is sent to the interleaving read address, and different two interleaving read addresses are distributed to different interleaving operation units in each interleaving operation group; two groups of multiple interleaving data generated by the two groups of interleaving operation units are combined into one group of multiple interleaving data; the multiple interleaving data after the combination is output in parallel by the ping-pong read-write gating module, and one interleaving operation is completed; The interleaving read address generating module comprises N ROM double-port address ROMs, which are used to generate the first read address after receiving the first read cycle of the X and Y path gating control signals, generate one read address in each read-write cycle, generate two read addresses in each time, the initial address of the first read address is 0, is added by 2 in each clock cycle, the initial address of the second read address is 1, is added by 2 in each clock cycle; each double-port address ROM reads out the interleaving read addresses initialized and stored in the double-port address ROM according to the same two read addresses according to the system interleaving formula; and the multiple interleaving read addresses are sent to the ping-pong read-write gating module. The interleaving operation unit comprises N RAM two-port RAMs, which are used to write different two-way encoded data into each two-port RAM in the same interleaving operation unit according to the same two-way interleaving write address in a write cycle after receiving the two-way interleaving write address and the multi-way encoded data; at the same time of the write operation of the interleaving operation unit, the same two-way write operation is performed on the two-port RAMs in different interleaving operation units in the same group; in a read cycle, the RAM read address is obtained by performing left shift operation on the interleaving read address by N bit bits, wherein N bit =log2N RAM , N RAM represents the number of two-port RAMs in the interleaving operation unit; in the read cycle, two-way interleaving data is read out from each two-port RAM in the same interleaving operation unit according to the same two-way RAM read address; in the read cycle, the two-way interleaving data read out from the two-port RAM corresponding to the remainder obtained by performing modulo operation on the number of convolution encoders with the received interleaving read address is output; each interleaving operation unit sends the two-way interleaving data generated by itself into the ping-pong read-write gating module; and the encoded data in the interleaving operation unit group controlled by the X-way ping-pong read-write gating signal is emptied.

2. The method for parallel interleaving for multi-path convolutional encoding of the system of claim 1, wherein, The two-punch valid identification signals are generated, the interleaving write addresses are generated according to the punch valid identification signals, the interleaving read addresses are generated by using the dual-port ROM, and the interleaving read-write operation is performed by using the dual-port RAM, and the data and the address are gated according to the ping-pong read-write gating signal, and the specific steps of the method include the following: Step 1, the generated multiple encoding data and two-punch valid identification signals are sent: Step 1.1, each convolutional encoder in the convolutional encoding module encodes according to the system encoding rule to obtain A and B two encoding data; Step 1.2, a convolutional encoder is randomly selected, and the A and B two encoding data corresponding to the convolutional encoder are sent to the valid identification module; Step 1.3, the encoding data of all convolutional encoders are sent to the ping-pong read-write gating module; Step 1.4, the puncturing module in the convolutional encoding module respectively marks the valid punctured data after puncturing operation on the two-channel encoded data A and B; the two-channel valid signals are sent to the interleaving write address generating module; Step 2, send the two-channel interleaving write addresses generated according to the puncturing valid signals; Step 2.1, the interleaving write address generating module generates two-channel parallel interleaving write addresses in the clock cycle when the two-channel puncturing valid signals are high after receiving the two-channel puncturing valid signals; the interleaving write address corresponding to the A-channel puncturing valid signal starts from 0 and is accumulated by 2 in each high clock cycle; the interleaving write address corresponding to the B-channel puncturing valid signal starts from 1 and is accumulated by 2 in each high clock cycle; Step 2.2, the interleaving write address generating module sends the two-channel interleaving write addresses to the ping-pong read-write gating module; Step 3, send the generated ping-pong read-write gating signals and gate the encoded data and the interleaving write addresses; Step 3.1, the ping-pong read-write gating module starts after receiving the multi-channel encoded data; at this time, the maximum write time of the system is taken as the read-write cycle, and the X and Y two-channel ping-pong read-write gating signals are generated; in the first read-write cycle, the X channel is in the write cycle and the Y channel is in the read cycle; in the next read-write cycle, the X channel is in the read cycle and the Y channel is in the write cycle; thus the signal gating and reciprocating control are realized until the system stops operating; Step 3.2, send the X and Y two-channel ping-pong read-write gating signals in the read-write cycle to the interleaving read address generating module; Step 3.3, send the X-channel ping-pong read-write gating signal in the read-write cycle to one group of interleaving operation units, and send the Y-channel ping-pong read-write gating signal in the read-write cycle to another group of interleaving operation units; Step 3.4, after receiving the encoded data and the interleaving write addresses, the ping-pong read-write gating module sends the interleaving write addresses and the encoded data to the interleaving operation unit group in the write cycle, and outputs two-channel interleaving write addresses and multi-channel encoded data for each interleaving operation unit in the interleaving operation unit group; Step 4, use dual-port RAM for interleaving write operation: Step 4.1, the interleaving operation unit in the X-channel ping-pong read-write gating signal controlled interleaving operation unit group writes different two-channel encoded data into each dual-port RAM in the same interleaving operation unit according to the same two-channel interleaving write addresses in the write cycle after receiving the two-channel interleaving write addresses and the multi-channel encoded data; at the same time of the write operation of the above interleaving operation unit, the dual-port RAM of each interleaving operation unit in the same group performs the same write operation as the above interleaving operation unit; Step 5, send the multi-channel interleaving read addresses generated by using dual-port ROM: Step 5.1 After receiving the first read cycle of the X, Y road gating control signal, the ROM read address starts to generate for the first time, and generates once every read-write cycle, and generates two road ROM read addresses each time, the first road ROM address is initially 0, and is accumulated once every clock cycle, and is accumulated by 2 ROM addresses once, the second road ROM address is initially 1, and is accumulated once every clock cycle, and is accumulated by 2 ROM addresses once; Step 5.2 Each dual-port address ROM in the interleaved read address generation module reads the interleaved read address initialized and stored in the dual-port address ROM according to the same two road ROM addresses according to the system interleaving formula; Step 5.3 The interleaved read address generation module sends the multiple interleaved read addresses to the ping-pong read-write gating module; Step 6, according to the ping-pong read-write gating signal to select the interleaved read address: The ping-pong read-write gating module sends the interleaved read address to the interleaved operation unit group in the read cycle after receiving the interleaved read address, and distributes different two-way interleaved read addresses to different interleaved operation units of each interleaved operation group; Step 7, using dual-port RAM to perform interleaved read operation and sending the combined interleaved data: Step 7.1, interleaving operation unit in the group of interleaving operation units controlled by X-bounce ping read-write selection signals, obtains RAM read address by performing arithmetic left shift of interleaving read address by N bit bits in the read cycle, wherein N bit = log2N RAM , N RAM represents the number of dual-port RAMs in the interleaving operation unit; Step 7.2, the interleaved operation unit in the X road ping-pong read-write gating signal controlled interleaved operation unit group reads out two-way interleaved data from each dual-port RAM in the same interleaved operation unit according to the same two-way RAM read address in the read cycle; Step 7.3, the interleaved operation unit in the X road ping-pong read-write gating signal controlled interleaved operation unit group outputs the two-way interleaved data read out by the dual-port RAM corresponding to the remainder obtained by performing modulo operation on the number of convolution encoders with the received interleaved read address in the read cycle; Each interleaved operation unit sends the two-way interleaved data generated by itself to the ping-pong read-write gating module; Step 7.5, clear the encoding data in the X road ping-pong read-write gating signal controlled interleaved operation unit group; Step 7.6, the ping-pong read-write gating module combines the two sets of multiple interleaved data generated by the two interleaved operation unit groups into one set of multiple interleaved data; the ping-pong read-write gating module outputs the combined multiple interleaved data in parallel to complete an interleaved operation; Step 8, using dual-port RAM to perform synchronous switching interleaved read-write operation: Step 8.1, the Y road ping-pong read-write gating signal controlled interleaved operation unit group is in the write cycle, and the interleaved write operation described in step 4 is executed synchronously in a read-write cycle; Step 8.2, the Y road ping-pong read-write gating signal controlled interleaved operation unit group switches to the read cycle in the next read-write cycle, and executes the operation described in step 7; Step 8.3, the X road ping-pong read-write gating signal controlled interleaved operation unit group switches to the write cycle in the next read-write cycle, and executes the operation described in step 4 synchronously in a read-write cycle; Step 9, the system stops working: When the convolution encoding module stops generating data, the system stops working after the operation described in step 7 is performed on the last interleaved operation unit group having uninterleaved data.

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