Semiconductor devices

Abstract

The semiconductor device (100) disclosed in the present invention comprises a semiconductor chip (130) having a protruding terminal (14) that is conductive with a transistor (13) and has a larger cross-sectional area than a bonding wire (4), and an insulating short-circuit prevention side wall (15) that covers the side surface facing the periphery thereof. The semiconductor chip (130) is bonded to the upper surface (3) of a metal plate (2) by a conductive bonding material (6). A conductor pattern (34a) formed on a circuit substrate (30) bonded to the upper surface (3) of the metal plate (2) and an end of the protruding direction of the protruding terminal (14) are connected by a bonding wire (4).

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices for amplifying power at high frequencies. Background Art

[0002] With the start of fifth-generation mobile communication system services, high-frequency amplifiers used in base stations are required to be miniaturized and have higher output. As a form of high-frequency amplifier, there is a tendency to miniaturize the entire RF front-end circuit of the base station by integrating high-output transistors, matching circuits, and functional circuits into one amplifier module. In addition, a plan to reduce the number of antennas and miniaturize the base station by implementing high-output amplifier modules is also being studied.

[0003] When implementing modularization of high-output transistors, the module needs a mechanism to release the heat generated by the transistor. The heat dissipation mechanism is usually a structure that dissipates heat from the back of the semiconductor chip formed with the transistor to the back of the package. In order to improve the heat dissipation, a metal plate with low thermal resistance is used on the back of the package. In order to reduce the thermal resistance, the semiconductor chip is not mounted on the substrate, but directly bonded to the metal plate.

[0004] On the other hand, from the perspective of miniaturization of the entire RF front-end circuit, in addition to the matching circuit and bias circuit required for amplifier operation, functional circuits such as bias control circuits tend to be integrated into the amplifier module. In this case, although the circuit scale becomes larger and a complex wiring layout is required, miniaturization is achieved by multi-layering the amplifier module substrate.

[0005] For example, patent document 1 discloses a semiconductor packaging device comprising: a ceramic multilayer substrate having wiring formed into multiple layers; a metal base, wherein the ceramic multilayer substrate is arranged on a portion of the surface; at least one semiconductor element is arranged on the ceramic multilayer substrate; at least one semiconductor element is arranged on the metal base; and a cover for sealing the semiconductor element on the ceramic multilayer substrate and the semiconductor element on the metal base.

[0006] Here, in order to achieve further high output, it is effective to reduce thermal resistance by thinning the semiconductor chip so as to efficiently dissipate heat from the transistor on the surface of the semiconductor chip for the power amplifier arranged on the metal substrate. In addition, in order to achieve further miniaturization, it is effective to further multilayer the multilayer substrate.

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 7-50386

[0008] However, if the semiconductor chip is made thinner for high output, there is a possibility that the chip bonding material will climb to the upper surface of the semiconductor chip. As a chip bonding material for semiconductor chips, the usual silver paste has electrical conductivity. In addition, the solder that exhibits lower thermal resistance than silver paste is metal and has electrical conductivity. Here, if the chip bonding material reaches the terminal formed on the upper surface of the semiconductor chip, a fatal adverse situation will occur in which the terminal and the metal substrate are short-circuited via the chip bonding material.

[0009] In addition, the increase in the number of layers of the multi-layer substrate generally leads to a thicker substrate, and combined with the thinner semiconductor chip, the height difference between the semiconductor chip and the multi-layer substrate increases. As a result, the wire that electrically connects the semiconductor chip to the multi-layer substrate becomes longer. Since the increase in wire length increases the inductance component, there is a problem of deteriorating high-frequency characteristics. Summary of the invention

[0010] The present disclosure is made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device that can avoid terminal short-circuit defects caused by chip bonding materials climbing to the upper surface of the semiconductor chip and reduce the thermal resistance of the transistor even when the semiconductor chip is thinned.

[0011] Another object is to provide a semiconductor device that suppresses increase in inductance components and thus suppresses degradation in high-frequency characteristics even when a line becomes longer due to an increase in substrate thickness or a reduction in the thickness of a semiconductor chip.

[0012] The semiconductor device disclosed in the present invention comprises: a semiconductor chip, comprising: a semiconductor substrate, having a first main surface and a first back surface facing each other; a transistor formed on the first main surface; a protruding terminal, which is conductive with the transistor and protrudingly formed on the first main surface; and an insulating side wall for preventing short circuit, which covers the side surface of the protruding terminal facing the semiconductor substrate and is arranged on the peripheral portion of the first main surface; a circuit substrate, having a second main surface and a second back surface facing each other, and a conductor pattern formed on the second main surface; a metal plate, having an upper surface, the first back surface being bonded to the upper surface by a conductive bonding material, and the second back surface being bonded to the upper surface; and a bonding wire, which connects the end of the protruding direction of the protruding terminal to the conductor pattern. Here, the protruding terminal has a larger cross-sectional area than the bonding wire.

[0013] According to the present disclosure, a protruding terminal having a larger cross-sectional area than a bonding wire is formed protrudingly on the main surface of a semiconductor substrate, and the side surface of the protruding terminal facing the periphery of the semiconductor substrate is covered by an insulating short-circuit prevention side wall. Furthermore, the end of the protruding terminal in the protruding direction is connected to a conductor pattern formed on a circuit substrate by a bonding wire.

[0014] Therefore, even when the semiconductor substrate is made thinner, it is possible to avoid short-circuit failure of the terminal caused by the die-bonding material creeping up the main surface of the semiconductor substrate, thereby reducing the thermal resistance of the transistor.

[0015] In addition, even when the line length is increased due to an increase in the thickness of the circuit board or a reduction in the thickness of the semiconductor chip, an increase in the inductance component is suppressed, thereby suppressing the degradation of the high-frequency characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 (a) and (b) are a plan view and a cross-sectional view of the semiconductor chip 110 according to the first embodiment.

[0017] Figure 2 1 is a plan view of the semiconductor device 100 according to the first embodiment.

[0018] Figure 3 It is a bottom view of the semiconductor device 100 according to the first embodiment.

[0019] Figure 4 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment.

[0020] Figure 5 (a) to (c) are a top view, a bottom view, and a cross-sectional view of a cover substrate 50a according to the second embodiment.

[0021] Figure 6 (a) and (b) are a top view and a cross-sectional view of a semiconductor device 200 according to the second embodiment.

[0022] Figure 7 (a) and (b) are a top view and a cross-sectional view of the semiconductor chip 130 according to the third embodiment.

[0023] Figure 8 (a) to (c) are a top view, a bottom view, and a cross-sectional view of a cover substrate 50b according to the third embodiment.

[0024] Fig. 9 (a) and (b) are a top view and a cross-sectional view of a semiconductor device 300 according to the third embodiment.

[0025] Fig.10 (a) to (c) are a top view, a bottom view, and a cross-sectional view of a cover substrate 50c according to the fourth embodiment.

[0026] Fig.11 It is a cross-sectional view of a semiconductor device 400 according to the fourth embodiment. DETAILED DESCRIPTION

[0027] A semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and duplicate descriptions may be omitted.

[0028] Implementation Method 1

[0029] The semiconductor chip 110 according to the first embodiment of the present disclosure will be described.

[0030] Figure 1 (a) and (b) are a top view and a cross-sectional view of the semiconductor chip 110 according to the first embodiment of the present disclosure. Figure 1 (a) is a top view of the semiconductor chip 110 as viewed from above. Figure 1 (b) is from Figure 1 (a) is a cross-sectional view of the semiconductor chip 110 observed from the AA position.

[0031] The semiconductor chip 110 includes a semiconductor substrate 10 , a transistor 13 , a protruding terminal 14 , and a short-circuit preventing sidewall 15 .

[0032] The semiconductor substrate 10 has a first main surface 11 and a first back surface 12 opposite to the first main surface 11. The semiconductor substrate 10 is a nitride semiconductor including GaN (gallium nitride) stacked on a SiC (Silicon Carbide) substrate. The thickness of the semiconductor substrate 10 is 50 μm, which is thinner than a conventional semiconductor substrate having a thickness of about 100 μm.

[0033] A transistor 13 for amplifying high-frequency power and matching circuits 20 and 20b are formed on the first main surface 11 of the semiconductor substrate 10. The matching circuits 20 and 20b are formed of microstrip lines.

[0034] Transistor 13 is Figure 1 The transistor 13 and the matching circuits 20 and 20b are schematically shown in (a). Figure 1 It is not shown in (b) and other cross-sectional views to be described later.

[0035] The transistor 13 is a multi-finger HEMT (High Electron Mobility Transistor) and has a gate, a drain, and a source.

[0036] The source of the transistor 13 is connected to a metal film that blocks the opening on the first main surface 11 side of the through hole 21 formed through the semiconductor substrate 10. The metal film is connected to a multilayer film composed of multiple metals formed on the side of the through hole 21. The multilayer film is connected to a metal thin film (not shown) formed on almost the entire surface of the first back surface 12. That is, the source of the transistor 13 is connected to the metal thin film, and the metal thin film functions as a ground (GND) electrode of the semiconductor chip 110.

[0037] The gate of the transistor 13 is connected to the matching circuit 20, and the matching circuit 20 is connected to the protruding terminal 14. That is, the gate of the transistor 13 and the protruding terminal 14 are electrically connected.

[0038] The drain of the transistor 13 is connected to the matching circuit 20b, and the matching circuit 20b is connected to the protruding terminal 14b. That is, the drain of the transistor 13 is electrically connected to the protruding terminal 14b.

[0039] The protruding terminals 14 and 14b are prisms with square bottoms formed to protrude upward on the first main surface 11 of the semiconductor substrate 10. The height H of the protruding terminals 14 and 14b is 250 μm. The material of the protruding terminals 14 and 14b is gold.

[0040] The bottom surface of the protruding terminals 14 and 14b in contact with the first main surface 11 is a square with a side length of 100 μm. The bottom surface on the opposite side, that is, the bottom surface of the end 23 located in the protruding direction of the protruding terminal 14 and the bottom surface of the end 23b located in the protruding direction of the protruding terminal 14b are squares with a side length of 100 μm. The bottom surface of the end 23 located in the protruding direction of the protruding terminal 14 and the bottom surface of the end 23b located in the protruding direction of the protruding terminal 14b are formed flat to the extent that wire bonding can be performed. The square with a side length of 100 μm is equal to the size of a bonding pad suitable for a gold wire with a diameter of 25 μm.

[0041] The protruding terminal 14 has four side surfaces 22 a , 22 b , 22 c , and 22 d . The side surfaces 22 a , 22 b , and 22 c face the periphery of the semiconductor chip 110 , and the side surface 22 d faces the inside of the semiconductor chip 110 .

[0042] In addition, although the protruding terminals 14 and 14b in the present disclosure are quadrangular columns, they may be polygonal columns or circular columns. In addition, they may be formed of stud bumps or the like, or may have a multi-layer structure.

[0043] The short-circuit-proof side wall 15 is provided in an uninterrupted manner on the periphery of the first main surface 11 of the semiconductor substrate 10. The height H of the short-circuit-proof side wall 15 is 250 μm. The material of the short-circuit-proof side wall 15 is polyimide. Alternatively, it may be a material such as SiN, SiON, BCB (Benzocyclobutene). That is, the short-circuit-proof side wall 15 has insulating properties. The short-circuit-proof side wall 15 may also be a multilayer structure.

[0044] The short-circuit preventing side walls 15 cover three side surfaces 22 a , 22 b , and 22 c of the protruding terminal 14 that face the periphery of the semiconductor substrate 10 .

[0045] The side wall 15 for preventing short circuit does not cover the side surface 22d of the protruding terminal 14 facing the inner side of the semiconductor substrate 10. If the transistor 13 is covered with a dielectric, the high-frequency gain is reduced due to the increase in parasitic capacitance. Therefore, the upper surface of the transistor 13 is not covered by the side wall 15 for preventing short circuit. The bottom surface of the end 23 located in the protruding direction of the protruding terminal 14 is not covered by the side wall 15 for preventing short circuit, but is exposed. The side wall 15 for preventing short circuit does not cover the upper surface of the matching circuit 20 and 20b.

[0046] Here, the protruding terminal 14 connected to the gate of the transistor 13 is described. The protruding terminal 14b connected to the drain of the transistor 13 is also the same as the protruding terminal 14. That is, the three side surfaces of the protruding terminal 14b facing the periphery of the semiconductor substrate 10 are covered by the short-circuit prevention side walls 15, and the side surfaces of the protruding terminal 14b facing the inner side of the semiconductor substrate 10 are not covered. The bottom surface of the end 23b located in the protruding direction of the protruding terminal 14b is also not covered by the short-circuit prevention side walls 15, but is exposed.

[0047] In the following description, for example, regarding the circuit board 30 and other components, the structure of the drain side and the structure of the gate side are the same except for the difference in circuit constants, etc. Therefore, the description of the structure of the drain side that overlaps with the gate side is appropriately omitted.

[0048] The steps of forming the protruding terminals 14 and 14 b will be described.

[0049] First, transistors 13, matching circuits 20, through holes 21, etc. are formed on the semiconductor substrate 10. Then, the first main surface 11 of the semiconductor substrate 10 is covered with a resist. Next, the resist of the portion where the protruding terminals 14 and 14b are set is removed to open the resist. Next, the base metal is evaporated and a thick film resist is further applied. The portion of the thick film resist where the protruding terminals 14 and 14b are set is opened to expose the base metal. Next, gold is grown in the opening by electrolytic plating. Finally, the unnecessary gold, resist, and base metal are removed, thereby forming the protruding terminals 14 and 14b.

[0050] The process of forming the short-circuit preventing side wall 15 will be described.

[0051] A polyimide sheet is laminated on the first main surface 11 side of the semiconductor substrate 10. Next, the polyimide is pressed in contact with the semiconductor substrate 10 to fill the polyimide in the unevenness of the structure formed on the first main surface 11 of the semiconductor substrate 10. Next, after covering the required part with a mask and exposing the unnecessary part to light, the unnecessary part is developed and removed. Next, the remaining required part is heat-treated (cured) to form the side wall 15 for preventing short circuit.

[0052] Figure 2 is a top view of the semiconductor device 100 according to the first embodiment. Figure 3 It is a bottom view of the semiconductor device 100 according to the first embodiment. Figure 4 It is a cross-sectional view of the semiconductor device 100 according to the first embodiment. Figure 4 Shown from Figure 2 The cross section observed at the AA position.

[0053] The semiconductor device 100 includes a semiconductor chip 110 , a circuit board 30 , a metal plate 2 , and bonding wires 4 .

[0054] The circuit substrate 30 is a multilayer printed wiring board. The thickness of the circuit substrate 30 is 300 μm. The upper surface of the circuit substrate 30, that is, the surface on the insulating layer 35a side is the second main surface 31. The lower surface of the circuit substrate 30, that is, the surface on the insulating layer 35c side is the second back surface 32. The second main surface 31 and the second back surface 32 are opposite to each other.

[0055] Conductor patterns 34a, 34b, and 34c as surface conductor layers are provided on the second main surface 31 of the circuit board 30. The circuit board 30 has insulating layers 35a, 35b, and 35c. The insulating layers 35a to 35c are made of glass epoxy resin, thermosetting resin, fluororesin, and the like.

[0056] The circuit board 30 has inner layers 36 a and 36 b as inner conductor pattern layers.

[0057] The conductor patterns 34 a to 34 c , the inner layers 36 a and 36 b , the metal plate 2 , the input terminal 7 a , and the output terminal 7 b are connected to each other through vias according to the design of the semiconductor device 100 .

[0058] For example, in Figure 4In the embodiment, the conductor pattern 34a and the inner layer 36a are connected by a through hole 37a penetrating the insulating layer 35a. The inner layer 36a and the inner layer 36b are connected by a through hole 37b penetrating the insulating layer 35b. The inner layer 36b and the input terminal 7a are connected by a through hole 37c penetrating the insulating layer 35c.

[0059] The electronic component 81 is mounted and connected to the conductor patterns 34b and 34c. The electronic component 81 is an IC chip, a surface mount component, etc. There may be a plurality of electronic components 81.

[0060] The metal plate 2, the input terminal 7a and the output terminal 7b are thin metal plates made of copper and having a thickness of 0.2 mm. The upper surface 3 of the metal plate 2, the input terminal 7a and the output terminal 7b are bonded to the second back surface 32 of the circuit substrate 30. The metal plate 2 is separated from the input terminal 7a and the output terminal 7b. The separated portion can be easily formed by etching or drilling the desired area. As described later, the metal plate 2 is a ground (GND) terminal when the semiconductor device 100 is mounted on a high-frequency amplifier. The lower surfaces of the metal plate 2, the input terminal 7a and the output terminal 7b have a flatness to the extent that the semiconductor device 100 can be mounted on the high-frequency amplifier.

[0061] In plan view, a through hole 38 is formed in the middle of the circuit board 30 to penetrate the circuit board 30. The second back surface 32 side of the through hole 38 is covered by the metal plate 2. The through hole 38 portion of the circuit board 30 forms a recessed cavity 39 in top view.

[0062] The semiconductor chip 110 is mounted in the cavity 39 of the circuit substrate 30. Specifically, the first back surface 12 of the semiconductor substrate 10 constituting the semiconductor chip 110 is bonded to the upper surface 3 of the metal plate 2 in the cavity 39 using the conductive bonding material 6.

[0063] Specific examples of the bonding material 6 include conductive epoxy resin generally called silver paste, sintered silver paste having higher thermal conductivity than general silver paste, solder, and the like.

[0064] From the viewpoint of heat dissipation of the semiconductor device 100 , the thermal conductivity of the bonding material 6 is preferably high, and the thickness of the bonding material 6 is preferably thin.

[0065] The bottom surface of the end portion 23 of the protruding terminal 14 in the protruding direction is connected to the conductor pattern 34a by the bonding wire 4. That is, the end portion of the protruding terminal 14 in the protruding direction is connected to the conductor pattern 34a by the bonding wire 4. Since the conductor pattern 34a is connected to the input terminal 7a, the gate of the transistor 13 is connected to the input terminal 7a. Similarly, the drain of the transistor 13 is connected to the output terminal 7b. The length L of the bonding wire 4 in the horizontal direction is 500 μm.

[0066] The semiconductor device 100 is used in a high-frequency amplifier in a base station of a fifth-generation mobile communication system. When in use, the lower surface of the metal plate 2 is connected to the ground (GND) of the high-frequency amplifier. The lower surface of the metal plate 2 is a ground terminal of the semiconductor device 100. As described above, the source of the transistor 13 is connected to a metal film (not shown) formed on almost the entire surface of the first back surface 12 via the through hole 21. As a result, the source of the transistor 13 is conductive with the metal plate 2. By connecting the source of the transistor 13 to the metal plate 2 via the through hole 21, the source inductance of the transistor 13 is reduced, thereby improving the high-frequency characteristics of the transistor 13.

[0067] The input terminal 7a and the output terminal 7b are also connected to the high-frequency amplifier. The frequency band of the high-frequency signal input to the input terminal 7a is, for example, the frequency band number n77 (n78) (=3.6 GHz to 4.2 GHz), or n79 (=4.4 GHz to 4.9 GHz). The input high-frequency signal is amplified by the transistor 13 and output from the output terminal 7b. The maximum power of the output high-frequency signal is about 10 W. The semiconductor device 100 can also be surface mounted on the high-frequency amplifier.

[0068] Furthermore, it goes without saying that the semiconductor device 100 may have various terminals such as a bias terminal and a terminal for inputting and outputting a control signal in addition to the input terminal 7 a and the output terminal 7 b .

[0069] The transistor 13 provided on the first main surface 11 of the semiconductor substrate 10 generates heat when it operates. The generated heat is conducted from the first main surface 11 to the metal plate 2 via the semiconductor substrate 10 and the bonding material 6. The heat conducted to the metal plate 2 is further conducted to the high-frequency amplifier and discharged from the high-frequency amplifier to the outside. The metal plate 2 is also a heat dissipation terminal of the semiconductor device 100. From the viewpoint of heat dissipation of the semiconductor device 100, it is preferred that the thermal conductivity of the semiconductor substrate 10 is high, and the thickness of the semiconductor substrate 10 is preferably thin.

[0070] The following describes the function and effect of the protruding terminal 14. As described above, if the wire length of the bonding wire 4 increases, the inductance component of the wire increases, which causes a problem of deterioration of high frequency characteristics.

[0071] In the first embodiment, since the thickness of the circuit substrate 30 is set to 300 μm, the thickness of the semiconductor substrate 10 is set to 50 μm, and the height of the protruding terminal 14 is set to 250 μm, the height difference between the second main surface 31 of the circuit substrate 30 and the end 23 of the protruding terminal 14 is 0 μm. The matching circuit 20 and the conductor pattern 34a are connected by the bonding wire 4 with a height difference of 0 μm and a protruding terminal 14 with a height of 250 μm, whose starting point and end point are separated by 500 μm in the horizontal direction.

[0072] If the protruding terminal 14 is not provided, the matching circuit 20 and the conductor pattern 34a are connected by a bonding wire whose start and end points are 500 μm apart in the horizontal direction and 250 μm apart in the height direction. That is, the bonding wire 4 can be shortened by providing the protruding terminal 14.

[0073] On the other hand, the protruding terminal 14 also generates an inductance component that affects high-frequency characteristics.

[0074] Here, the diameter is 25 μm and the cross-sectional area is about 490 μm. 2 The bonding wire 4, the protruding terminal 14 is a quadrangular prism with a side length of 100 μm and a cross-sectional area of ​​10000 μm 2 The protruding terminal 14 is half the length and about 20 times the cross-sectional area of ​​the bonding wire 4. Therefore, the inductance component of the protruding terminal 14 is negligibly small compared to the inductance component of the bonding wire 4.

[0075] That is, by providing the protruding terminal 14, the length of the bonding wire 4 can be shortened compared to the case where the conductor pattern 34a is connected to the first main surface 11 without providing the protruding terminal 14. Although an inductance component is also generated in the protruding terminal 14, since the cross-sectional area of ​​the protruding terminal 14 is set larger than the cross-sectional area of ​​the bonding wire 4, the inductance component per unit length of the protruding terminal 14 is smaller than the inductance component per unit length of the bonding wire 4. Thus, even if the height difference increases due to an increase in the thickness of the circuit board 30 or a reduction in the thickness of the semiconductor substrate 10, an increase in the inductance component can be suppressed.

[0076] That is, the inductance component causing the degradation of the high frequency characteristics can be reduced, thereby achieving the effect of being able to suppress the degradation of the high frequency characteristics.

[0077] Next, the function and effect of the short-circuit preventing side wall 15 will be described.

[0078] Generally, the semiconductor substrate 10 has a thickness of about 100 μm. If it is thinned to 50 μm in order to reduce thermal resistance, the semiconductor substrate 10 becomes buried in the bonding material 6 when the chip is bonded, and the bonding material 6 rises to the first main surface of the semiconductor substrate 10. Since the connection between the semiconductor chip and the external circuit is generally performed by connecting the bonding pads provided at the periphery of the semiconductor substrate to the external circuit using bonding wires, the metal plate 2 and the bonding wires are firstly connected through the bonding material 6. In the case of a serious degree of climbing, it may also cause a bad situation of conduction with the matching circuit, transistors and other components provided in the middle of the semiconductor substrate.

[0079] On the other hand, in the first embodiment, the protruding terminal 14 is provided protrudingly on the first main surface 11 of the semiconductor substrate 10, and the side surfaces of the protruding terminal 14 facing the surroundings are covered with the short-circuit prevention side walls 15. Since the short-circuit prevention side walls 15 have insulating properties, even if the conductive bonding material 6 contacts the short-circuit prevention side walls 15, the protruding terminal 14 will not be electrically connected to the metal plate 2. In addition, since the bonding wire 4 connects the end 23 of the protruding terminal 14 to the surface conductive layer of the circuit substrate 30, that is, the conductive pattern 34a, the bonding wire 4 will not be electrically connected to the metal plate 2.

[0080] That is, even when the semiconductor substrate 10 is thinned, it is possible to avoid a short circuit failure of the terminal caused by the bonding material 6 creeping up the first main surface 11 of the semiconductor substrate 10. This achieves an effect of reducing the thermal resistance of the transistor 13.

[0081] Furthermore, the short-circuit prevention sidewall 15 in the first embodiment is provided in an uninterrupted manner around the periphery of the first main surface 11 of the semiconductor substrate 10. This also has the effect of preventing the bonding material 6 from reaching the matching circuit, transistors and other components provided in the middle of the semiconductor substrate 10 and causing conduction.

[0082] As described above, the semiconductor device 100 involved in embodiment 1 of the present disclosure includes a semiconductor chip 110, which has: a semiconductor substrate 10, having a first main surface 11 and a first back surface 12 opposite to each other; a transistor 13 formed on the first main surface 11; a protruding terminal 14, which is conductive with the transistor 13 and is formed protrudingly on the first main surface 11; and an insulating short-circuit prevention side wall 15, which covers the side surfaces 22a, 22b, and 22c of the protruding terminal 14 facing the surrounding of the semiconductor substrate 10 and is arranged on the peripheral portion of the first main surface 11.

[0083] In addition, the semiconductor device 100 includes: a circuit substrate 30 having a second main surface 31 and a second back surface 32 opposite to each other, and a conductor pattern 34a is formed on the second main surface 31; a metal plate 2, the first back surface 12 is bonded to the upper surface 3 by a conductive bonding material 6, and the second back surface 32 is bonded to the upper surface 3; and a bonding wire 4, connecting the end 23 of the protruding direction of the protruding terminal 14 to the conductor pattern 34a.

[0084] Here, the protruding terminal 14 has a larger cross-sectional area than the bonding wire 4. In addition, the short-circuit preventing side wall 15 is provided on the peripheral edge portion of the first main surface 11 of the semiconductor substrate 10 so as to surround the semiconductor substrate 10 without interruption.

[0085] According to such a structure, even when the semiconductor substrate 10 is thinned, a short circuit failure caused by the bonding material 6 climbing up to the first main surface 11 of the semiconductor substrate 10 can be avoided. As a result, the thermal resistance of the transistor 13 can be reduced. In addition, since the increase in inductance component is suppressed even when the bonding wire 4 becomes longer due to an increase in the thickness of the circuit substrate 30 or a thinning of the semiconductor chip, it is possible to provide a semiconductor device with suppressed degradation of high-frequency characteristics.

[0086] In addition, by shortening the bonding wire 4, the maximum allowable current that can flow through the bonding wire 4 can be increased, so that a semiconductor chip with higher output can be applied. By reducing the inductance component, circuit design becomes easier.

[0087] In addition, by thinning the semiconductor substrate 10, the processing time of the through hole 21 can be shortened, thereby improving the productivity of the processing process of the semiconductor chip 110. Since the aspect ratio of the through hole 21, that is, the ratio of the hole depth to the hole diameter, can be reduced, it is possible to improve the processing yield of the through hole 21. Since the thermal resistance of the transistor 13 can be reduced, a transistor with higher output can be used.

[0088] Furthermore, by thinning the semiconductor substrate 10, the microstrip lines constituting the matching circuits 20 and 20b can achieve the same line impedance as before the thinning even if the line width is reduced. This can reduce the wiring layout on the semiconductor substrate 10, thereby miniaturizing the semiconductor chip 110.

[0089] Implementation Method 2

[0090] In the first embodiment, the semiconductor chip 110 and other components are exposed. However, in order to protect the semiconductor chip 110 and other components from external vibration, impact, moisture in the air, and dust, and to facilitate operation, a conventional semiconductor device is sealed by some method. The second embodiment is an example in which the sealing is performed by the most common sealing method, that is, molded resin.

[0091] The semiconductor device 200 according to the second embodiment includes a cover substrate 50 a in addition to the semiconductor chip 110 , the circuit board 30 , the metal plate 2 , and the bonding wires 4 .

[0092] Figure 5 (a) to (c) are a top view, a bottom view, and a cross-sectional view of a cover substrate 50a according to Embodiment 2 of the present disclosure. Figure 5 (a) is a top view of the cover substrate 50a as viewed from above, Figure 5 (b) is a bottom view of the cover substrate 50a as viewed from below. Figure 5 (c) is from Figure 5 (a) is a cross-sectional view of the cover substrate 50a viewed from the AA position.

[0093] The cover substrate 50a has a third main surface 51 and a third back surface 52 opposite to the third main surface 51. A first wiring 54 is provided on the third main surface 51 of the cover substrate 50a. The first wiring 54 has a pad portion 53. A second wiring 56 is provided on the third back surface 52 of the cover substrate 50a. The second wiring 56 has a pad portion 55.

[0094] The first wiring 54 is electrically connected to the through hole 58. The through hole 58 penetrates the cover substrate 50a. The second wiring 56 is electrically connected to the through hole 58. That is, the first wiring 54 and the second wiring 56 are electrically connected.

[0095] The circuit pattern 60 is provided on the third main surface 51 and is electrically connected to the first wiring 54. That is, the circuit pattern 60 is electrically connected to the transistor 13. The circuit pattern 60 is an open stub in the second embodiment and functions as a matching circuit that helps fundamental wave matching. In addition, the circuit pattern 60 may also be a harmonic processing circuit that performs harmonic matching.

[0096] The material of the cover substrate 50a is, for example, a thin ceramic plate having low loss at high frequencies, such as alumina or low temperature co-fired ceramic (LTCC), or a semi-insulating gallium arsenide substrate or a high resistance silicon substrate.

[0097] Figure 6 (a) and (b) are a top view and a cross-sectional view of a semiconductor device 200 according to the second embodiment. Figure 6 (a) is a top view of the semiconductor device 200 as viewed from above. Figure 6 The molding material 9 is not shown in (a). Figure 6 (b) is from Figure 6 (a) is a cross-sectional view of the semiconductor device 200 viewed from the AA position.

[0098] The cover substrate 50a is bonded to the protruding terminal 14 and the short-circuit preventing side wall 15 via the anisotropic conductive film 82. The third main surface 51 of the cover substrate 50a faces the first main surface 11 of the semiconductor substrate 10. That is, the third main surface 51 faces the first main surface 11 with the short-circuit preventing side wall 15 interposed therebetween.

[0099] Similar to the first embodiment, the short-circuit prevention side wall 15 is provided in an uninterrupted manner around the periphery of the first main surface 11. The cover substrate 50a and the short-circuit prevention side wall 15 are bonded to each other without a gap through the anisotropic conductive film 82. As a result, a closed cavity 8 is formed above the first main surface 11 of the semiconductor substrate 10, which faces the first main surface 11 and the third main surface 51 and is surrounded by the semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50a.

[0100] The upper part of the semiconductor device 200 is sealed by the molding material 9. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50a forming the cavity 8 are also sealed by the molding material 9. Since the cavity 8 is sealed, the molding material 9 does not enter the cavity 8 during the molding and sealing of the semiconductor device 200. That is, the semiconductor device 200 has a hollow structure, and the first main surface 11 and the third main surface 51 face the hollow structure.

[0101] The bottom surface of the end portion 23 of the protruding terminal 14 and the pad portion 53 (not shown) of the first wiring 54 are arranged to overlap in a plan view and are electrically connected via the anisotropic conductive film 82. The pad portion 55 (not shown) of the second wiring 56 is electrically connected to the conductor pattern 34a via the bonding wire 4.

[0102] In the second embodiment, the cover substrate 50 a , the protruding terminals 14 , and the short-circuit preventing side walls 15 are bonded together via the anisotropic conductive film 82 , but they may be bonded together via an anisotropic conductive paste or the like.

[0103] The other parts are the same as those in Implementation 1 and the description thereof is omitted.

[0104] As described above, the semiconductor device 200 involved in embodiment 2 of the present disclosure includes a semiconductor chip 110, which has: a semiconductor substrate 10, having a first main surface 11 and a first back surface 12 opposite to each other; a transistor 13, formed on the first main surface 11; a protruding terminal 14, which is conductive with the transistor 13 and protrudes from the first main surface 11 and has a larger cross-sectional area than the bonding wire 4; and an insulating short-circuit prevention side wall 15, which covers the side surfaces 22a, 22b, and 22c of the protruding terminal 14 facing the surrounding of the semiconductor substrate 10 and is arranged on the peripheral portion of the first main surface 11.

[0105] In addition, the semiconductor device 200 includes: a circuit substrate 30, having a second main surface 31 and a second back surface 32 opposite to each other, and a conductor pattern 34a is formed on the second main surface 31; a metal plate 2, the first back surface 12 is bonded to the upper surface 3 by a conductive bonding material 6, and the second back surface 32 is bonded to the upper surface 3; a cover substrate 50a, having a third main surface 51 and a third back surface 52 opposite to each other, the third main surface 51 is opposite to the first main surface 11 with the anti-short-circuit side wall 15 in between and bonded to the anti-short-circuit side wall 15, a first wiring 54 that is conductive to the bottom surface of the end of the protruding direction of the protruding terminal 14 is formed on the third main surface 51, and a second wiring 56 that is conductive to the first wiring 54 through a through hole 58 is formed on the third back surface 52; and a bonding wire 4 that connects the second wiring 56 to the conductor pattern 34a.

[0106] Here, the short-circuit prevention side wall 15 is provided in an uninterrupted manner around the periphery of the first main surface 11 of the semiconductor substrate 10. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50a form a closed cavity 8 facing the first main surface 11 and the third main surface 51. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50a forming the cavity 8 are sealed by the molding material 9. A matching circuit connected to the transistor 13 is provided on the third main surface 51 of the cover substrate 50a.

[0107] According to such a structure, similarly to the semiconductor device 100 shown in the first embodiment, when the semiconductor substrate 10 is thinned, a short circuit failure caused by the bonding material 6 climbing up to the first main surface 11 of the semiconductor substrate 10 can be avoided. As a result, the thermal resistance of the transistor 13 can be reduced. In addition, since the increase in inductance component is suppressed even when the line becomes longer due to the increase in the thickness of the circuit substrate 30 or the thinning of the semiconductor chip, it is possible to provide a semiconductor device in which the degradation of high-frequency characteristics is suppressed.

[0108] Furthermore, in the semiconductor device 200, since the matching circuit is formed on the third main surface 51 of the cover substrate 50a, the semiconductor device 200 can be miniaturized. Since a hollow structure is provided in which the matching circuit is not in contact with the mold material 9, there is no high-frequency loss caused by the mold material 9 compared to a case where the hollow structure is not provided, and the degradation of the characteristics of the matching circuit can be avoided. Since a hollow structure is provided in which the transistor 13 is not in contact with the mold material 9, the parasitic capacitance component of the transistor 13 is not increased compared to a case where the hollow structure is not provided, and the degradation of the characteristics of the transistor 13 can be avoided. Since a hollow structure is provided in which the transistor 13 is not in contact with the mold material 9, the channel temperature of the transistor 13 can be increased without being restricted by the glass transition temperature of the mold material 9, and the semiconductor device 200 can be made high-output.

[0109] Furthermore, a matching circuit that is electrically connected to the second wiring 56 and connected to the transistor 13 may be provided on the third back surface 52. Even a matching circuit provided in this way can achieve a reduction in size of the semiconductor device 200.

[0110] Implementation 3

[0111] The semiconductor chip 130 according to the third embodiment of the present disclosure will be described.

[0112] Figure 7 (a) and (b) are a top view and a cross-sectional view of a semiconductor chip 130 according to Embodiment 3 of the present disclosure. Figure 7 (a) is a top view of the semiconductor chip 130 as viewed from above. Figure 7 (b) is from Figure 7 (a) is a cross-sectional view of the semiconductor chip 130 viewed from the AA position.

[0113] The semiconductor chip 130 is different from the semiconductor chip 110 in that the semiconductor chip 130 includes a grounding side wall 16. The grounding side wall 16 is formed on the first main surface 11 of the semiconductor substrate 10 of the semiconductor chip 130. The grounding side wall 16 is in contact with the short-circuit prevention side wall 15 and covers the outer peripheral wall surface of the short-circuit prevention side wall 15 without interruption. The height of the grounding side wall 16 is the same as that of the short-circuit prevention side wall 15 and the protruding terminals 14 and 14b.

[0114] The grounding side wall 16 is made of gold and can be formed simultaneously with the protruding terminals 14 and 14 b.

[0115] Figure 8 (a) to (c) are a top view, a bottom view, and a cross-sectional view of a cover substrate 50b according to Embodiment 3 of the present disclosure. Figure 8 (a) is a top view of the cover substrate 50b as viewed from above, Figure 8 (b) is a bottom view of the cover substrate 50b as viewed from below. Figure 8 (c) is from Figure 8 (a) is a cross-sectional view of the cover substrate 50b observed at the AA position.

[0116] The cover substrate 50b is different from the cover substrate 50a in that the cover substrate 50b includes a ground pattern 62. The ground pattern 62 is a conductor pattern that is separated from the circuit pattern 60 by a predetermined interval and is formed on the entire surface of the third main surface 51 of the cover substrate 50b. Figure 8The dotted line B in (b) indicates the position of the inner periphery of the ground side wall 16 when viewed from above when the cover substrate 50b is bonded to the semiconductor chip 130. The outer shapes of the cover substrate 50b and the semiconductor chip 130 are set to be consistent when viewed from above when the cover substrate 50b and the semiconductor chip 130 are bonded. The peripheral edge portion of the ground pattern 62 of the cover substrate 50b that is outside the dotted line B is set as the peripheral edge portion 63.

[0117] Fig. 9 (a) and (b) are a top view and a cross-sectional view of a semiconductor device 300 according to the third embodiment. Fig. 9 (a) is a top view of the semiconductor device 300 as viewed from above. Fig. 9 In (a), the molding material 9, the cover substrate 50b, and the bonding wires 4 are not shown. Fig. 9 (b) is from Fig. 9 (a) is a cross-sectional view of the semiconductor device 300 viewed from the AA position.

[0118] The semiconductor device 300 includes a semiconductor chip 130 , a circuit board 30 , a metal plate 2 , bonding wires 4 , and a cover substrate 50 b .

[0119] The semiconductor chip 130 is bonded to the upper surface 3 of the metal plate 2 via the bonding material 6. The grounding side wall 16 of the semiconductor chip 130 is in contact with the bonding material 6, and the grounding side wall 16 and the metal plate 2 are electrically connected.

[0120] The cover substrate 50b makes the third main surface 51 face the first main surface 11 of the semiconductor substrate 10, and is bonded to the protruding terminal 14, the short-circuit prevention side wall 15, and the grounding side wall 16 using the anisotropic conductive film 82. That is, the cover substrate 50b makes the third main surface 51 face the first main surface 11 via the short-circuit prevention side wall 15, and is bonded to the short-circuit prevention side wall 15.

[0121] The cover substrate 50b is seamlessly bonded to the short-circuit preventing side walls 15. As a result, a closed cavity 8 is formed which faces the first main surface 11 and the third main surface 51 and is surrounded by the semiconductor substrate 10, the short-circuit preventing side walls 15, and the cover substrate 50b.

[0122] The bottom surface of the end portion of the protruding terminal 14 in the protruding direction and the pad portion 53 (not shown) of the first wiring 54 are arranged to overlap when viewed from above and are electrically connected via the anisotropic conductive film 82. The peripheral edge portion 63 of the ground pattern 62 and the grounding side wall 16 are arranged to overlap when viewed from above and are electrically connected via the anisotropic conductive film 82. Since the protruding terminal 14 and the ground pattern 62 are arranged not to overlap when viewed from above, the protruding terminal 14 and the ground pattern 62 are electrically connected not via the anisotropic conductive film 82. The pad portion 55 (not shown) of the second wiring 56 is electrically connected to the conductor pattern 34a via the bonding wire 4.

[0123] The peripheral edge portion 63 of the ground pattern 62 is electrically connected to the ground side wall 16 via the anisotropic conductive film 82, and the ground side wall 16 is electrically connected to the metal plate 2 via the conductive bonding material 6 that climbs up to the ground side wall 16. The metal plate 2 is a ground terminal of the semiconductor device 300, and is connected to the ground of the high-frequency amplifier when the semiconductor device 300 is used. That is, the ground pattern 62 is also connected to the ground of the high-frequency amplifier.

[0124] Thus, the ground pattern 62 and the circuit pattern 60 operate as a coplanar line with the ground pattern 62 being a ground conductor metal and the circuit pattern 60 being a signal conductor metal. Such a circuit pattern 60 is also an open stub and functions as a matching circuit that contributes to fundamental wave matching.

[0125] However, in the semiconductor device 200 according to the second embodiment, in the matching circuit formed on the third main surface 51 of the cover substrate 50 a , there is a limit to the range of achievable characteristics of the matching circuit.

[0126] In order to reduce the characteristic impedance of the circuit pattern 60 forming the matching circuit, it is sufficient to expand the line width, that is, the pattern width. However, the area of ​​the cover substrate 50a is small. Therefore, it is difficult to form a low-impedance line with a wide line width and a large setting area. Moreover, the farther the distance between the signal line and the ground is, the more it is necessary to expand the line width in order to maintain the same characteristic impedance. In the semiconductor device 200, the ground corresponding to the circuit pattern 60 forming the matching circuit is the metal plate 2, and the distance between the signal line and the ground is far, which is also the main reason for the need for a wide line width. Therefore, there is a limitation on the characteristic range of the matching circuit that can be achieved.

[0127] In contrast, in the semiconductor device 300 according to the third embodiment, the circuit pattern 60 is a signal conductor metal and the ground pattern 62 is a ground conductor metal, thereby forming a coplanar line. In this case, the impedance of the line can be adjusted by the width of the signal conductor metal and the interval between the ground conductor metal and the signal conductor metal, regardless of the distance between the metal plate 2 and the circuit pattern 60. This ensures the freedom of setting the line impedance and relaxes the limitation on the characteristic range of the matching circuit that can be realized. This has the effect of improving the high-frequency characteristics of the semiconductor device 300.

[0128] Other descriptions are omitted.

[0129] As described above, the semiconductor device 300 involved in embodiment 3 of the present disclosure has a semiconductor chip 130, which has: a semiconductor substrate 10, having a first main surface 11 and a first back surface 12 opposite to each other; a transistor 13, formed on the first main surface 11; a protruding terminal 14, which is conductive with the transistor 13 and protrudingly formed on the first main surface 11, and has a larger cross-sectional area than the bonding wire 4; and an insulating short-circuit prevention side wall 15, which covers the side surfaces 22a, 22b, and 22c of the protruding terminal 14 facing the surrounding of the semiconductor substrate 10 and is arranged on the peripheral portion of the first main surface 11.

[0130] In addition, the semiconductor device 300 comprises: a circuit substrate 30, having a second main surface 31 and a second back surface 32 opposite to each other, and a conductor pattern 34a is formed on the second main surface 31; a metal plate 2, the first back surface 12 is bonded to the upper surface 3 by a conductive bonding material 6, and the second back surface 32 is bonded to the upper surface 3; a cover substrate 50b, having a third main surface 51 and a third back surface 52 opposite to each other, the third main surface 51 is opposite to the first main surface 11 with the anti-short-circuit side wall 15 in between and bonded to the anti-short-circuit side wall 15, a first wiring 54 that is conductive to the bottom surface of the end of the protruding direction of the protruding terminal 14 is formed on the third main surface 51, and a second wiring 56 that is conductive to the first wiring 54 through a through hole 58 is formed on the third back surface 52; and a bonding wire 4 that connects the second wiring 56 to the conductor pattern 34a.

[0131] Here, the short-circuit prevention side wall 15 is provided in an uninterrupted manner around the periphery of the first main surface 11 of the semiconductor substrate 10. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50b form a closed cavity 8 facing the first main surface 11 and the third main surface 51. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50b forming the cavity 8 are sealed by the molding material 9.

[0132] The semiconductor chip 130 further includes a conductive grounding side wall 16 , which covers the outer peripheral wall surface of the short-circuit prevention side wall 15 and is provided on the first main surface 11 . The grounding side wall 16 is electrically connected to the metal plate 2 via a conductive bonding material 6 .

[0133] A circuit pattern 60 connected to the transistor 13 and a ground pattern 62 electrically connected to the ground side wall 16 are provided on the third main surface 51 of the cover substrate 50b. The circuit pattern 60 forms a coplanar line using the ground side wall 16 as a ground conductor metal and functions as a matching circuit.

[0134] With such a structure, the same effects as those of the semiconductor device 100 described in Embodiment 1 and the semiconductor device 200 described in Embodiment 2 can be achieved.

[0135] In addition to the above, in the semiconductor device 300 according to the third embodiment, the matching circuit provided on the cover substrate 50b is constituted by a coplanar line having the circuit pattern 60 as a signal conductor metal and the ground pattern 62 as a ground conductor metal. This ensures the degree of freedom in setting the line characteristic impedance, and has the effect of improving the high frequency characteristics of the semiconductor device 300.

[0136] Implementation 4

[0137] In the third embodiment, the bonding material 6 climbs up to the grounding side wall 16. However, in the manufacturing process, it is difficult to control the climbing amount of the bonding material 6. The fourth embodiment is a structure that facilitates the manufacturing of the semiconductor device even if the bonding material 6 climbs up.

[0138] The difference between the fourth embodiment and the third embodiment lies in the difference in the cover substrate, and the other aspects are the same as those of the third embodiment.

[0139] Fig.10 (a) to (c) are a top view, a bottom view, and a cross-sectional view of a cover substrate 50c according to Embodiment 4 of the present disclosure. Fig.10 (a) is a top view of the cover substrate 50c as viewed from above, Fig.10 (b) is a bottom view of the cover substrate 50c as viewed from below. Fig.10 (c) is from Fig.10 (a) is a cross-sectional view of the cover substrate 50c viewed from the AA position.

[0140] exist Fig.10 In (a) to (c), the dotted line C shows the outer dimensions of the cover substrate 50b. Within the range of the dotted line C, the structure of the cover substrate 50c is the same as that of the cover substrate 50b. Outside the range of the dotted line C, the cover substrate 50c has a structure that expands the periphery of the cover substrate 50b as it is. The portion of the cover substrate 50c outside the range of the dotted line C is set as a protrusion 64. The ground pattern 62 is separated from the circuit pattern 60 at a predetermined interval and is provided on the entire surface of the third main surface 51 of the cover substrate 50c including the protrusion 64.

[0141] A semiconductor device 400 according to a fourth embodiment of the present disclosure will be described. Fig.11 is a cross-sectional view of a semiconductor device 400 according to Embodiment 4. The position of the cross section corresponds to Fig. 9 The semiconductor device 400 includes a semiconductor chip 130 , a circuit board 30 , a metal plate 2 , bonding wires 4 , and a cover substrate 50 c .

[0142] The positional relationship between the range of the dotted line C (not shown) of the cover substrate 50c and the semiconductor chip 130 is the same as the positional relationship between the cover substrate 50b and the semiconductor chip 130 in Embodiment 3. The cover substrate 50c is configured so that the dotted line C (not shown) coincides with the outer shape of the semiconductor chip 130 when viewed from above. The portion outside the dotted line C of the cover substrate 50c, that is, the protrusion 64, extends from the outer shape of the semiconductor chip 130 toward the periphery when viewed from above.

[0143] In Embodiment 3, the bonding material 6 is made to climb to the side of the grounding side wall 16, so that the grounding side wall 16 and the metal plate 2 are connected. The degree of climbing depends on the weight of the bonding material 6. If the weight of the bonding material 6 is too much, it is possible to climb to the third back side 52 of the cover substrate 50b, causing the metal plate 2 and the second wiring 56 or the bonding wire 4 formed on the third back side 52 to short-circuit. However, if the weight of the bonding material 6 is too little, it is possible that the grounding side wall 16 and the metal plate 2 are not connected. In addition, the climbing depends on the surface tension of the bonding material, so even if the weight of the bonding material 6 is the same, there is a deviation in the climbing amount.

[0144] In contrast, in the fourth embodiment, the protrusion 64 extending from the semiconductor chip 130 toward the periphery in a plan view is provided on the cover substrate 50c. Therefore, even if the amount of the bonding material 6 is increased to the extent that it exceeds the grounding side wall 16 and reaches the third back surface 52 of the cover substrate 50b in the third embodiment, Fig.11 The protrusion 64 protruding from the side surface of the grounding side wall 16 like an eave blocks the bonding material 6 climbing up the side surface of the grounding side wall 16 , so that the bonding material 6 is unlikely to reach the third rear surface 52 of the cover substrate 50 c .

[0145] Therefore, the upper limit of the amount of bonding material 6 used in the assembly process can be increased, so that the amount of bonding material 6 can be easily controlled. As a result, the length of the assembly process can be reduced. In addition, it is noted that the above effect can be obtained even if the ground pattern 62 is not provided on the protruding portion 64.

[0146] In addition, it is noted that in the semiconductor device 200 of the second embodiment, by providing a protrusion extending from the outer periphery of the semiconductor chip 110 toward the periphery when viewed from above on the cover substrate 50a, the effect of facilitating the control of the amount of the bonding material 6 can be obtained, similar to the semiconductor device 400 in the fourth embodiment.

[0147] Description of other parts is omitted.

[0148] As described above, the semiconductor device 400 involved in embodiment 4 of the present disclosure has a semiconductor chip 130, which has: a semiconductor substrate 10, having a first main surface 11 and a first back surface 12 opposite to each other; a transistor 13, formed on the first main surface 11; a protruding terminal 14, which is conductive with the transistor 13 and protrudingly formed on the first main surface 11, and has a larger cross-sectional area than the bonding wire 4; and an insulating anti-short-circuit side wall 15, which covers the side surfaces 22a, 22b, and 22c of the protruding terminal 14 facing the surrounding of the semiconductor substrate 10 and is arranged on the peripheral portion of the first main surface 11.

[0149] In addition, the semiconductor device 400 comprises: a circuit substrate 30, having a second main surface 31 and a second back surface 32 opposite to each other, and a conductor pattern 34a is formed on the second main surface 31; a metal plate 2, the first back surface 12 is bonded to the upper surface 3 by a conductive bonding material 6, and the second back surface 32 is bonded to the upper surface 3; a cover substrate 50c, having a third main surface 51 and a third back surface 52 opposite to each other, the third main surface 51 is opposite to the first main surface 11 with the anti-short-circuit side wall 15 in between and bonded to the anti-short-circuit side wall 15, a first wiring 54 that is conductive to the bottom surface of the end of the protruding direction of the protruding terminal 14 is formed on the third main surface 51, and a second wiring 56 that is conductive to the first wiring 54 through a through hole 58 is formed on the third back surface 52; and a bonding wire 4 that connects the second wiring 56 to the conductor pattern 34a.

[0150] Here, the short-circuit prevention side wall 15 is provided in an uninterrupted manner around the periphery of the first main surface 11 of the semiconductor substrate 10. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50c form a closed cavity 8 facing the first main surface 11 and the third main surface 51. The semiconductor substrate 10, the short-circuit prevention side wall 15, and the cover substrate 50c forming the cavity 8 are sealed by the molding material 9.

[0151] The semiconductor chip 130 further includes a conductive grounding side wall 16 , which covers the outer peripheral wall surface of the short-circuit prevention side wall 15 and is provided on the first main surface 11 . The grounding side wall 16 is electrically connected to the metal plate 2 via a conductive bonding material 6 .

[0152] A circuit pattern 60 connected to the transistor 13 and a ground pattern 62 conductively connected to the ground side wall 16 are provided on the third main surface 51 of the cover substrate 50c. The circuit pattern 60 forms a coplanar line with the ground side wall 16 as a ground conductor metal, and functions as a matching circuit. The cover substrate 50c has a protrusion 64 extending from the outer shape of the semiconductor chip 130 toward the periphery when viewed from above.

[0153] With such a structure, the same effects as those of the semiconductor device 100 described in Embodiment 1, the semiconductor device 200 described in Embodiment 2, and the semiconductor device 300 described in Embodiment 3 can be achieved.

[0154] In addition to the above, in the semiconductor device 400 according to the fourth embodiment, since the protrusion 64 extends from the semiconductor chip 130 like an eave to block the top, it is difficult for the bonding material 6 to reach the third back surface 52 of the cover substrate 50c. Therefore, the upper limit of the amount of bonding material 6 used in the assembly process can be increased, so that the amount of bonding material 6 can be easily controlled. As a result, the assembly process can be prevented from being prolonged.

[0155] In addition, the material of the semiconductor substrate 10 can also be Si (Silicon), GaAs (Gallium Arsenide), GaN on Si (Gallium Nitride on Silicon), GaN on GaN (Gallium Nitride on Gallium Nitride), GaN on Diamond (Gallium Nitride on Diamond), etc.

[0156] The material of the cover substrate may be GaN on Si, GaN on GaN, GaN on Diamond, or the like.

[0157] The transistor 13 may be a FET (Field effect transistor), an HBT (Heterojunction Bipolar Transistor), or the like.

[0158] There may be a plurality of semiconductor chips bonded to the metal plate 2 , and the semiconductor chip may not be provided with a matching circuit.

[0159] The metal plate 2, the input terminal 7a, and the output terminal 7b may be made of a low thermal resistance material such as copper-tungsten, copper-molybdenum, or a laminated material such as copper / molybdenum / copper.

[0160] The material of the protruding terminal 14 and the grounding side wall 16 may be aluminum, copper, or the like, or may be an alloy.

[0161] Even if the circuit board 30 is a single-layer board, the present disclosure works effectively when the distance between the main surface of the semiconductor chip and the main surface of the single-layer board is large and the line is long, for example, when the board thickness is increased to increase the mechanical strength.

[0162] As described above, the semiconductor device of the present disclosure reduces the thermal resistance of the transistor and suppresses the degradation of high-frequency characteristics, and is suitable for a semiconductor device for amplifying high frequencies, and is also suitable for a semiconductor device for power amplification.

[0163] The present disclosure is not limited to the above-described embodiments, but includes various modified examples. For example, the above-described embodiments are described in detail to explain the present disclosure in an easy-to-understand manner, and are not limited to necessarily having all the described structures.

[0164] In addition, a part of the structure of a certain embodiment can be replaced with the structure of another embodiment, and the structure of another embodiment can be added to the structure of a certain embodiment. In addition, for a part of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0165] Description of Reference Numerals

[0166] 2…Metal plate; 3…Upper surface; 4…Bonding wire; 6…Bonding material; 8…Void; 9…Molding material; 7a…Input terminal; 7b…Output terminal; 10…Semiconductor substrate; 11…First main surface; 12…First back surface; 13…Transistor; 14…Projecting terminal; 15…Side wall for short circuit prevention; 16…Side wall for grounding; 21…Through hole; 22a, 22b, 22c, 22d…Side surface; 23, 23b…End; 30…Electrode Circuit board; 31…second main surface; 32…second back surface; 34a, 34b, 34c…conductor pattern; 50a, 50b, 50c…cover substrate; 51…third main surface; 52…third back surface; 54…first wiring; 56…second wiring; 60…circuit pattern; 62…ground pattern; 64…protrusion; 81…electronic component; 100, 200, 300, 400…semiconductor device; 110, 130…semiconductor chip.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor chip comprises: a semiconductor substrate having a first main surface and a first back surface facing each other; A transistor formed on the first main surface; a protruding terminal conductively connected to the transistor and protrudingly formed on the first main surface; and an insulating short-circuit prevention side wall, covering the side surface of the protruding terminal facing the periphery of the semiconductor substrate and provided at the peripheral edge of the first main surface; A circuit substrate having a second main surface and a second back surface facing each other, and a conductor pattern is formed on the second main surface; a metal plate having an upper surface, the first back surface being bonded to the upper surface via a bonding material having electrical conductivity, and the second back surface being bonded to the upper surface; as well as A bonding wire connects an end portion of the protruding terminal in a protruding direction to the conductor pattern, and the protruding terminal has a larger cross-sectional area than the bonding wire.

2. The semiconductor device according to claim 1, wherein: The short-circuit preventing side wall is provided in a surrounding manner without interruption on the peripheral edge portion of the first main surface.

3. A semiconductor device, characterized in that: have: A semiconductor chip comprises: a semiconductor substrate having a first main surface and a first back surface facing each other; A transistor formed on the first main surface; a protruding terminal conductively connected to the transistor and protrudingly formed on the first main surface; and an insulating short-circuit prevention side wall, covering the side surface of the protruding terminal facing the periphery of the semiconductor substrate and provided at the peripheral edge of the first main surface; A circuit substrate having a second main surface and a second back surface facing each other, and a conductor pattern is formed on the second main surface; a metal plate having an upper surface, the first back surface being bonded to the upper surface via a bonding material having electrical conductivity, and the second back surface being bonded to the upper surface; a cover substrate having a third main surface and a third back surface facing each other, the third main surface facing the first main surface across the short-circuit-preventing side wall and bonded to the short-circuit-preventing side wall, a first wiring conductively connected to an end portion of the protruding direction of the protruding terminal formed on the third main surface, and a second wiring conductively connected to the first wiring formed on the third back surface; as well as a bonding wire connecting the second wiring and the conductor pattern, The protruding terminal has a larger cross-sectional area than the bonding wire.

4. The semiconductor device according to claim 3, wherein: The short-circuit preventing side wall is provided in a surrounding manner without interruption on the peripheral edge portion of the first main surface.

5. The semiconductor device according to claim 4, wherein: A matching circuit connected to the transistor is further provided on the third main surface of the cover substrate.

6. The semiconductor device according to claim 5, wherein: The semiconductor substrate, the short-circuit prevention side walls, and the cover substrate form a closed cavity facing the first main surface and the third main surface, and the semiconductor substrate, the short-circuit prevention side walls, and the cover substrate forming the cavity are sealed by a molding material.

7. The semiconductor device according to claim 5 or 6, characterized in that: The semiconductor chip further includes a conductive grounding side wall, the grounding side wall covers the outer peripheral wall surface of the short-circuit prevention side wall and is provided on the first main surface. The grounding side wall is electrically connected to the metal plate through the conductive bonding material. The cover substrate further includes a ground pattern, the ground pattern being provided on the third main surface and being electrically connected to the ground side wall. The matching circuit is formed by a coplanar line using the ground pattern as a ground conductor metal.

8. The semiconductor device according to any one of claims 4 to 7, wherein: The cover substrate has a protrusion extending from an outer shape of the semiconductor chip toward a periphery in a plan view.

9. The semiconductor device according to claim 3, wherein: A matching circuit connected to the transistor is further provided on the third main surface of the cover substrate.

10. The semiconductor device according to claim 4, wherein: The semiconductor substrate, the short-circuit prevention side walls, and the cover substrate form a closed cavity facing the first main surface and the third main surface, and the semiconductor substrate, the short-circuit prevention side walls, and the cover substrate forming the cavity are sealed by a molding material.

11. The semiconductor device according to any one of claims 3 to 10, characterized in that A matching circuit connected to the transistor is further provided on the third rear surface of the cover substrate.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that The semiconductor chip amplifies high frequencies.

13. The semiconductor device according to any one of claims 1 to 12, wherein: A through hole is provided which penetrates the semiconductor substrate, and the transistor is connected to the metal plate via the through hole.

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