A method for manufacturing a gate oxide structure and a corresponding gate oxide structure, device

Abstract

The application relates to the technical field of silicon carbide, and discloses a preparation method of a gate oxide structure, a corresponding gate oxide structure and a device. A plurality of silicon dioxide films arranged at intervals are formed on the surface of a silicon carbide substrate to obtain a silicon dioxide film layer; the plurality of silicon dioxide films are annealed and passivated; and a high-dielectric material film layer is formed on the surface of the silicon dioxide film layer. The application forms a plurality of silicon dioxide films arranged at intervals on the surface of a silicon carbide substrate, and further carries out annealing treatment, so that the contact area between the interface of the silicon dioxide film and the annealing nitrogen-containing gas is increased, the passivation proportion of the dangling bond at the interface is effectively increased, and the generation of interface state defects is inhibited. In addition, the application grows a high-dielectric material film layer on the silicon dioxide film layer, increases the interface valence band difference and the conduction band difference of the silicon carbide substrate layer, thereby inhibiting the leakage current and reducing the energy loss.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon carbide, in particular to a preparation method of gate oxide structure and corresponding gate oxide structure and device. BACKGROUND

[0002] In the preparation process of existing SiC power devices, especially MOSFET, a mature SiC thermal oxidation process is often used to prepare a SiO2 oxide insulating layer, as shown in the following formula: However, for the SiO2 oxide insulating layer grown by thermal oxidation, due to insufficient chemical reaction, a large number of interface defects such as Si-Si and C-C will inevitably occur at the interface, resulting in a large decrease in channel mobility, which is far from the theoretical electron mobility of SiC.

[0003] On the other hand, the method for reducing the interface defects of the SiO2 layer in the traditional method is to perform an annealing process by using NO, N2O, N2 and other gases to react with Si and C atoms at the interface to form Si-N and C-N to raise the defect level, so as to avoid the trapping of electrons and thus improve the channel electron mobility. However, the channel electron mobility obtained by these methods still has a large gap with the theoretical value.

[0004] In addition, the dielectric constant of SiO2 material is low (only 3.9), according to Gauss theorem, ε1*E1=ε2*E2, the low dielectric constant will increase the electric field at the gate oxide, which challenges its reliability. In recent years, gate oxide materials represented by Al2O3 and other high dielectric materials have been widely studied. These materials have larger dielectric constant than SiO2 and have significant advantages in reliability. However, the preparation process of these materials is poor in matching with SiC, and often has high interface state defects and large gate leakage current. SUMMARY

[0005] The present application aims to overcome the problem of poor reliability of the existing gate oxide structure, and provides a preparation method of gate oxide structure and corresponding gate oxide structure and device.

[0006] In order to achieve the above-mentioned purpose, the present application provides a preparation method of gate oxide structure, comprising:

[0007] providing a silicon carbide substrate, forming a plurality of spaced silicon dioxide films on the surface of the silicon carbide substrate to obtain a silicon dioxide film layer;

[0008] annealing and passivating the plurality of silicon dioxide films; and forming a high dielectric material film layer on the surface of the silicon dioxide film layer.

[0009] As an implementable mode, the size of the silicon dioxide film ranges from 10nm to 100nm, and the interval of the adjacent silicon dioxide films ranges from 10nm to 100nm.

[0010] As an implementable mode, the thickness of the silicon dioxide film ranges from 3nm to 10nm, and the thickness of the high dielectric material film layer ranges from 10nm to 57nm.

[0011] As an implementable mode, the step of forming the plurality of silicon dioxide films arranged at intervals on the surface of the silicon carbide substrate specifically comprises:

[0012] forming a photoresist layer on the surface of the silicon carbide substrate, and performing photoetching on the photoresist layer to form a photoetching pattern;

[0013] growing silicon dioxide on the silicon carbide substrate with the photoetching pattern to obtain the plurality of silicon dioxide films arranged at intervals corresponding to the photoetching pattern, and removing the photoresist remaining between the silicon dioxide films.

[0014] As an implementable mode, the method of growing the silicon dioxide film on the silicon carbide substrate with the photoetching pattern is specifically an LPCVD method; wherein the deposition temperature in the LPCVD method ranges from 500℃ to 800℃.

[0015] As an implementable mode, the step of annealing and passivating the plurality of silicon dioxide films specifically comprises: annealing and passivating the plurality of silicon dioxide films by using a nitroxide gas; wherein the temperature during annealing ranges from 900℃ to 1200℃, and the time of the annealing treatment ranges from 10min to 40min; the nitroxide gas is a mixed gas of any one of NO, N2O or NO2 and an inert gas, the ratio of the two gases is 1:1, and the gas pressure of the mixed gas ranges from 1.5Pa to 2.5Pa.

[0016] As an implementable mode, the high dielectric material of the high dielectric material film layer is one of Al2O3, ZrO2 and HfO2; the method of forming the high dielectric material film layer on the surface of the silicon dioxide film layer is specifically an ALD method; wherein the temperature for preparing the high dielectric material by using the ALD method ranges from 600℃ to 900℃.

[0017] As an implementable mode, the step of forming the high dielectric material film layer on the surface of the silicon dioxide film layer further comprises: forming a first electrode layer on the surface of the high dielectric material film layer, and forming a second electrode layer on the other side surface of the silicon carbide substrate opposite to the side surface provided with the silicon dioxide film layer.

[0018] Correspondingly, the application also provides a gate oxide structure prepared by the preparation method of the gate oxide structure.

[0019] Correspondingly, the application also provides a device comprising the gate oxide structure prepared by the preparation method of the gate oxide structure.

[0020] The application discloses a preparation method of a gate oxide structure and a corresponding gate oxide structure and device, and the method comprises the following steps: providing a silicon carbide substrate, forming a plurality of silicon dioxide films arranged at intervals on the surface of the silicon carbide substrate to obtain a silicon dioxide film layer; performing annealing passivation on the plurality of silicon dioxide films; and forming a high-dielectric material film layer on the surface of the silicon dioxide film layer. The method forms a plurality of silicon dioxide films arranged at intervals on the surface of the silicon carbide substrate, and further performs annealing treatment, so that the contact area of the interface between the silicon dioxide film and the silicon carbide substrate and the nitroxyl gas is increased, the nitroxyl gas can enter the interface between the silicon dioxide film and the silicon carbide substrate from the boundary of the silicon dioxide film, the interface defects of the silicon dioxide film and the silicon carbide substrate are sufficiently passivated, the passivation proportion of the dangling bonds at the interface is effectively increased, and the generation of the interface state defects is inhibited. In addition, the high-dielectric material film layer is grown on the silicon dioxide film layer, the interface valence band difference and the conduction band difference of the silicon carbide substrate layer are increased, the leakage current is inhibited, and the energy loss is reduced.

[0021] The size range of the silicon dioxide film is 10-100 nm, the interval range of the adjacent silicon dioxide films is 10-100 nm, and the thickness range of the silicon dioxide film is 3-10 nm, so that the passivation effect is good, the interface defects are effectively solved, and the high-dielectric material film layer is well protected.

[0022] The high-dielectric material film layer growth temperature is 600-900 DEG C, the patterned silicon dioxide film layer that has been passivated is not damaged, and the interface carriers have high mobility. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 The figure is a preparation method of a gate oxide structure of an embodiment of the application;

[0024] Figures 2-13 The figure is a preparation method of a gate oxide structure of an embodiment of the application;

[0025] Figure 14 The figure is a preparation method of a gate oxide structure of an embodiment of the application; DETAILED DESCRIPTION

[0026] Clearly, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.

[0027] Referring to Figure 1 The present embodiment provides a technical solution: a preparation method of a gate oxide structure, comprising:

[0028] Step S100, providing a silicon carbide substrate, forming a plurality of spaced silicon dioxide films on the surface of the silicon carbide substrate to obtain a silicon dioxide film layer;

[0029] Step S200, annealing and passivating the plurality of silicon dioxide films; and forming a high dielectric material film layer on the surface of the silicon dioxide film layer.

[0030] In the present embodiment, the size of the silicon dioxide film ranges from 10nm to 100nm, and the interval between adjacent silicon dioxide films ranges from 10nm to 100nm; and the thickness of the silicon dioxide film ranges from 3nm to 10nm.

[0031] The present embodiment sets the reasonable size and thickness range of the silicon dioxide film, so that a good passivation effect can be achieved, the problem of interface defects can be effectively solved, and the high dielectric material film layer can be well protected.

[0032] The present embodiment sets the size of the silicon dioxide film to range from 10nm to 100nm, and the interval between adjacent silicon dioxide films to range from 10nm to 100nm, so that a sufficient passivation effect is obtained.

[0033] The step of forming a plurality of spaced silicon dioxide films on the surface of the silicon carbide substrate specifically comprises:

[0034] Forming a photoresist layer on the surface of the silicon carbide substrate, and performing photoetching on the photoresist layer to form a photoetching pattern.

[0035] Growth of silicon dioxide on the silicon carbide substrate with the photoetching pattern to obtain a plurality of spaced silicon dioxide films corresponding to the photoetching pattern, and removal of the remaining photoresist between the silicon dioxide films.

[0036] The method for growing the silicon dioxide film on the silicon carbide substrate with the photoetching pattern is specifically an LPCVD method; and the deposition temperature when the LPCVD method is used is 500-800℃.

[0037] The step S200 of annealing and passivating the plurality of silicon dioxide thin films comprises: annealing and passivating the plurality of silicon dioxide thin films by using nitroxyl gas.

[0038] Specifically, in order to further improve the proportion of nitrogen atom annealing and passivation at the interface between the patterned silicon dioxide thin film layer and the silicon carbide substrate, the plurality of silicon dioxide thin films formed by annealing treatment in the nitroxyl gas environment need to be annealed, the temperature range of the annealing is 900-1200℃, and the annealing treatment time range is 10-40min; the nitroxyl gas is any one of NO, N2O or NO2 mixed with inert gas, wherein the proportion of the two gases is 1:1, and the gas pressure range of the mixed gas is 1.5-2.5Pa, and the inert gas is used to dilute the nitroxyl gas to prevent the oxidation reaction from being too fast, which causes the active part of the SiC substrate layer to be rapidly oxidized, so that the reaction of the lack of active part is not complete, thereby causing the overall reaction to be uneven.

[0039] Further, when NO is selected for annealing, the gas pressure can be controlled to be 1.5Pa, and the annealing time is 10min. Compared with NO, N2O has weaker activity of N atom, but has less damage to the density of SiO2 bulk phase, so in order to achieve better annealing and passivation effect, the high-temperature oxidation time of N2O can be controlled to be increased, and the gas pressure can be increased, so as to anneal and passivate the silicon dioxide thin film layer; for example, the gas pressure can be controlled to be 2.0Pa, and the annealing time is 20min.

[0040] In the embodiment, since the passivation of the interface affecting the carrier mobility is considered, the thickness of the silicon dioxide thin film layer needs to be controlled to be about 3-10nm, and the effective thickness of the general gate oxide layer is about 20-60nm, so the thickness range of the high dielectric material thin film layer can be controlled to be 10-57nm by adjusting the annealing time in the embodiment.

[0041] As an example, the high dielectric material of the high dielectric material thin film layer can be one of Al2O3, ZrO2, HfO2, etc.; the method for forming the high dielectric material thin film layer on the surface of the silicon dioxide thin film layer is ALD method; wherein in the process of preparing the high dielectric material by using the ALD method, in order to not produce new defects in the growth process and not damage the patterned silicon dioxide thin film layer which has been annealed and passivated, so as to make the interface carrier have higher mobility, the growth temperature is set to be 600-900℃, which is lower than the traditional annealing temperature setting.

[0042] It should be noted that when different high dielectric materials are selected, the thickness of the corresponding silicon dioxide film and the thickness of the high dielectric material film layer should be selected according to the characteristics of the high dielectric material itself. For example, when Al2O3 is selected as the high dielectric material in an embodiment, the thickness of the formed silicon dioxide film can be 3 nm, and the thickness of the high dielectric material film layer can be 50 nm. When ZrO2 is selected, the dielectric constant of ZrO2 is larger than that of Al2O3, and thus the protection ability of the gate current is stronger, and the required thickness is smaller. Therefore, a 20 nm ZrO2 film can be selected. In addition, the energy band gap of ZrO2 is smaller than that of Al2O3, and thus the leakage current is more likely to occur. Therefore, a thicker SiO2 film with a larger energy band gap is required to protect it. Therefore, a 10 nm SiO2 film can be selected as the intermediate layer.

[0043] Further, the embodiment further includes, after the step of forming the high dielectric material film layer on the surface of the silicon dioxide film layer, forming a first electrode layer on the surface of the high dielectric material film layer, and forming a second electrode layer on the other side surface of the silicon carbide substrate opposite to the side surface provided with the silicon dioxide film layer.

[0044] In the embodiment, a first electrode layer is deposited on the densified SiO2 film layer by a magnetron sputtering method, and a second electrode layer is deposited on the silicon carbide substrate layer. The first electrode layer is a gate electrode layer, and the second electrode layer is a bottom electrode layer. Thus, the preparation of the gate oxide structure of the SiC power device is completed.

[0045] Specifically, as shown in Figure 2 and Figure 3 , a silicon carbide substrate 10 is provided, Figure 2 is a top view, Figure 3 is Figure 2 a side view; and as shown in Figure 4 and Figure 5 , the Figure 4 is a top view, Figure 5 is Figure 4 a side view, a photoresist layer 20 is coated on the silicon carbide substrate 10 by a spin coating method; then as shown in Figure 6 and Figure 7 , the Figure 6 is a top view, Figure 7 is Figure 6 a side view in the AA direction, the photoresist layer 20 is subjected to photolithography to form a plurality of photoresist patterns 21, wherein the size of each photoresist pattern is 10-100 nm, and the interval between adjacent photoresist patterns is 10-100 nm;

[0046] A patterned silicon dioxide film is grown on the photoresist-processed silicon carbide substrate by an LPCVD method, i.e., as shown in Figure 8As shown, multiple silicon dioxide thin films 30 are formed at the locations where the photolithographic pattern is formed, and the size of the resulting silicon dioxide thin films is 10-100 nm, with the spacing between adjacent photolithographic patterns also being 10-100 nm. Then, the photoresist layer 20 on the patterned silicon dioxide thin films is cleaned using a cleaning solvent to obtain the desired result. Figure 9 The plurality of silicon dioxide thin films 30 distributed on the surface of the silicon carbide substrate 10 are shown. Figure 10 Then it is Figure 9 A side view; annealing of the patterned silicon dioxide film using nitrogen oxide gas for dangling bond passivation and dangling bond defects; followed by ALD at high temperature, such as... Figure 11 As shown, a high-dielectric material thin film layer 50 is grown on the patterned silicon dioxide thin film 30; for example... Figure 12 and Figure 13 As shown, Figure 12 Top view, Figure 13 for Figure 12 The side view shows a first electrode layer 60 deposited on the high dielectric material thin film layer 50 and a second electrode layer 70 deposited on the silicon carbide substrate layer.

[0047] Furthermore, after the step of forming a high-dielectric material thin film layer on the surface of the silicon dioxide thin film layer, the method further includes: forming a first electrode layer on the surface of the high-dielectric material thin film layer, and forming a second electrode layer on the silicon carbide substrate on the opposite side of the side surface where the silicon dioxide thin film layer is located.

[0048] On the one hand, the embodiments of the present invention grow patterned silicon dioxide thin film layers, i.e., multiple spaced silicon dioxide thin films, by photolithography, and then further perform nitrogen annealing passivation annealing treatment to obtain annealed passivation patterned silicon dioxide thin film layers, thereby increasing the contact area between the interface between SiO2 and SiC and the nitrogen-containing annealing gas. Furthermore, by adjusting parameters such as film thickness and annealing atmosphere time, the annealing passivation ratio of dangling bonds at the interface is effectively increased, thereby suppressing the generation of interface state defects.

[0049] On the other hand, in this embodiment of the invention, a high-dielectric material thin film layer is grown on a photolithographically patterned silicon dioxide thin film layer, increasing the valence band gap and conduction band gap at the interface of the silicon carbide substrate layer, thereby suppressing leakage current, reducing energy loss, and preventing electrons from crossing the potential barrier under gate voltage, generating a large tunneling current and causing significant energy loss. Figure 14 This can be verified by ΔE in the diagram. v1 ΔE v2 Indicates the price band difference, ΔE c1 E c2The band gap difference is represented, and it can be seen from the figure that the valence band gap difference measured by the SiC / SiO2 / high dielectric material structure obtained by fine layering is larger than the valence band gap difference measured by the SiC / high dielectric material structure, and similarly, the conduction band gap difference measured by the SiC / SiO2 / high dielectric material structure is larger than the conduction band gap difference measured by the SiC / high dielectric material structure, thereby proving the purpose of increasing the interface valence band and conduction band gap difference in actual detection, and further suppressing the leakage current.

[0050] Based on the same inventive concept, the embodiment of the present application also provides a gate oxide structure prepared based on the preparation method of the gate oxide structure.

[0051] Based on the same inventive concept, the present application also provides a device comprising a gate oxide structure prepared based on the preparation method of the gate oxide structure.

[0052] Although the present application has been disclosed with the above preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not depart from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A method for preparing a gate oxide structure, characterized in that, include: A silicon carbide substrate is provided, and a plurality of spaced-apart silicon dioxide thin films are formed on the surface of the silicon carbide substrate to obtain a discontinuous silicon dioxide thin film layer; Multiple silicon dioxide thin films are annealed and passivated using nitrogen oxidizing gas, which allows the nitrogen oxidizing gas to enter the interface between the silicon dioxide thin film and the silicon carbide substrate from the boundary of the silicon dioxide thin film. This fully passivates the interface defects between the silicon dioxide thin film and the silicon carbide substrate, effectively increasing the passivation ratio of dangling bonds at the interface and thus suppressing the generation of interface state defects. A high dielectric material thin film layer is then formed on the surface of the silicon dioxide thin film layer.

2. The method for preparing the gate oxide structure according to claim 1, characterized in that, The size range of the silicon dioxide film is 10-100 nm, and the spacing between adjacent silicon dioxide films is 10-100 nm.

3. The method for preparing the gate oxide structure according to claim 1, characterized in that, The thickness of the silicon dioxide thin film ranges from 3 to 10 nm, and the thickness of the high dielectric material thin film layer ranges from 10 to 57 nm.

4. The method for preparing the gate oxide structure according to claim 1, characterized in that, The step of forming a plurality of spaced-apart silicon dioxide thin films on the surface of the silicon carbide substrate specifically includes: A photoresist layer is formed on the surface of the silicon carbide substrate, and the photoresist layer is subjected to photolithography to form a photolithographic pattern; Silicon dioxide is grown on a silicon carbide substrate that forms a photolithographic pattern to obtain multiple spaced silicon dioxide films corresponding to the photolithographic pattern, and then the remaining photoresist between the silicon dioxide films is removed.

5. The method for preparing the gate oxide structure according to claim 4, characterized in that, The method for growing silicon dioxide thin films on silicon carbide substrates with photolithographic patterns is LPCVD; wherein the deposition temperature when using LPCVD is 500-800℃.

6. The method for preparing the gate oxide structure according to claim 1, characterized in that, The specific steps of annealing and passivating multiple silicon dioxide films include: annealing and passivating multiple silicon dioxide films with nitrogen oxidizing gas; wherein the annealing temperature range is 900-1200℃, the annealing time range is 10-40min; the nitrogen oxidizing gas is any one of NO, N2O or NO2 mixed with an inert gas, the ratio of the two gases is 1:1, and the gas pressure range of the mixed gas is 1.5-2.5Pa.

7. The method for preparing the gate oxide structure according to claim 1, characterized in that, The high dielectric material of the high dielectric material thin film layer is one of Al2O3, ZrO2, and HfO2; the method for forming the high dielectric material thin film layer on the surface of the silicon dioxide thin film layer is specifically the ALD method; wherein, the temperature range for preparing the high dielectric material using the ALD method is 600~900℃.

8. The method for preparing the gate oxide structure according to claim 1, characterized in that, After the step of forming a high-dielectric material thin film layer on the surface of the silicon dioxide thin film layer, the method further includes: forming a first electrode layer on the surface of the high-dielectric material thin film layer, and forming a second electrode layer on the silicon carbide substrate on the opposite side of the side surface where the silicon dioxide thin film layer is located.

9. A gate oxide structure prepared by the method for preparing a gate oxide structure according to any one of claims 1-8.

10. A device comprising a gate oxide structure prepared by a method for preparing a gate oxide structure according to any one of claims 1-8.

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