Semiconductor device and method of forming the same, memory

Abstract

This disclosure provides a semiconductor device and a method for forming the same, relating to the field of semiconductor technology. The method includes: providing a substrate; forming a metal layer on the substrate, the metal layer including a plurality of spaced conductive portions; sequentially forming an insulating layer and a mask layer on the metal layer, the mask layer including a plurality of mask patterns, the orthographic projection of the mask patterns on the substrate covering the orthographic projection of the conductive portions on the substrate; etching the insulating layer through the mask layer to form trenches exposing the conductive portions; and removing the mask layer using an oxygen-free stripping gas. The semiconductor device formation method provided by this disclosure, by etching the insulating layer through the mask layer to form trenches exposing the conductive portions, and by using an oxygen-free stripping gas to remove the mask layer, avoids oxidation of the metal layer caused by the stripping gas during mask layer removal, thereby solving the problem of poor connection due to oxidation of metal wires.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for forming the same, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in smart devices such as mobile phones and tablets due to its small size, high data transfer speed, and high integration. As the size of terminal devices continues to shrink, the size of memory is also shrinking, thus placing increasingly higher demands on the manufacturing process of memory.

[0003] The connection of metal wires is related to the connection of internal components of the device. Because metal wires are prone to oxidation during the semiconductor manufacturing process, poor connection or short circuit between wires may occur, affecting the quality of the device.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a semiconductor device and a method for forming the same, which solves the problem of metal wire oxidation caused by the process and the problem of poor connection or short circuit between metal wires.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0007] According to one aspect of this disclosure, a method for forming a semiconductor device is provided, the method comprising:

[0008] Provide a substrate;

[0009] A metal layer is formed on the substrate, the metal layer comprising a plurality of spaced conductive portions;

[0010] An insulating layer and a mask layer are sequentially formed on the metal layer. The mask layer includes multiple mask patterns, and the orthographic projection of the mask patterns on the substrate covers the orthographic projection of the conductive part on the substrate.

[0011] The insulating layer is etched through the mask layer to form trenches that expose the conductive parts;

[0012] The mask layer is removed using an oxygen-free stripping gas.

[0013] In some embodiments of this disclosure, based on the foregoing scheme, the mask layer includes a spin-coated hard mask, and the oxygen-free stripping gas contains nitrogen and hydrogen, the oxygen-free stripping gas being used to remove the spin-coated hard mask.

[0014] In some embodiments of this disclosure, after forming the trench based on the foregoing scheme, the method further includes:

[0015] A filling layer is formed within the trench.

[0016] In some embodiments of this disclosure, based on the foregoing scheme, a filling layer is formed within the trench, the method comprising:

[0017] The trench is filled with a filler material, which at least completely fills the trench.

[0018] The filler material is planarized by removing the filler material located on the surface of the insulating layer to form a filler layer flush with the surface of the insulating layer.

[0019] In some embodiments of this disclosure, based on the foregoing scheme, the method further includes:

[0020] A protective layer is formed between the insulating layer and the mask layer.

[0021] In some embodiments of this disclosure, based on the foregoing scheme, the method further includes:

[0022] The protective layer is etched simultaneously with the insulating layer through the mask layer.

[0023] In some embodiments of this disclosure, after etching the protective layer based on the foregoing scheme, the method further includes:

[0024] The trench is filled with a filler material, which at least covers the surface of the protective layer.

[0025] In some embodiments of this disclosure, based on the foregoing scheme, after filling the trench with filler material, the method further includes:

[0026] Remove the protective layer and the filler material above the surface of the protective layer, so that the filler material is flush with the surface of the insulating layer to form a filler layer.

[0027] In some embodiments of this disclosure, based on the foregoing scheme, the filling material is a conductive material.

[0028] In some embodiments of this disclosure, based on the foregoing scheme, the conductive material is at least one of copper, titanium, titanium nitride, and tungsten.

[0029] In some embodiments of this disclosure, based on the foregoing scheme, the volumetric flow rate ratio of nitrogen to hydrogen in the oxygen-free stripping gas is 2:1 to 4:1.

[0030] In some embodiments of this disclosure, based on the foregoing scheme, the working time of the oxygen-free stripping gas is 100S to 150S.

[0031] In some embodiments of this disclosure, based on the foregoing scheme, the working power of the oxygen-free stripping gas is 700W-900W, and the working frequency of the oxygen-free stripping gas is 25MHz-29MHz.

[0032] According to another aspect of this disclosure, a semiconductor device is provided, which is manufactured using the semiconductor device forming method described above.

[0033] According to another aspect of this disclosure, a memory is provided that includes the aforementioned semiconductor device.

[0034] This disclosure provides a method for forming a semiconductor device. A metal layer with multiple spaced conductive portions is formed on a substrate. An insulating layer and a mask layer are sequentially formed on the metal layer. After etching the insulating layer through the mask layer, trenches exposing the conductive portions are formed. The mask layer is then removed using an oxygen-free stripping gas. This method avoids the oxidation of the metal layer caused by using stripping gas to remove the mask layer in the semiconductor device manufacturing process. It ensures the conductivity of the metal layer and the contact between metal wires, solves the problem of poor contact or short circuit of metal wires caused by metal oxidation, and thus improves the yield of the device.

[0035] In another aspect, this disclosure provides a semiconductor device fabricated using the above-described semiconductor device formation method, which prevents oxidation of the metal wires in the semiconductor device and ensures good connectivity of the metal wires within the device.

[0036] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0037] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0038] Figure 1 This is a schematic flowchart of a semiconductor device formation method according to an exemplary embodiment of the present disclosure.

[0039] Figures 2-6 This is a schematic structural view of a semiconductor device formation process according to an exemplary embodiment of the present disclosure.

[0040] Figures 7-11 This is a schematic diagram of another process in the formation of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0041] Figure 12 This is a schematic diagram of a structure formed by existing metal wires in an exemplary embodiment of this disclosure.

[0042] The reference numerals in the attached figures are explained as follows:

[0043] 10: Substrate; 20: Metal layer; 30: Insulating layer; 40: Mask layer; 50: Photoresist layer; 60: Protective layer; 70: Filler layer; 80: Trench; 100: Oxide; 401: Spin-on hard mask; 402: Sacrificial layer; 403: Anti-reflection layer. Detailed Implementation

[0044] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0045] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0046] Dynamic Random Access Memory (DRAM) has been widely used in various fields due to its small size and high data read / write speed. As the requirements for memory size increase, DRAM manufacturing processes are also continuously shrinking. Connections between metal wires within the memory device can lead to short circuits and device damage. Therefore, the morphology of the metal wires within the device is crucial, and the manufacturing process of the metal wires is a key step affecting their morphology.

[0047] Currently, in the manufacturing of metal wires, the oxidizing properties of the stripping gas introduced during the film removal process can cause oxidation of the metal wires, resulting in poor contact or short circuits between the metal wires.

[0048] In some embodiments, during semiconductor manufacturing processes, a stripping gas is often introduced to remove the mask layer 40. This stripping gas typically contains gases such as oxygen, carbon monoxide, carbon dioxide, nitrous oxide, or carbonyl sulfide (COS). These gases all contain oxygen atoms or oxygen elements and possess oxidizing properties. The stripping gas forms a plasma to remove the mask layer 40. However, these oxidizing gases often cause oxidation of the metal layer 20 exposed in the stripping gas during the stripping of the mask layer 40. Figure 12 As shown, oxide 100 is located on the surface of metal layer 20, which can cause problems such as poor contact or short circuit when metal wires are connected.

[0049] Therefore, this disclosure provides a method for forming a semiconductor device, which solves the problem of oxidation of the metal layer 20 when removing the mask layer 40, ensures the conductivity and connectivity of the metal, and thus avoids poor contact or short circuits when connecting metal wires.

[0050] This disclosure provides a method for forming a semiconductor device, such as... Figure 1 As shown, the method includes:

[0051] Step S10: Provide a substrate;

[0052] Step S20: Form a metal layer on the substrate, the metal layer including a plurality of spaced conductive portions;

[0053] Step S30: An insulating layer and a mask layer are sequentially formed on the metal layer. The mask layer includes multiple mask patterns. The orthogonal projection of the mask patterns on the substrate covers the orthogonal projection of the conductive part on the substrate.

[0054] Step S40: Etch the insulating layer through a mask layer to form trenches that expose the conductive parts;

[0055] Step S50: Remove the mask layer using oxygen-free stripping gas.

[0056] The semiconductor device formation method disclosed herein forms a metal layer, an insulating layer, and a mask layer with conductive parts on a substrate. After etching the insulating layer with the mask layer, trenches exposing the conductive parts are formed. The mask layer is then removed with an oxygen-free stripping gas. This avoids the oxidation of the metal layer by the stripping gas during mask layer removal, ensuring the conductivity of the metal layer. This, in turn, improves the connectivity and contact between metal wires and increases the device yield.

[0057] The following is combined with Figures 1 to 11The method for forming a semiconductor device provided in this disclosure will be described in detail below:

[0058] In steps S10 and S20, a substrate 10 is provided; a metal layer 20 is formed on the substrate 10, the metal layer 20 including a plurality of spaced conductive portions.

[0059] In the embodiments provided in this disclosure, such as Figure 2 As shown, the substrate 10 can be made of polycrystalline silicon, and multiple film layers can be formed between the substrate 10 and the metal layer 20. The specific film layer structure between the substrate 10 and the metal layer 20 can be set according to the specific structure of the semiconductor device.

[0060] The metal layer 20 formed on the substrate 10 has multiple spaced conductive portions made of a conductive material, such as tungsten or copper. These conductive portions are where metal wires are formed on the metal layer 20, connecting different metal wires and establishing connectivity between devices. In this disclosure, the conductive portions are spaced apart on the metal layer 20. The conductive portions can be multiple wire structures arranged in an array on the substrate 10, and the specific positional relationship and shape of each conductive portion can be adaptively adjusted according to the specific application and function of the device.

[0061] In step S30, an insulating layer 30 and a mask layer 40 are sequentially formed on the metal layer 20. The mask layer 40 includes a plurality of mask patterns, and the orthogonal projection of the mask patterns on the substrate 10 covers the orthogonal projection of the conductive part on the substrate 10.

[0062] In the embodiments of this disclosure, an insulating layer 30 and a mask layer 40 are sequentially formed on the metal layer 20. The insulating layer 30 can be composed of multiple film layers. For example, the insulating layer 30 includes a dielectric layer and an oxide layer formed on the metal layer 20. The dielectric layer can be a low-dielectric-constant dielectric layer, with a dielectric constant K < 3. The formation of a low-dielectric-constant dielectric layer can reduce the capacitive effect between metal wires. The oxide layer can be a film layer formed of oxides such as silicon oxide. The insulating layer 30 may also include other film layers besides the dielectric layer and oxide layer. In actual manufacturing processes, the number of film layers can be increased or decreased according to the structure of the semiconductor device.

[0063] like Figure 2As shown, the mask layer 40 may include a spin-on hard mask 401, a sacrificial layer 402, and an anti-reflection layer 403 (ARC) formed sequentially. Of course, the mask layer 40 may also include other film layers for photolithography besides the above-mentioned film layers. The spin-on hard mask 401 may be a spin-on hard mask (SOH) or a spin-on carbon hard mask (SOC), etc.; the sacrificial layer may be a silicon oxynitride or silicon oxide film layer, etc.; the anti-reflection layer 403 is used to prevent light reflected from the bottom from affecting exposure and development during the photolithography process.

[0064] The mask layer 40 formed on the insulating layer 30 has multiple mask patterns, and the orthographic projection of the mask patterns on the substrate 10 covers the orthographic projection of the conductive part on the substrate 10. The formation process of the mask patterns on the mask layer 40 is as follows: a photoresist layer 50 is formed on the mask layer 40; the photoresist layer 50 is exposed and developed to form multiple mask patterns on the mask layer 40.

[0065] In step S40, the insulating layer 30 is etched through the mask layer 40 to form a trench 80 that exposes the conductive part.

[0066] By utilizing multiple mask patterns formed on the mask layer 40, the insulating layer 30 is etched to form trenches 80 that expose the conductive portions. Dry etching can be used to etch the insulating layer 30 to create mask patterns based on the mask patterns. Since the orthogonal projection of the mask patterns onto the substrate 10 covers the orthogonal projection of the conductive portions onto the substrate 10, the surface of the conductive portions is exposed after etching the insulating layer 30.

[0067] In one embodiment of this disclosure, after etching the insulating layer 30, the top surface of the conductive portion can be flush with the bottom surface of the insulating layer 30, and the exposed portion of the conductive portion is the top surface of the conductive portion. In another embodiment of this disclosure, after etching the insulating layer 30, the bottom surface of the insulating layer 30 is lower than the top surface of the conductive portion, and the exposed portion of the conductive portion consists of the top surface of the conductive portion and part of the sidewall of the conductive portion. Both of the above etching methods for the insulating layer 30 are applicable to this disclosure. In order to make the metal conductivity formed by the conductive portion have better contact and connection performance, the bottom surface of the insulating layer 30 can be etched below the top surface of the conductive portion during etching.

[0068] In step S50, an oxygen-free stripping gas is used to remove the mask layer 40.

[0069] After etching the insulating layer 30 through the mask layer 40, the mask layer 40 needs to be removed to form a trench 80 exposing the conductive portion. The mask layer 40 includes a spin-coated hard mask 401, and the removal of the mask layer 40 described in this disclosure mainly refers to the spin-coated hard mask 401 in the mask layer 40.

[0070] In semiconductor device manufacturing processes, the removal method for mask layer 40 typically employs ashing. Ashing is used in semiconductor manufacturing processes to remove and clean the photosensitive coating during the photolithography step. Oxygen is usually chosen as the process gas, and it is combined with other gases to act on the photosensitive coating, causing it to peel off from other materials. However, the stripping gas containing oxygen often has oxidizing properties on metal materials, causing oxidation of the metal layer 20 and forming oxide 100 on it. This significantly reduces the conductivity and contactability of the metal.

[0071] Based on the oxidizing properties of oxygen or oxygen-containing media, while achieving complete removal of the photosensitive coating, other metal materials are prevented from being oxidized, thus ensuring the conductivity and connectivity of the metal layer 20. In the embodiments provided in this disclosure, an oxygen-free stripping gas is used as the process gas to remove the mask layer 40, which can achieve complete removal of the mask layer 40 while ensuring that the metal layer 20 is not oxidized.

[0072] In the embodiments provided in this disclosure, such as Figure 3 and Figure 4 As shown, the mask layer 40 is stripped using an oxygen-free stripping gas. The oxygen-free stripping gas refers to a stripping gas containing no oxygen. Specifically, it includes hydrogen and nitrogen. Due to the strong reducing properties of hydrogen, when nitrogen is used as the carrier gas, the hydrogen-containing stripping gas passes through an ashing treatment device. The hydrogen generates plasma, which then strips the spin-coated hard mask 401 from the insulating layer 30. Alternatively, the oxygen-free stripping gas can also include other types of inert gases as the hydrogen carrier gas, such as helium (He), argon (Ar), or neon (Ne). Since hydrogen and nitrogen do not oxidize the metal layer 20 during the stripping process, oxidation of the exposed metal layer 20 is avoided, ensuring the conductivity of the metal layer 20.

[0073] In the embodiments provided in this disclosure, the mask layer 40 can be removed using an in-situ strip etching process. The method for stripping the mask layer 40 provided in this disclosure uses an in-situ stripping process and oxygen-free stripping gas to strip the mask layer 40, ensuring complete removal of the mask layer 40 while avoiding oxidation of the exposed metal layer 20.

[0074] The volumetric flow rate ratio of nitrogen to hydrogen in the oxygen-free stripping gas is 2:1 to 4:1. Taking the in-situ etching process as an example, the stripping conditions for spin-coated hard mask 401 can be as follows: working power of 700W-900W, working pressure of 60mtorr-80mtorr, working time of 100s-150s, working frequency of 25MHz-29MHz, nitrogen volumetric flow rate of 600scccm-800scccm, and hydrogen volumetric flow rate of 200scccm-300scccm.

[0075] The following are examples of various operating conditions for removing the mask layer 40 using oxygen-free stripping gas:

[0076] Operating Condition 1: The operating frequency is 27MHz, the operating power is 800W, the operating pressure is 70mtorr, the operating time is 130S, the volumetric flow rate of nitrogen is 700scccm, and the volumetric flow rate of hydrogen is 250scccm.

[0077] Operating Condition 2: The operating frequency is 27MHz, the operating power is 700W, the operating pressure is 80mtorr, the operating time is 130S, the volumetric flow rate of nitrogen is 700scccm, and the volumetric flow rate of hydrogen is 250scccm.

[0078] Operating Condition 3: The operating frequency is 27MHz, the operating power is 900W, the operating pressure is 60mtorr, the operating time is 150S, the volumetric flow rate of nitrogen is 800scccm, and the volumetric flow rate of hydrogen is 300scccm.

[0079] Operating Condition 4: The operating frequency is 27MHz, the operating power is 900W, the operating pressure is 60mtorr, the operating time is 150S, the volumetric flow rate of nitrogen is 600scccm, and the volumetric flow rate of hydrogen is 150scccm.

[0080] Operating Condition 5: Operating frequency is 27MHz, operating power is 700W, operating pressure is 70mtorr, operating time is 140S, nitrogen volumetric flow rate is 600scccm, and hydrogen volumetric flow rate is 150scccm.

[0081] The above-mentioned operating conditions are merely illustrative of the working conditions when removing spin-coated hard mask 401 with oxygen-free stripping gas. This disclosure includes, but is not limited to, the operating conditions listed above. In practical applications, the conditions can be adaptively adjusted according to parameters such as the composition and thickness of the mask layer 40.

[0082] like Figure 5As shown, after removing the mask layer 40, a filling layer 70 needs to be formed in the trench 80 to form a bridging structure for the conductive parts. The bridging structure is used for the connection between the conductive parts of different metal layers 20.

[0083] In one embodiment provided in this disclosure, a filling layer 70 is formed within a trench 80. The formation of the filling layer 70 includes: filling the trench 80 with a filling material, wherein the filling material at least fills the trench 80; planarizing the filling material; and removing the filling material located on the surface of the insulating layer 30 to form a filling layer 70 flush with the insulating layer 30.

[0084] When filling the trench 80 with filler material, it is necessary to ensure that the filler material completely fills the trench 80. The filler material can be filled to the level of the surface of the insulating layer 30 or to a level higher than the surface of the insulating layer 30. In order to ensure that the filler material can completely fill the trench 80, the filler material is usually filled to a level higher than the surface of the insulating layer 30 to avoid filling defects in the filler layer 70 formed by the filler material.

[0085] like Figure 6 As shown, the filler material is planarized so that the surface of the filler layer 70 is flush with the surface of the insulating layer 30. Chemical mechanical polishing (CMP) is typically used to planarize the filler material. A polishing slurry is applied to the surface of the filler material, combined with mechanical polishing, to remove any portion of the filler material that protrudes above the surface of the insulating layer 30, making the surface of the filler material sufficiently smooth to form a filler layer 70 that is flush with the surface of the insulating layer 30.

[0086] In another embodiment provided in this disclosure, during the removal of the mask layer 40, stripping gas acts on the top surface of the trench 80, causing the top surface of the trench 80 to form a dome structure. Since the apex of the dome structure is slightly lower than the surface of the insulating layer 30, when the filling layer 70 is formed in the trench 80, connections will occur between the filling layers 70 in multiple trenches 80, resulting in lap short circuits. In order to eliminate the short circuit effect of the dome structure on the top surface of the trench 80 on the wire connection, a protective layer 60 is formed between the insulating layer 30 and the mask layer 40 to protect the trench 80 from being damaged during the semiconductor device manufacturing process.

[0087] like Figures 7 to 11 As shown, the specific process for forming a semiconductor structure with protective layer 60 is as follows:

[0088] Step S601: A metal layer 20, an insulating layer 30, a protective layer 60 and a mask layer 40 are sequentially formed on the substrate 10;

[0089] Step S602: Etch the protective layer 60 and the insulating layer 30 through the mask layer 40 to form a trench 80 that exposes the conductive parts;

[0090] Step S603: Remove the mask layer 40 using oxygen-free stripping gas;

[0091] Step S604: Fill the trench 80 with filler material, the filler material covering at least the surface of the protective layer 60;

[0092] Step S605: Remove the protective layer 60 and the filler material on the surface of the protective layer 60, so that the filler material is flush with the surface of the insulating layer 30 to form the filler layer 70.

[0093] In this process, a metal layer 20, an insulating layer 30, a protective layer 60, and a mask layer 40 are sequentially formed on a substrate. The protective layer 60 is formed between the insulating layer 30 and the mask layer 40, covering the surface of the insulating layer 40. The protective layer 60 protects the surface of the insulating layer 40 during etching and removal of the mask layer 40. The protective layer 60 can be a protective film formed of silicon oxynitride, silicon nitride, or similar materials.

[0094] The protective layer 60 and the insulating layer 30 are etched through the mask layer 40 to expose the surface of the conductive portion of the metal layer 20, forming a trench 80; the mask layer 40 located above the protective layer 60 is removed using an oxygen-free stripping gas. Wherein, as Figure 7 As shown, when etching the protective layer 60 and the insulating layer 30, a photoresist layer 50 can be formed on the mask layer; the photoresist layer 50 is exposed and developed to form multiple mask patterns on the mask layer 40. Figure 8 As shown, multiple mask patterns on the mask layer 40 are used to simultaneously etch the protective layer 60 and the insulating layer 30 to ensure that the same pattern is etched on the protective layer 60 and the insulating layer 30. Of course, multiple mask patterns on the mask layer 40 can also be used to etch the protective layer 60 and the insulating layer 30 separately, so that the protective layer 60 and the insulating layer 30 have the same etching pattern.

[0095] The oxygen-free stripping gas is a stripping gas containing hydrogen and nitrogen, with a hydrogen to nitrogen volume flow ratio of 2:1 to 4:1. After removing the mask layer 40 using the oxygen-free stripping gas, a dome structure is formed on the protective layer 60, such as... Figure 9 As shown, due to the provision of the protective layer 60, a dome structure is avoided from forming on the surface of the insulating layer 30, the top surface shape of the groove 80 formed by the insulating layer 30 is protected, and the length of the groove 80 is prevented from changing.

[0096] like Figure 10As shown, in order to form an overlapping structure that mates with the conductive part, a filler material needs to be filled into the trench 80, and the filler material at least covers the surface of the protective layer 60. When filling the trench 80, it is necessary to ensure that the filler material completely fills the trench 80. The filler material can be filled to the level of the surface of the protective layer 60, or it can be filled above the surface of the protective layer 60, and the filler material can cover the surface of the protective layer 60. To ensure that the filler material completely fills the trench 80, it is preferable that the filler material is filled above the surface of the protective layer 60 and covers the surface of the protective layer 60, avoiding filling defects in the filler layer 70 formed by the filler material.

[0097] like Figure 11 As shown, after the filling material is formed in the trench 80, the protective layer 60 and the filling material above the protective layer 60 are removed, making the filling material flush with the surface of the insulating layer 30 to form the filling layer 70. After the filling material is formed in the trench 80, the protective layer 60 needs to be removed and the filling material needs to be planarized. Chemical mechanical polishing (CMP) is typically used to remove the protective layer 60 and the filling material above it. Polishing fluid is applied to the surface formed by the protective layer 60 and the filling material, combined with mechanical polishing, to remove the filling material above the insulating layer 30 and the protective layer 60, forming the filling layer 70 flush with the surface of the insulating layer 30.

[0098] The aforementioned removal of the protective layer 60 and the filling material above the protective layer 60 can be performed in one step to form a filling layer 70 flush with the surface of the insulating layer 30; or the protective layer 60 and the filling material can be removed multiple times to form a filling layer 70 flush with the surface of the insulating layer 30.

[0099] like Figure 11 As shown, during the removal of the mask layer 40, because the protective layer 60 protects the surface of the insulating layer 30, the surface shape of the insulating layer 30 remains unchanged after the removal of both the mask layer 40 and the protective layer 60. After the filling layer 70 is formed within the trench 80, multiple overlapping structures with good isolation can be formed within the multiple trenches 80. These overlapping structures, in conjunction with conductive parts, form multiple metal wires. By forming the protective layer 60 between the insulating layer 30 and the mask layer 40, when the mask layer 40 is removed using oxygen-free stripping gas, the stripping gas acts on the protective layer 60 formed on the insulating layer 30, preventing the stripping gas from directly acting on the surface of the insulating layer 30 and causing a change in the shape of the insulating layer 30, which in turn changes the length of the trench 80, thus achieving the purpose of protecting the structure of the trench 80.

[0100] The filling material provided in the two embodiments of this disclosure is a conductive material, which can be at least one of copper, titanium, titanium nitride, and tungsten. Furthermore, in other structures of semiconductor devices, the filling material may be a non-conductive material due to the different functions of the filling layer 70. The specific material of the filling layer 70 can be adaptively selected according to the structure and application scenario of the semiconductor device.

[0101] In the embodiments provided in this disclosure, a single photolithography step is provided to illustrate the etching of the insulating layer 30 and the protective layer 60. In actual processes, etching can be done in one step to form the trench 80, or it can be done through multiple etching steps to form the final semiconductor structure. For example, the protective layer 60 can be etched first using the mask layer 40, and then the insulating layer 30 can be etched to form the trench 80 exposed to the conductive part. This disclosure is not limited to etching the trench 80 in one step.

[0102] The semiconductor device formation method disclosed herein involves forming a metal layer 20 with conductive portions, an insulating layer 30, and a mask layer 40 on a substrate 10. After etching the insulating layer 30 through the mask layer 40, a trench 80 exposing the conductive portions is formed. The mask layer 40 is then removed using an oxygen-free stripping gas. This method avoids the oxidation of the metal layer 20 by the stripping gas during the removal of the mask layer 40, ensuring the conductivity of the metal layer 20. Consequently, it improves the connectivity and contact between metal wires and increases the device yield.

[0103] It should be noted that although the steps of the semiconductor device formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0104] This disclosure also provides a semiconductor device fabricated using the semiconductor device formation method described above. The metal wires of this semiconductor device have good contact and connectivity; when connecting the metal wires, problems such as poor contact or short circuits do not occur, resulting in a high-quality device.

[0105] This disclosure also provides a memory that includes the aforementioned semiconductor device and is a high-quality memory with good wire contact and connectivity.

[0106] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0107] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method of forming a semiconductor device, characterized by, include: Provide a substrate; A metal layer is formed on the substrate, the metal layer comprising a plurality of spaced conductive portions; An insulating layer, a protective layer, and a mask layer are sequentially formed on the metal layer. The mask layer includes multiple mask patterns, and the orthogonal projection of the mask patterns on the substrate covers the orthogonal projection of the conductive part on the substrate. The mask layer includes a spin-coated hard mask. The insulating layer is etched through the mask layer to form trenches that expose the conductive parts; The mask layer is removed using an oxygen-free stripping gas containing nitrogen and hydrogen, which is used to remove the spin-coated hard mask.

2. The method according to claim 1, wherein After forming the trench, the method further includes: A filling layer is formed within the trench.

3. The method according to claim 2, wherein The method for forming a filling layer within the trench includes: The trench is filled with a filler material, which at least completely fills the trench. The filler material is planarized by removing the filler material located on the surface of the insulating layer to form a filler layer flush with the surface of the insulating layer.

4. The method according to claim 1, wherein The method further includes: The protective layer is etched simultaneously with the insulating layer through the mask layer.

5. The semiconductor device formation method according to claim 4, characterized in that, After etching the protective layer, the method further includes: The trench is filled with a filler material, which at least covers the surface of the protective layer.

6. The method according to claim 5, wherein After filling the trench with filler material, the method further includes: Remove the protective layer and the filler material above the surface of the protective layer, so that the filler material is flush with the surface of the insulating layer to form a filler layer.

7. The method according to claim 2 or 5, wherein The filling material is a conductive material.

8. The method according to claim 7, wherein The conductive material is at least one of copper, titanium, titanium nitride, and tungsten.

9. The method according to claim 1, wherein The volumetric flow rate ratio of nitrogen to hydrogen in the oxygen-free stripping gas is 2:1 to 4:

1.

10. The method according to claim 1, wherein The working time of the oxygen-free stripping gas is 100S~150S.

11. The method according to claim 1, wherein The working power of the oxygen-free stripping gas is 700W-900W, and the working frequency of the oxygen-free stripping gas is 25 MHz-29 MHz.

12. A semiconductor device, characterized by comprising: It is manufactured using the semiconductor device forming method as described in any one of claims 1-11.

13. A memory, comprising: The memory includes the semiconductor device as described in claim 12.

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