Layout and Its Processing Method, Storage Medium and Program Product

Abstract

The present application provides a layout and its processing method, a storage medium and a program product, so as to improve the integration degree of the layout of semiconductor devices, relating to the field of semiconductor technology, and used to solve the technical problem of low integration degree of semiconductor devices. The layout has a first storage area and a second storage area; the layout includes a substrate array pattern and a storage pattern. The substrate array pattern includes a plurality of plug patterns arranged at intervals; the storage pattern includes a magnetic tunnel junction pattern located in the first storage area and a capacitor pattern located in the second storage area. The magnetic tunnel junction pattern and the plug pattern located in the first storage area have a partial overlapping area, and the capacitor pattern and the plug pattern located in the second storage area have a partial overlapping area. When producing using this layout, the manufacturing process of dynamic random access memory can be used to manufacture magnetic random access memory, so that the storage density of the magnetic random access memory is increased, and the integration degree of semiconductor devices is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a layout and a processing method thereof, a storage medium, and a program product. Background Art

[0002] With the development of semiconductor technology, the integration degree of semiconductor devices has been continuously improved, and the size of semiconductor devices has become smaller and smaller. The size of a memory, especially a Magnetic Random Access Memory (MRAM for short), needs to be further miniaturized to improve the integration degree of the magnetic random access memory. In order to further improve the integration degree of semiconductor devices, it is necessary to further optimize the layout of semiconductor devices. Summary of the Invention

[0003] In view of the above problems, embodiments of the present application provide a layout and a processing method thereof, a storage medium, and a program product to improve the integration degree of semiconductor devices.

[0004] In a first aspect of embodiments of the present application, a layout is provided. The layout has a first storage area and a second storage area at least partially surrounding the first storage area. The layout includes: a substrate array pattern, the substrate array pattern including a plurality of plug patterns arranged at intervals; a storage pattern, the storage pattern including a magnetic tunnel junction pattern located in the first storage area and a capacitor pattern located in the second storage area. The magnetic tunnel junction pattern and the plug pattern located in the first storage area have a partial overlapping area, and the capacitor pattern and the plug pattern located in the second storage area have a partial overlapping area.

[0005] For the layout as described above, the substrate array pattern includes: a substrate pattern, the substrate pattern including a plurality of active region sub-patterns arranged at intervals, the active region sub-patterns extending along a first direction; a plurality of first data line patterns arranged at intervals and extending along a second direction, the second direction intersecting with the first direction, and each first data line pattern and the active region sub-pattern located in the same column having a partial overlapping area; a plurality of the plug patterns are located between two adjacent first data line patterns and have a partial overlapping area with the active region sub-patterns.

[0006] For the layout as described above, the first data line pattern includes a plurality of conductive column sub-patterns arranged at intervals and a plurality of wire sub-patterns extending along the first direction; each conductive column sub-pattern and an active region sub-pattern have a partial overlapping area, and each wire sub-pattern passes through the conductive column sub-patterns located in the same column; the part of the wire sub-pattern located in the first storage area forms a source line pattern, and the part of the wire sub-pattern located in the second storage area forms a bit line pattern.

[0007] For the layout as described above, a plurality of word line patterns which are arranged at intervals and extend in a third direction are further disposed within the substrate pattern. The third direction intersects with the first direction and the third direction intersects with the second direction; the word line patterns intersect with the active region sub-patterns in the same row and pass through the active region sub-patterns.

[0008] For the layout as described above, a second insulating pattern is further disposed between the portion of the same word line pattern located in the first storage region and the portion located in the second storage region.

[0009] For the layout as described above, there are two word line patterns that intersect with the active region sub-patterns in the same row. These two word line patterns divide the active region sub-patterns they intersect into a first contact region in the middle and second contact regions on both sides of the first contact region; the conductive pillar sub-pattern overlaps with a partial region of the first contact region, and the plug sub-pattern overlaps with a partial region of the second contact region.

[0010] For the layout as described above, the plug sub-pattern includes a first plug sub-pattern and a second plug sub-pattern corresponding to the first plug sub-pattern; the first plug sub-pattern is located between adjacent first data line patterns, and the second plug sub-pattern has a partial overlapping region with both the first data line pattern and the first plug sub-pattern; the second plug sub-pattern located in the first storage region forms a first electrode contact pattern, and the second plug sub-pattern located in the second storage region forms a capacitor contact pad pattern.

[0011] For the layout as described above, each capacitor pattern has a partial overlapping region with one capacitor contact pad pattern, and a plurality of capacitor patterns are arranged in a hexagonal close-packed arrangement.

[0012] For the layout as described above, the layout further includes a conductive pattern located in the second storage region, and the conductive pattern covers the capacitor pattern.

[0013] For the layout as described above, the layout further includes a plurality of second electrode contact patterns, and each second electrode contact pattern overlaps at least a partial region with one magnetic tunnel junction pattern.

[0014] For the layout as described above, the magnetic tunnel junction patterns are arranged in a hexagonal close-packed arrangement, and the second electrode contact patterns are arranged in a rectangular array.

[0015] The layout as described above further includes a plurality of second data line patterns. The plurality of second data line patterns are arranged at intervals and extend along the second direction. Each second data line pattern has a partial overlapping area with the second electrode contact pattern and passes through the second electrode contact patterns located in the same column.

[0016] The layout provided by the embodiment of the present application has at least the following advantages:

[0017] The layout in the embodiment of the present application has a first storage area and a second storage area that at least partially surrounds the first storage area. The layout includes a substrate array pattern and a storage pattern. The substrate array pattern includes a plurality of plug patterns arranged at intervals. The storage pattern includes a magnetic tunnel junction pattern located in the first storage area and a capacitor pattern located in the second storage area. Among them, the magnetic tunnel junction pattern has a partial overlapping area with the plug pattern located in the first storage area, and the capacitor pattern has a partial overlapping area with the plug pattern located in the second storage area. The magnetic tunnel junction pattern and the substrate array pattern located in the first storage area can be used to form the pattern of a magnetic random access memory, and the capacitor pattern and the substrate array pattern located in the second storage area can be used to form the pattern of a dynamic random access memory, so that the layout includes the pattern of a dynamic random access memory and the pattern of a magnetic random access memory, that is, the pattern of a dynamic random access memory and the pattern of a magnetic random access memory are integrated in one layout. When subsequent production is carried out using this layout, the preparation process of the dynamic random access memory can be used to prepare the magnetic random access memory, so that the storage density of the magnetic random access memory is increased, thereby further increasing the integration degree of the magnetic random access memory and improving the integration degree of the semiconductor device.

[0018] The second aspect of the embodiment of the present application provides a method for processing a layout. The layout has a first storage area and a second storage area that at least partially surrounds the first storage area. The processing method includes: forming a substrate array pattern in a blank layout, the substrate array pattern including a plurality of plug patterns arranged at intervals; forming a storage pattern, the storage pattern including a magnetic tunnel junction pattern located in the first storage area and a capacitor pattern located in the second storage area, the magnetic tunnel junction pattern having a partial overlapping area with the plug pattern located in the first storage area, and the capacitor pattern having a partial overlapping area with the plug pattern located in the second storage area.

[0019] The method for processing the layout as described above, forming a substrate array pattern in the blank layout, where the substrate array pattern includes a plurality of plug patterns arranged at intervals, includes: forming a substrate pattern in the blank layout, where the substrate pattern includes a plurality of active region sub-patterns arranged at intervals, and the active region sub-patterns extend along a first direction; forming a plurality of first data line patterns arranged at intervals and extending along a second direction, where the second direction intersects the first direction; each of the first data line patterns has a partial overlap region with the active region sub-patterns located in the same column; forming a plurality of plug patterns located between two adjacent first data line patterns, and the plurality of plug patterns have a partial overlap region with the active region sub-patterns.

[0020] The method for processing the layout as described above, forming a storage pattern, includes: forming an initial magnetic tunnel junction pattern that covers the substrate array pattern; forming a first pattern in the initial magnetic tunnel junction pattern located in the first storage area, and the initial magnetic tunnel junction pattern with the first pattern forms the magnetic tunnel junction pattern; removing the initial magnetic tunnel junction pattern located in the second storage area; forming an initial capacitor pattern that covers the magnetic tunnel junction pattern in the first storage area and the substrate array pattern in the second storage area; forming a second pattern in the initial capacitor pattern located in the second storage area, and the initial capacitor pattern with the second pattern forms the capacitor pattern; removing the initial capacitor pattern located in the first storage area.

[0021] The method for processing the layout as described above, after forming the storage pattern, further includes: forming an initial conductive pattern that covers the magnetic tunnel junction pattern in the first storage area and the capacitor pattern in the second storage area; removing the initial conductive pattern located in the first storage area, and the remaining initial conductive pattern forms the conductive pattern.

[0022] The method for processing the layout as described above, after removing the initial conductive pattern located in the first storage area and the remaining initial conductive pattern forms the conductive pattern, further includes: forming an initial second electrode contact pattern that covers the magnetic tunnel junction pattern in the first storage area and the conductive pattern in the second storage area; forming a third pattern in the initial second electrode contact pattern located in the first storage area, and the initial second electrode contact pattern with the third pattern forms the second electrode contact pattern; removing the initial second electrode contact pattern located in the second storage area.

[0023] The method for processing the layout as described above, wherein the second electrode contact patterns are arranged in a rectangular array; after removing the initial second electrode contact patterns in the second storage area, the method further includes: forming a plurality of second data line patterns that are spaced apart and extend in the second direction, each of the second data line patterns having a partial overlapping area with the second electrode contact patterns and passing through the second electrode contact patterns in the same column.

[0024] The method for processing the layout provided by the embodiment of the present application has at least the following advantages:

[0025] The layout in the embodiment of the present application has a first storage area and a second storage area that at least partially surrounds the first storage area. In the method for processing the layout, a substrate array pattern with a plurality of spaced plug patterns is formed in a blank layout, and a storage pattern is formed. The storage pattern includes a magnetic tunnel junction pattern in the first storage area and a capacitor pattern in the second storage area. The magnetic tunnel junction pattern has a partial overlapping area with the plug pattern in the first storage area, and the capacitor pattern has a partial overlapping area with the plug pattern in the second storage area. The magnetic tunnel junction pattern and the substrate array pattern in the first storage area can be used to form the pattern of a magnetic random access memory, and the capacitor pattern and the substrate array pattern in the second storage area can be used to form the pattern of a dynamic random access memory, so that the formed layout includes the pattern of a dynamic random access memory and the pattern of a magnetic random access memory. When subsequent production is carried out using this layout, the preparation process of the dynamic random access memory can be used to prepare the magnetic random access memory, so that the storage density of the magnetic random access memory is increased, thereby further increasing the integration degree of the magnetic random access memory and improving the integration degree of the semiconductor device.

[0026] A third aspect of the embodiment of the present application provides a storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above-mentioned processing method is implemented. The storage medium in the embodiment of the present application is used to implement the above-mentioned processing method, and thus has at least the advantages of the above-mentioned processing method. For specific effects, refer to the above description and will not be elaborated here.

[0027] A fourth aspect of the embodiment of the present application provides a program product, including a computer program that implements the above-mentioned processing method when executed by a processor. The program product in the embodiment of the present application implements the above-mentioned processing method, and thus has at least the advantages of the above-mentioned processing method. For specific effects, refer to the above description and will not be elaborated here. Description of the Drawings

[0028] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0029] Figure 1 Schematic diagram of the core area and the peripheral area of the layout in the embodiment of the present application;

[0030] Figure 2 Schematic diagram of the magnetic tunnel junction pattern in the embodiment of the present application;

[0031] Figure 3 Schematic diagram of the capacitor pattern in the embodiment of the present application;

[0032] Figure 4 Schematic diagram of the active region sub-pattern of the first storage area in the embodiment of the present application;

[0033] Figure 5 Schematic diagram of the active region sub-pattern of the second storage area in the embodiment of the present application;

[0034] Figure 6 Schematic diagram of the word line pattern of the first storage area in the embodiment of the present application;

[0035] Figure 7 Schematic diagram of the word line pattern of the second storage area in the embodiment of the present application;

[0036] Figure 8 Schematic diagram of the conductive column pattern of the first storage area in the embodiment of the present application;

[0037] Figure 9 Schematic diagram of the conductive column pattern of the second storage area in the embodiment of the present application;

[0038] Figure 10 Schematic diagram of the conductive line pattern of the first storage area in the embodiment of the present application;

[0039] Figure 11 Schematic diagram of the conductive line pattern of the second storage area in the embodiment of the present application;

[0040] Figure 12 Schematic diagram of the first plug pattern of the first storage area in the embodiment of the present application;

[0041] Figure 13 Schematic diagram of the first plug pattern of the second storage area in the embodiment of the present application;

[0042] Figure 14Schematic diagram of the second plug pattern of the first storage area in the embodiment of the present application;

[0043] Figure 15 Schematic diagram of the second plug pattern of the second storage area in the embodiment of the present application;

[0044] Figure 16 Schematic diagram of the conductive pattern of the second storage area in the embodiment of the present application;

[0045] Figure 17 Schematic diagram of the second electrode contact pattern of the first storage area in the embodiment of the present application;

[0046] Figure 18 Schematic diagram of the second data line pattern of the first storage area in the embodiment of the present application;

[0047] Figure 19 Flowchart of the processing method of the layout in the embodiment of the present application.

[0048] Explanation of reference numerals:

[0049] 10 - Core area; 11 - First storage area;

[0050] 111 - Active region sub - pattern; 1111 - First contact area;

[0051] 1112 - Second contact area; 112 - Isolation sub - pattern;

[0052] 113 - Word line pattern; 114 - First data line pattern;

[0053] 1141 - Conductive pillar pattern; 1142 - Conductive wire sub - pattern;

[0054] 115 - Plug pattern; 1151 - First plug pattern;

[0055] 1152 - Second plug pattern; 116 - Capacitor pattern;

[0056] 117 - Conductive pattern; 12 - Second storage area;

[0057] 121 - Magnetic tunnel junction pattern; 122 - Second electrode contact pattern;

[0058] 123 - Second data line pattern; 20 - Peripheral area. Detailed implementation manners

[0059] In order to improve the integration of semiconductor devices, the layout in the embodiments of the present application includes an array pattern and a storage pattern. The substrate array pattern includes a plurality of plug patterns arranged at intervals. The storage pattern includes a magnetic tunnel junction pattern located in the first storage area and a capacitor pattern located in the second storage area. The magnetic tunnel junction pattern and the plug pattern located in the first storage area have a partial overlapping area, and the capacitor pattern and the plug pattern located in the second storage area have a partial overlapping area. By forming the substrate array pattern, the magnetic tunnel junction pattern, and the capacitor pattern in the layout, when subsequent production is carried out using this layout, a magnetic random access memory can be prepared using the manufacturing process of a dynamic random access memory, so that the storage density of the magnetic random access memory is increased, thereby further increasing the integration of the magnetic random access memory and improving the integration of semiconductor devices.

[0060] In order to make the above objects, features, and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0061] Reference Figure 1 , the layout has a first storage area 11 and a second storage area 12, and different memory patterns are formed in the first storage area 11 and the second storage area 12. For example, the pattern of a magnetic random access memory is formed in the first storage area 11, and the pattern of a dynamic random access memory is formed in the second area. As Figure 1 shown, the first storage area 11 and the second storage area 12 form a core area 10, and the core area 10 can also be called an array area (Array Area). The core area 10 is used to form the storage units of the memory. The layout also includes a peripheral area (Peripheral Area) 20 that surrounds the core area 10 in a circle, and the peripheral area 20 is used to form the control circuit of the memory.

[0062] Among them, the second storage area 12 at least partially surrounds the first storage area 11. For example, the second storage area 12 completely surrounds the first storage area 11, or the second storage area 12 partially surrounds the first storage area 11. Specifically, one edge of the first storage area 11 partially overlaps with one edge of the second storage area 12. As Figure 1As shown, the left edge of the first storage area 11 partially coincides with the left edge of the second storage area 12. With such a setting, the first storage area 11 can be adjacent to the peripheral area 20, facilitating the connection of the pattern in the first storage area 11 to the peripheral area 20. In addition, three sides of the first storage area 11 are adjacent to the second storage area 12, facilitating the configuration of an insulating pattern between the first storage area 11 and the second storage area 12.

[0063] Reference Figure 2 and Figure 3 , the layout includes a substrate array pattern and a storage pattern. The substrate array pattern includes a plurality of plug patterns 115 arranged at intervals, and the plug patterns 115 and the storage pattern have a partially overlapping area to connect the plug patterns 115 and the storage pattern.

[0064] Specifically, as Figure 2 and Figure 3 shown, the storage pattern includes a capacitor pattern 116 and a magnetic tunnel junction (MTJ) pattern 121. The magnetic tunnel junction pattern 121 is located in the first storage area 11, and the magnetic tunnel junction pattern 121 and the plug pattern 115 located in the first storage area 11 have a partially overlapping area. The capacitor pattern 116 is located in the second storage area 12, and the capacitor pattern 116 and the plug pattern 115 located in the second storage area 12 have a partially overlapping area.

[0065] In a possible example, referring to Figures 4 to 15 , the substrate array pattern includes a substrate pattern, a first data line pattern 114, and a plug pattern 115. Among them, the substrate pattern, the first data line pattern 114, and the plug pattern 115 are located in different pattern layers of the layout, and are subsequently transferred to different photomasks to form photomask patterns, and are respectively used for different patterning steps of manufacturing semiconductor devices to form the required semiconductor devices on the semiconductor substrate.

[0066] Reference Figure 4 and Figure 5 , the substrate pattern includes a plurality of active region sub-patterns 111 arranged at intervals, and the active region sub-patterns 111 are used to define the positions of active regions in the semiconductor substrate. The active region sub-patterns 111 extend in the first direction ( Figure 4 and Figure 5 shown in the Z direction) and are arranged in parallel. Adjacent active region sub-patterns 111 are in the second direction ( Figure 4 and Figure 5They are staggered in the second direction (the Y direction shown), and the second direction intersects with the first direction, that is, there is an included angle between the second direction and the first direction. Between each active region sub-pattern 111 is an isolation sub-pattern 112, and the isolation sub-pattern 112 is used to define the position of the shallow trench isolation (STI) in the semiconductor substrate. The active region sub-pattern 111 and the isolation sub-pattern 112 are transferred onto the same photomask together.

[0067] Reference Figure 6 and Figure 7 , and a plurality of word line patterns 113 arranged at intervals are further disposed in the substrate pattern. The word line patterns 113 and the active region sub-patterns 111 are located in different pattern layers of the layout. The word line patterns 113 are used to define the positions of the word lines in the semiconductor substrate, and the bit lines can be buried word lines. The plurality of word line patterns 113 extend in the third direction ( Figure 6 the X direction shown), and are arranged in parallel in the second direction ( Figure 6 the Y direction shown). Among them, the third direction intersects with the first direction, and the third direction intersects with the second direction. Exemplarily, the second direction and the third direction can be perpendicular to each other, and the first direction has included angles with both the second direction and the third direction.

[0068] As Figure 6 and Figure 7 shown, the word line pattern 113 intersects with the active region sub-patterns 111 in the same row and passes through the active region sub-patterns 111. The word line pattern 113 divides the active region sub-patterns 111 into different regions. When the active region sub-patterns 111 and the word line patterns 113 are transferred onto the semiconductor substrate to form the active regions and the word lines, different regions of the active regions are electrically connected to different structures. For example, the active regions are divided by the word lines into regions electrically connected to the bit lines (BL for short), and regions electrically connected to the capacitance. The layer of the word line in contact with the active region is a dielectric layer, and the dielectric layer can be used as the gate oxide layer to ensure insulation between the word line and the active region.

[0069] In some possible embodiments, there are two word line patterns 113 intersecting with the active region sub-patterns 111 in the same row. These two word line patterns 113 divide the active region sub-patterns 111 intersecting with them into a first contact region 1111 in the middle, and second contact regions 1112 on both sides of the first contact region 1111. As Figure 6 and Figure 7 shown, each active region sub-pattern 111 is divided into a first contact region 1111 and second contact regions 1112 by two word line patterns 113. The second contact regions 1112 are located on both sides of the first contact region 1111, and the shape of the first contact region 1111 can be a parallelogram.

[0070] It should be noted that some of the multiple word line patterns 113 will simultaneously pass through the first storage region 11 and the second storage region 12, while another part of the word line patterns 113 will only pass through the second storage region 12. There is at least one word line pattern 113 that will simultaneously pass through the first storage region 11 and the second storage region 12. In one word line pattern 113, a second insulating pattern is further disposed between the part located in the first storage region 11 and the part located in the second storage region 12.

[0071] Specifically, each word line pattern 113 in the second storage region 12 corresponds to a word line pattern 113 in the first storage region 11. The word line pattern 113 in the second storage region 12 and its corresponding word line pattern 113 in the first storage region 11 are located on the same straight line along the third direction, and an insulating pattern is provided between the word line pattern 113 in the second storage region 12 and its corresponding word line pattern 113 in the first storage region 11.

[0072] With such a setting, when the word line pattern 113 is transferred to the semiconductor substrate to form a word line, the word lines located in the first storage region 11 and the word lines located in the second storage region 12 are insulated from each other. The first storage region 11 and the second storage region 12 can be electrically connected to different control circuits, so that the dynamic random access memory and the magnetic random access memory can be driven separately, improving the flexibility of semiconductor device control. In addition, each word line located in the first storage region 11 and a word line located in the second storage region 12 are located on the same straight line, which is convenient for the fabrication of word lines.

[0073] Reference Figures 8 to 11 , there are multiple first data line patterns 114. The multiple first data line patterns 114 are arranged at intervals and extend along the second direction ( Figure 10 the Y direction shown), the second direction intersects the first direction, and each first data line pattern 114 has a partial overlapping region with the active region sub-pattern 111 located in the same column.

[0074] As Figures 8 to 11 shown, each first data line pattern 114 includes a plurality of conductive column sub-patterns 1141 arranged at intervals, and a plurality of wire sub-patterns 1142 extending along the second direction. The conductive column sub-patterns 1141 and the wire sub-patterns 1142 are located on different pattern layers of the layout.

[0075] Reference Figure 8 and Figure 9, the part of the conductive pillar pattern 1141 located in the first storage area 11 is used to define the position of the source line contact on the semiconductor substrate. The part of the conductive pillar pattern 1141 located in the second storage area 12 defines the position of the bit line contact on the semiconductor substrate. Refer to Figure 10 and Figure 11 , the part of the conductive wire pattern 1142 located in the first storage area 11 forms a source line pattern, and the source line pattern is used to define the position of the source line on the semiconductor substrate. The part of the conductive wire pattern 1142 located in the second storage area 12 forms a bit line pattern, and the bit line pattern is used to define the position of the bit line on the semiconductor substrate.

[0076] Continue to refer to Figures 8 to 11 , each conductive pillar pattern 1141 has a partial overlap area with an active region sub-pattern 111, and each conductive wire pattern 1142 passes through the conductive pillar patterns 1141 located in the same column. Specifically, a partial area of the first contact area 1111 of the conductive pillar pattern 1141 overlaps with the active region sub-pattern 111. As Figure 8 and Figure 9 shown, the conductive pillar pattern 1141 has a partial overlap area with the middle area (the first contact area 1111) of the active region sub-pattern 111. The two adjacent columns of conductive pillar patterns 1141 are staggered in the second direction.

[0077] Refer to Figures 12 to 15 , the plug pattern 115 is located between two adjacent first data line patterns 114 and has a partial overlap area with the active region sub-pattern 111. Specifically, a partial area of the plug pattern 115 overlaps with the second contact area 1112, that is, the plug pattern 115 has a partial overlap area with the edge area of the active region sub-pattern 111.

[0078] In a possible example, as Figures 12 to 15 shown, the plug pattern 115 includes a first plug sub-pattern 1151 and a second plug sub-pattern 1152, and the first plug sub-pattern 1151 and the second plug sub-pattern 1152 are located in different pattern layers in the layout. The number of the first plug sub-patterns 1151 is multiple, and the multiple first plug sub-patterns 1151 are arranged at intervals. The number of the second plug sub-patterns 1152 is multiple, and the multiple second plug sub-patterns 1152 are arranged at intervals. The multiple second plug sub-patterns 1152 correspond to the multiple first plug sub-patterns 1151 one by one, that is, one first plug sub-pattern 1151 corresponds to one second plug sub-pattern 1152. The corresponding first plug sub-pattern 1151 and the second plug sub-pattern 1152 have a partial overlap area.

[0079] Among them, the first plug pattern 1151 is located between adjacent first data line patterns 114, as Figure 12 and Figure 13 shown, the first plug pattern 1151 is also located between adjacent word line patterns 113. The first plug pattern 1151 located in the first storage area 11 is used to define the position where the first electrode contact is made, and the first plug pattern 1151 located in the second storage area 12 is used to define the position of the capacitor contact (Node Contact). As Figure 12 and Figure 13 shown, multiple first plug patterns 1151 can be arranged in a matrix array, that is, every four first plug patterns 1151 form a group, and a group of first plug patterns 1151 encloses a virtual rectangle, and each first plug pattern 1151 in a group of first plug patterns 1151 is respectively located at a vertex of the virtual rectangle.

[0080] Referring to Figure 14 and Figure 15 , the second plug pattern 1152 has a partial overlap area with both the first data line pattern 114 and the first plug pattern 1151. Each second plug pattern 1152 can also have a partial overlap area with two adjacent word line patterns 113. For example, as Figure 14 and Figure 15 shown, the upper side area of each second plug pattern 1152 partially overlaps with one word line pattern 113, and the lower side area of each second plug pattern 1152 partially overlaps with another word line pattern 113, and these two word line patterns 113 are adjacent.

[0081] Multiple second plug patterns 115 can be arranged in a hexagonal close-packed arrangement, that is, every six second plug patterns 1152 form a group, and a group of second plug patterns 1152 encloses a virtual regular hexagon, and each second plug pattern 1152 in a group of second plug patterns 1152 is respectively located at a vertex of the virtual regular hexagon to increase the arrangement density of the second plug pattern 1152.

[0082] The second plug pattern 1152 located in the first storage area 11 forms a first electrode contact pattern, and the first electrode contact pattern is used to define the position of the first electrode contact, and the first electrode contact can be a bottom electrode contact. The second plug pattern 1152 located in the second storage area 12 forms a capacitor landing pad pattern, and the capacitor landing pad pattern is used to define the position of the capacitor landing pad.

[0083] Refer to Figure 14 , Figure 15 , Figure 2 and Figure 3The magnetic tunnel junction pattern 121 is located in the first storage area 11 and is used to define the position of the magnetic tunnel junction. The number of magnetic tunnel junction patterns 121 located in the first storage area 11 is multiple, and the multiple magnetic tunnel junction patterns 121 are arranged at intervals. The multiple magnetic tunnel junction patterns 121 can be arranged in a hexagonal close-packed manner, and each magnetic tunnel junction pattern 121 has a partial overlap area with a first electrode contact pattern.

[0084] The capacitor pattern 116 is located in the second storage area 12 and is used to define the position of the capacitor. There are multiple capacitor patterns 116 located in the second storage area 12, and the multiple capacitor patterns 116 are arranged at intervals. The multiple capacitor patterns 116 are arranged in a hexagonal close-packed manner, and each capacitor pattern 116 has a partial overlap area with a capacitor contact pad pattern.

[0085] refer to Figure 3 and Figure 16 The layout also includes a conductive pattern 117 located in the second storage area 12, and the conductive pattern 117 covers the capacitor pattern 116. The conductive pattern 117 may fill the second storage area 12, and the conductive pattern 117 is used to define the position of the conductive layer, and the conductive layer may be a whole layer structure, which covers the capacitor to electrically connect the capacitor to the control circuit.

[0086] refer to Figure 2 and Figure 17 The layout further includes a plurality of second electrode contact patterns 122, each of which overlaps at least partially with a magnetic tunnel junction pattern 121. The second electrode contact pattern 122 is used to define the position of a second electrode contact, which may be a top electrode contact.

[0087] like Figure 17 As shown, the magnetic tunnel junction patterns 121 are arranged in a hexagonal close packing arrangement, and the second electrode contact patterns 122 are arranged in a rectangular array. The overlapping positions of the magnetic tunnel junction patterns 121 and the second electrode contact patterns 122 in the same row are the same, and the overlapping positions of the magnetic tunnel junction patterns 121 and the second electrode contact patterns 122 in two adjacent rows are different. In this way, the second electrode contact patterns 122 arranged in a rectangular array can be formed on the magnetic tunnel junction patterns 121 arranged in a hexagonal close packing arrangement, so that the second data line patterns 123 (reference Figure 18 ) can be a straight line.

[0088] like Figure 18As shown, the layout further includes a plurality of second data line patterns 123, which are arranged at intervals and extend along the second direction. Each second data line pattern 123 has a partial overlapping area with the second electrode contact pattern 122 and passes through the second electrode contact patterns 122 located in the same column. As Figure 18 shown, the second data line patterns 123 and the first data line patterns 114 are alternately arranged in the third direction.

[0089] In summary, the layout in the embodiment of the present application has a first storage area 11 and a second storage area 12 that at least partially surrounds the first storage area 11. The layout includes a substrate array pattern and a storage pattern. The substrate array pattern includes a plurality of plug patterns 115 arranged at intervals. The storage pattern includes a magnetic tunnel junction pattern 121 located in the first storage area 11 and a capacitor pattern 116 located in the second storage area 12. Among them, the magnetic tunnel junction pattern 121 has a partial overlapping area with the plug pattern 115 located in the first storage area 11, and the capacitor pattern 116 has a partial overlapping area with the plug pattern 115 located in the second storage area 12. The magnetic tunnel junction pattern 121 and the substrate array pattern located in the first storage area 11 can be used to form the pattern of a magnetic random access memory, and the capacitor pattern 116 and the substrate array pattern located in the second storage area 12 can be used to form the pattern of a dynamic random access memory, so that the layout includes the pattern of a dynamic random access memory and the pattern of a magnetic random access memory, that is, the pattern of a dynamic random access memory and the pattern of a magnetic random access memory are integrated in one layout. When subsequent production is carried out using this layout, the preparation process of the dynamic random access memory can be used to prepare the magnetic random access memory, so that the storage density of the magnetic random access memory is increased, thereby further increasing the integration degree of the magnetic random access memory and improving the integration degree of the semiconductor device.

[0090] The embodiment of the present application further provides a method for processing a layout, such as Figure 1 shown, the layout has a first storage area 11 and a second storage area 12 that at least partially surrounds the first storage area 11. Different memory patterns are formed in the first storage area 11 and the second storage area 12. For example, the first storage area 11 forms the pattern of a magnetic random access memory, and the second area forms the pattern of a dynamic random access memory. Refer to Figure 19 , the method for processing the layout includes the following steps:

[0091] Step S100: Form a substrate array pattern in a blank layout, and the substrate array pattern includes a plurality of plug patterns arranged at intervals.

[0092] Refer to Figure 2 and Figure 3, multiple plug patterns 115 can be arranged in an array and distributed in the first storage area 11 and the second storage area 12. In a possible example, forming a substrate array pattern in a blank layout, the substrate array pattern includes a plurality of plug patterns arranged at intervals, may include the following process:

[0093] Form a substrate pattern in the blank layout, the substrate pattern includes a plurality of active region sub-patterns arranged at intervals, and the active region sub-patterns extend along the first direction.

[0094] Reference Figure 6 And Figure 7 , the active region sub-pattern 111 extends along the first direction ( Figure 5 the Z direction shown) and is arranged in parallel. Adjacent active region sub-patterns 111 are staggered in the third direction ( Figure 5 the X direction shown), and the second direction intersects the first direction. A plurality of word line patterns 113 arranged at intervals are also configured in the substrate pattern. The plurality of word line patterns 113 extend along the third direction ( Figure 5 the X direction shown), and are arranged in parallel in the second direction ( Figure 5 the Y direction shown). Among them, the third direction intersects the first direction, and the third direction intersects the second direction. The word line pattern 113 intersects the active region sub-pattern 111 in the same row and passes through the active region sub-pattern 111, and the word line pattern 113 divides the active region sub-pattern 111 into different regions. Exemplarily, there are two word line patterns 113 intersecting the active region sub-pattern 111 in the same row, and these two word line patterns 113 separate the active region sub-pattern 111 they intersect into a first contact region 1111 in the middle and second contact regions 1112 on both sides of the first contact region 1111.

[0095] After forming the substrate pattern, form a plurality of first data line patterns arranged at intervals and extending along the second direction, and the second direction intersects the first direction; each first data line pattern has a partial overlapping region with the active region sub-pattern in the same column.

[0096] Reference Figure 10 And Figure 11 , there are a plurality of first data line patterns 114, and the plurality of first data line patterns 114 are arranged at intervals and extend along the second direction ( Figure 10As shown in the Y direction, the second direction intersects the first direction, and each first data line pattern 114 has a partial overlapping region with the active region sub-pattern 111 located in the same column. Exemplarily, each first data line includes a plurality of spaced-apart conductive pillar patterns 1141 and a plurality of wire sub-patterns 1142 extending in the second direction. Each conductive pillar pattern 1141 has a partial overlapping region with an active region sub-pattern 111, and each wire sub-pattern 1142 passes through the conductive pillar patterns 1141 located in the same column. The portion of the wire sub-pattern 1142 located in the first storage region 11 forms a source line pattern, and the portion of the wire sub-pattern 1142 located in the second storage region 12 forms a bit line pattern.

[0097] After forming the first data line pattern, a plurality of plug patterns are formed between two adjacent first data line patterns, and the plurality of plug patterns have a partial overlapping region with the active region sub-pattern.

[0098] Reference Figure 14 and Figure 15 As shown in FIGS. and, the plug pattern 115 includes a first plug sub-pattern 1151 and a second plug sub-pattern 1152. The number of the first plug sub-patterns 1151 is multiple, and the multiple first plug sub-patterns 1151 are spaced apart. The multiple first plug sub-patterns 1151 can be arranged in a matrix array. The number of the second plug sub-patterns 1152 is multiple, and the multiple second plug sub-patterns 1152 are spaced apart and correspond to the first plug sub-patterns 1151 one by one. The corresponding first plug sub-pattern 1151 and the second plug sub-pattern 1152 have a partial overlapping region. The multiple second plug patterns 115 can be arranged in a hexagonal close-packed manner.

[0099] Reference Figure 12 and Figure 13 As shown in FIGS. and, the first plug sub-pattern 1151 is located between two adjacent first data line patterns 114 and has a partial overlapping region with the active region sub-pattern 111. The second plug sub-pattern 1152 has a partial overlapping region with both the first data line pattern 114 and the first plug sub-pattern 1151. The second plug sub-pattern 1152 located in the first storage region 11 forms a first electrode contact pattern, and the second plug sub-pattern 1152 located in the second storage region 12 forms a capacitor contact pad pattern.

[0100] Step S200: Form a storage pattern, where the storage pattern includes a magnetic tunnel junction pattern located in the first storage region and a capacitor pattern located in the second storage region. The magnetic tunnel junction pattern has a partial overlapping region with the plug pattern located in the first storage region, and the capacitor pattern has a partial overlapping region with the plug pattern located in the second storage region.

[0101] In some possible examples, forming the storage pattern may include the following process:

[0102] An initial magnetic tunnel junction pattern is formed, and the initial magnetic tunnel junction pattern covers the substrate array pattern. The substrate array pattern is partially located in the first storage area and another part is located in the second storage area, and the initial magnetic tunnel junction pattern covers the entire substrate array pattern. The initial magnetic tunnel junction pattern is a closed figure and there are no holes inside the closed figure.

[0103] After forming the initial magnetic tunnel junction pattern, a first pattern is formed in the initial magnetic tunnel junction pattern located in the first storage area, and the initial magnetic tunnel junction pattern with the first pattern forms a magnetic tunnel junction pattern. Refer to Figure 2 , that is, the initial tunnel junction pattern located in the first storage area 11 is processed to form a magnetic tunnel junction pattern 121. The number of magnetic tunnel junction patterns 121 is multiple, and the multiple magnetic tunnel junction patterns 121 are arranged at intervals. The multiple magnetic tunnel junction patterns 121 can be arranged in a hexagonal close-packed manner, and each magnetic tunnel junction pattern 121 has a partial overlapping area with a plug pattern 115 in the substrate array pattern located in the first storage area 11.

[0104] After forming the magnetic tunnel junction pattern, the initial magnetic tunnel junction pattern located in the second storage area is removed. The remaining initial magnetic tunnel junction pattern is removed, and the magnetic tunnel junction pattern is retained. No other patterns are covered on the substrate array pattern in the second storage area.

[0105] After removing the initial magnetic tunnel junction pattern located in the second storage area, an initial capacitor pattern is formed. The initial capacitor pattern covers the magnetic tunnel junction pattern in the first storage area and the substrate array pattern in the second storage area. The initial capacitor pattern is a closed figure and there are no holes inside the closed figure, and it covers the substrate array pattern and the magnetic tunnel junction pattern.

[0106] After forming the initial capacitor pattern, a second pattern is formed in the initial capacitor pattern located in the second storage area, and the initial capacitor pattern with the second pattern forms a capacitor pattern. Refer to Figure 3 , the initial capacitor pattern located in the second storage area 12 is processed to form a capacitor pattern 116. The number of capacitor patterns 116 located in the second storage area 12 is multiple, and the multiple capacitor patterns 116 are arranged at intervals. The multiple capacitor patterns 116 are arranged in a hexagonal close-packed manner, and each capacitor pattern 116 has a partial overlapping area with a plug pattern 115 in the substrate array pattern located in the second storage area 12.

[0107] After forming the capacitor pattern, the initial capacitor pattern located in the first storage area is removed. The remaining initial capacitor pattern is removed, and the capacitor pattern 116 is retained. No other patterns are covered on the magnetic tunnel junction pattern 121 in the first storage area 11.

[0108] In summary, the layout in the embodiments of the present application has a first storage area 11 and a second storage area 12 that at least partially surrounds the first storage area 11. The method for processing the layout includes: forming a substrate array pattern with a plurality of plug patterns 115 arranged at intervals in a blank layout, and forming a storage pattern. The storage pattern includes a magnetic tunnel junction pattern 121 located in the first storage area 11 and a capacitor pattern 116 located in the second storage area 12. The magnetic tunnel junction pattern 121 and the plug pattern 115 located in the first storage area 11 have a partial overlapping area, and the capacitor pattern 116 and the plug pattern 115 located in the second storage area 12 have a partial overlapping area. The magnetic tunnel junction pattern 121 and the substrate array pattern located in the first storage area 11 can be used to form a pattern of a magnetic random access memory, and the capacitor pattern 116 and the substrate array pattern located in the second storage area 12 can be used to form a pattern of a dynamic random access memory, so that the formed layout includes a pattern of a dynamic random access memory and a pattern of a magnetic random access memory. When using this layout for production subsequently, the preparation process of the dynamic random access memory can be used to prepare the magnetic random access memory, so that the storage density of the magnetic random access memory is increased, thereby further increasing the integration degree of the magnetic random access memory and improving the integration degree of the semiconductor device.

[0109] In a possible example of the present application, after forming the storage pattern (step S200), it further includes:

[0110] Step S300: Form an initial conductive pattern that covers the magnetic tunnel junction pattern in the first storage area and the capacitor pattern in the second storage area. The initial conductive pattern is a closed figure and there are no holes inside the closed figure, and it covers the magnetic tunnel junction pattern and the capacitor pattern.

[0111] Step S400: Remove the initial conductive pattern located in the first storage area, and the remaining initial conductive pattern forms a conductive pattern. Remove the initial conductive pattern located in the first storage area and retain the initial conductive pattern located in the second storage area. Refer to Figure 16 and the remaining initial conductive pattern forms a conductive pattern 117 that covers the capacitor pattern 116, and there is no other pattern covering the magnetic tunnel junction pattern 121 in the first storage area 11.

[0112] Step S500: Form an initial second electrode contact pattern that covers the magnetic tunnel junction pattern in the first storage area and the conductive pattern in the second storage area. The initial second electrode contact pattern is a closed figure and there are no holes inside the closed figure, and it covers the magnetic tunnel junction pattern and the conductive pattern.

[0113] Step S600: Form a third pattern in the initial second electrode contact pattern located in the first storage area. The initial second electrode contact pattern with the third pattern forms the second electrode contact pattern. Refer to Figure 17 , the initial second electrode contact pattern located in the first storage area 11 is processed to form the second electrode contact pattern 122. The number of the second electrode contact patterns 122 is multiple, and the multiple second electrode contact patterns 122 are arranged at intervals. Each second electrode contact pattern 122 at least partially overlaps with a magnetic tunnel junction pattern 121. Exemplarily, the multiple second electrode contact patterns 122 may be arranged in a rectangular array.

[0114] Step S700: Remove the initial second electrode contact pattern located in the second storage area. Remove the remaining initial second electrode contact patterns, and retain the second electrode contact pattern. No other pattern covers the conductive pattern in the second storage area.

[0115] In a possible example, as Figure 17 and Figure 18 shown, the second electrode contact patterns 122 are arranged in a rectangular array. After removing the initial second electrode contact patterns 122 located in the second storage area 12, it further includes: forming a plurality of second data line patterns 123 arranged at intervals and extending along the second direction. Each second data line pattern 123 has a partial overlapping area with the second electrode contact pattern 122 and is aligned with the second electrode contact patterns 122 in the same column.

[0116] The embodiment of the present application further provides a storage medium, in which computer-executable instructions are stored. When the processor executes the computer-executable instructions, the processing method of any layout in the foregoing embodiments of the present application is implemented. The storage medium may be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk, or an optical disc, etc., which can store computer-executable instructions. The storage medium in the embodiment of the present application is used to implement the above-mentioned processing method of the layout, and thus has at least the advantages of the above-mentioned processing method of the layout. For specific effects, refer to the above, and details are not described herein again.

[0117] The embodiment of the present application further provides a program product, including a computer program, which implements the processing method of any layout in the foregoing embodiments of the present application when executed by a processor. The program product in the embodiment of the present application implements the above-mentioned processing method of the layout, and thus has at least the advantages of the above-mentioned processing method of the layout. For specific effects, refer to the above, and details are not described herein again.

[0118] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product of the present application includes one or more computer instructions. When the computer program instructions of the present application are loaded and executed on a computer, the processes or functions of the present application according to the embodiments of the present application are generated in whole or in part. The computer of the present application can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions of the present application can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions of the present application can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium of the present application can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more integrated available media. The available media of the present application can be magnetic media (such as floppy disks, hard disks, magnetic tapes), optical media (such as DVDs), or semiconductor media (such as solid state disk (SSD)), etc.

[0119] The embodiments or implementation manners in this specification are described in a progressive manner. The focus of each embodiment is on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0120] In the description of this specification, the descriptions with reference to terms such as "an implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A layout, characterized in that, The layout has a first storage area and a second storage area that at least partially surrounds the first storage area; the layout includes: A substrate array pattern that includes a plurality of plug patterns arranged at intervals; A storage pattern that includes a magnetic tunnel junction pattern in the first storage area and a capacitor pattern in the second storage area. The magnetic tunnel junction pattern and the plug pattern in the first storage area have a partial overlap area, and the capacitor pattern and the plug pattern in the second storage area have a partial overlap area; A conductive pattern that is located in the second storage area and covers the capacitor pattern.

2. The layout according to claim 1, wherein, The substrate array pattern includes: A substrate pattern that includes a plurality of active region sub-patterns arranged at intervals and extending along a first direction; A plurality of first data line patterns arranged at intervals and extending along a second direction, where the second direction intersects the first direction. Each first data line pattern has a partial overlap area with the active region sub-patterns in the same column; A plurality of the plug patterns are located between two adjacent first data line patterns and have a partial overlap area with the active region sub-patterns.

3. The layout according to claim 2, wherein The first data line pattern includes a plurality of conductive column sub-patterns arranged at intervals and a plurality of wire sub-patterns extending along the first direction; Each conductive column sub-pattern has a partial overlap area with one active region sub-pattern, and each wire sub-pattern passes through the conductive column sub-patterns in the same column; The part of the wire sub-pattern in the first storage area forms a source line pattern, and the part of the wire sub-pattern in the second storage area forms a bit line pattern.

4. The layout according to claim 3, wherein A plurality of word line patterns arranged at intervals and extending along a third direction are further configured in the substrate pattern. The third direction intersects the first direction and the third direction intersects the second direction; The word line pattern intersects and passes through the active region sub-patterns in the same row.

5. The layout according to claim 4, wherein In the same word line pattern, a second insulating pattern is further configured between the part in the first storage area and the part in the second storage area.

6. The layout according to claim 4, wherein There are two word line patterns that intersect the active region sub-patterns in the same row, and these two word line patterns separate the active region sub-patterns they intersect into a first contact area in the middle and second contact areas on both sides of the first contact area; The conductive column sub-pattern overlaps with a partial area of the first contact area, and the plug pattern overlaps with a partial area of the second contact area.

7. The layout according to claim 2, wherein The plug pattern includes a first plug sub-pattern and a second plug sub-pattern corresponding to the first plug sub-pattern; The first plug sub-pattern is located between adjacent first data line patterns, and the second plug sub-pattern has a partial overlap area with both the first data line pattern and the first plug sub-pattern; The second plug pattern located in the first storage region forms a first electrode contact pattern, and the second plug pattern located in the second storage region forms a capacitive contact pad pattern.

8. The layout according to claim 7, wherein Each of the capacitive patterns has a partial overlap region with one of the capacitive contact pad patterns, and the plurality of capacitive patterns are arranged in a hexagonal close-packed arrangement.

9. The layout according to claim 8, characterized in that, The layout further includes a conductive pattern located in the second storage region, and the conductive pattern covers the capacitive pattern.

10. The layout according to claim 8, wherein The layout further includes a plurality of second electrode contact patterns, and each of the second electrode contact patterns at least partially overlaps with one of the magnetic tunnel junction patterns.

11. The layout according to claim 10, wherein The magnetic tunnel junction patterns are arranged in a hexagonal close-packed arrangement, and the second electrode contact patterns are arranged in a rectangular array.

12. The layout according to claim 10, wherein The layout further includes a plurality of second data line patterns, the plurality of second data line patterns are spaced apart and extend along the second direction, each of the second data line patterns has a partial overlap region with the second electrode contact pattern, and passes through the second electrode contact patterns located in the same column.

13. A method for processing a layout, characterized in that, The layout has a first storage region and a second storage region at least partially surrounding the first storage region; The processing method includes: Forming a substrate array pattern in a blank layout, the substrate array pattern including a plurality of spaced plug patterns; Forming a storage pattern, the storage pattern including a magnetic tunnel junction pattern located in the first storage region and a capacitive pattern located in the second storage region, the magnetic tunnel junction pattern having a partial overlap region with the plug pattern located in the first storage region, and the capacitive pattern having a partial overlap region with the plug pattern located in the second storage region; Forming an initial conductive pattern, the initial conductive pattern covering the magnetic tunnel junction pattern in the first storage region and the capacitive pattern in the second storage region; Removing the initial conductive pattern located in the first storage region, and the remaining initial conductive pattern forms a conductive pattern.

14. The processing method according to claim 13, characterized in that, The forming a substrate array pattern in a blank layout, the substrate array pattern including a plurality of spaced plug patterns, includes: Forming a substrate pattern in the blank layout, the substrate pattern including a plurality of spaced active region sub-patterns, the active region sub-patterns extending along a first direction; Forming a plurality of first data line patterns spaced apart and extending along a second direction, the second direction intersecting the first direction; each of the first data line patterns having a partial overlap region with the active region sub-patterns located in the same column; Forming a plurality of plug patterns located between two adjacent ones of the first data line patterns, the plurality of plug patterns having a partial overlap region with the active region sub-patterns.

15. The processing method according to claim 13, wherein, The forming the storage pattern includes: Forming an initial magnetic tunnel junction pattern, the initial magnetic tunnel junction pattern covering the substrate array pattern; Forming a first pattern in the initial magnetic tunnel junction pattern located in the first storage region, and the initial magnetic tunnel junction pattern having the first pattern forms the magnetic tunnel junction pattern; Removing the initial magnetic tunnel junction pattern located in the second storage region; Form an initial capacitance pattern that covers the magnetic tunnel junction pattern of the first storage area and the substrate array pattern of the second storage area; Form a second pattern in the initial capacitance pattern located in the second storage area, and the initial capacitance pattern with the second pattern forms the capacitance pattern; Remove the initial capacitance pattern located in the first storage area.

16. The processing method according to claim 13, characterized in that After removing the initial conductive pattern located in the first storage area and the remaining initial conductive pattern forms the conductive pattern, it further includes: Form an initial second electrode contact pattern that covers the magnetic tunnel junction pattern of the first storage area and the conductive pattern of the second storage area; Form a third pattern in the initial second electrode contact pattern located in the first storage area, and the initial second electrode contact pattern with the third pattern forms the second electrode contact pattern; Remove the initial second electrode contact pattern located in the second storage area.

17. The processing method according to claim 16, characterized in that The second electrode contact patterns are arranged in a rectangular array; After removing the initial second electrode contact pattern located in the second storage area, it further includes: Form a plurality of second data line patterns that are spaced apart and extend in the second direction. Each second data line pattern has a partial overlapping area with the second electrode contact pattern and passes through the second electrode contact patterns in the same column.

18. A storage medium, characterized in that, The storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the processing method described in any one of claims 13-17 is implemented.

19. A program product, characterized in that, It includes a computer program that, when executed by a processor, implements the processing method described in any one of claims 13-17.

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