A semiconductor device

Abstract

The application provides a semiconductor device, comprising a U-shaped boost diode, the U-shaped boost diode comprising a first isolation structure arranged below a first field oxide region, a source terminal and a base terminal, and a second isolation structure arranged below a second field oxide region, the first isolation structure and the second isolation structure are arranged in the same layer and are spaced apart, and a part of the first isolation structure along a thickness direction and a part of the second isolation structure along the thickness direction are located in a substrate, and the remaining part of the first isolation structure along the thickness direction and the remaining part of the second isolation structure along the thickness direction are located in an epitaxial layer. The second isolation structure in the application can disperse the electric field across the high potential, so as to prevent the electric field from concentrating, so that the electric field does not concentrate at the source terminal at the bottom of the U-shaped boost diode, and the breakdown voltage BV of the boost diode in the semiconductor device is increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor integrated circuit technology, chips are typically divided into multiple different voltage regions to integrate devices with different power supply voltage requirements. Related technologies integrate chips with different voltage regions, including low-voltage and high-voltage regions, which are isolated by an isolation ring structure. Generally, the power supply voltage required by devices in the high-voltage region is higher than that of devices in the low-voltage region. Therefore, to enable information exchange between devices in the low-voltage and high-voltage regions, a voltage converter is needed to connect them for voltage conversion. For example... Figure 1 As shown, current high-voltage ring structures integrating LDMOS (laterally diffused metal-oxide-semiconductor) transistors include a U-shaped boost diode 1 to increase current. In this structure, the source current BV (breakdown voltage) of the U-shaped boost diode 1 is reduced because the drain electric field of the U-shaped boost diode 1 is too concentrated towards the source. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device that can increase the source current BV of a U-type boost diode.

[0004] To address the aforementioned problems, this invention provides a semiconductor device, which is a high-voltage ring structure integrating an LDMOS transistor. The semiconductor device includes a U-shaped boost diode, which includes a substrate and an epitaxial layer located on the substrate. The U-shaped boost diode has a base terminal, a source terminal, a gate contact terminal, and a drain terminal arranged sequentially. The base terminal and the source terminal are located in the epitaxial layer, and a portion of the gate contact terminal and the drain terminal are located on the epitaxial layer. A first field oxide region is provided between the base terminal and the source terminal, and a portion of the gate contact terminal and a portion of the drain terminal are located on a second field oxide region.

[0005] A first isolation structure is disposed below the first field oxygen region, the source terminal, and the base terminal, and a second isolation structure is disposed below the second field oxygen region. The first isolation structure and the second isolation structure are disposed in the same layer and are spaced apart. The portion of the first isolation structure along the thickness direction and the portion of the second isolation structure along the thickness direction are both located in the substrate, and the remaining portion of the first isolation structure along the thickness direction and the remaining portion of the second isolation structure along the thickness direction are both located in the epitaxial layer.

[0006] Optionally, the first isolation structure includes a first buried layer and a first doped region, the first doped region being located above the first buried layer and within the epitaxial region, a portion of the first buried layer along the thickness direction being located within the epitaxial region, and the remaining portion along the thickness direction being located within the substrate.

[0007] Furthermore, the first buried layer is a P-type buried layer, and the first doped region is a P-type doped region.

[0008] Furthermore, the second isolation structure is located in the bottom region of the U-shaped boost diode.

[0009] Furthermore, the second isolation structure is arch-shaped.

[0010] Furthermore, the second isolation structure includes a second buried layer and a second doped region, the second doped region being located above the second buried layer, and the second buried layer and the second doped region being disposed in contact.

[0011] Furthermore, the second buried layer is a P-type buried layer, and the second doped region is a P-type doped region.

[0012] Furthermore, the second doped region is disposed in the same layer as the first doped region, and the second buried layer and the first buried layer are disposed in the same layer.

[0013] Furthermore, the second doped region and the first doped region have the same depth and the same thickness, the second buried layer and the first buried layer have the same depth and the same thickness.

[0014] Furthermore, a portion of the second buried layer along the thickness direction is located in the epitaxial region, while the remaining portion along the thickness direction is located in the substrate.

[0015] Optionally, the substrate is a P-type substrate, and the epitaxial region is an N-type epitaxial region.

[0016] Optionally, a P-well is formed in the epitaxial region, the first isolation structure is located below the P-well, and the P-well is formed with a first N+ region and a P+ region spaced apart, the first N+ region being the source terminal and the P+ region being the base terminal.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] This invention provides a semiconductor device including a U-shaped boost diode. The U-shaped boost diode includes a substrate and an epitaxial layer located on the substrate. The U-shaped boost diode has a base terminal, a source terminal, a gate contact terminal, and a drain terminal arranged sequentially. The base terminal and the source terminal are located in the epitaxial layer. A portion of the gate contact terminal and the drain terminal are located on the epitaxial layer. A first field oxide region is disposed between the base terminal and the source terminal. A portion of the gate contact terminal and a portion of the drain terminal are located on a second field oxide region. A first isolation structure is disposed below the first field oxide region, the source terminal, and the base terminal. A second isolation structure is disposed below the second field oxide region. The first isolation structure and the second isolation structure are on the same layer and spaced apart. A portion of the first isolation structure along the thickness direction and a portion of the second isolation structure along the thickness direction are both located in the substrate. The remaining portions of the first isolation structure along the thickness direction and the remaining portions of the second isolation structure along the thickness direction are both located in the epitaxial layer. The second isolation structure in this invention allows the high potential across the circuit to disperse the electric field, preventing electric field concentration. This prevents the electric field from concentrating at the source terminal at the bottom of the U-shaped boost diode, thereby increasing the breakdown voltage BV of the boost diode in the semiconductor device. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a longitudinal section of a high-pressure ring structure;

[0020] Figure 2 A top view of a semiconductor device provided according to an embodiment of the present invention;

[0021] Figure 3 for Figure 2 Schematic diagram of the longitudinal section at point AA.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1. 100 - U-type boost diode; 01 - P+ region; 02 - First N+ region; 03 - First field oxide region; 04 - First polysilicon gate; 05 - Second field oxide region; 06 - Second polysilicon gate; 07 - Second N+ region; 111 - First P-type buried layer; 112 - First P-type doped region; 120 - Second isolation structure; 121 - Second P-type buried layer; 122 - Second P-type doped region. Detailed Implementation

[0024] The following is a further detailed description of a semiconductor device according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0025] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0026] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0027] It should be noted that, in practice, the xx department... Figure 3 It cannot be seen in the top view, but its location is shown as a dashed line in order to illustrate its position.

[0028] Figure 2 This is a top view of a semiconductor device provided in this embodiment. Figure 2 As shown, this embodiment provides a semiconductor device, such as a high-voltage ring structure integrating an LDMOS transistor. The semiconductor device includes at least a U-shaped boost diode 100.

[0029] Figure 3 for Figure 2 A schematic diagram of the longitudinal section at point AA. Figure 3As shown, the U-type boost diode 100 includes a P-type substrate (i.e., Psub), an N-type epitaxial region (N-epi) located on the P-type substrate, a P-well located in the N-type epitaxial region, a first isolation structure located under the P-well, two spaced N-wells (NW) located in the P-well, each N-well having a first N+ region 02, a first field oxide region 03 located between the two first N+ regions 02 and on the surface of the N-type epitaxial region, a P+ region 01 located between the two first N+ regions 02 and in the P-well, a second field oxide region 05 located on the surface of the N-type epitaxial region outside the P-well, a first polysilicon gate 04 located in the second field oxide region 05 near the P-well, a second polysilicon gate 06 located on the second field oxide region 05 and spaced apart from the first polysilicon gate 04, and a second N+ region 07 located in the N-type epitaxial region away from the P-well of the second field oxide region 05.

[0030] Wherein, a portion of the first polysilicon gate 04 along the length direction is located on the surface of the N-type epitaxial region between the first field oxide region 03 and the second field oxide region 05, at the junction of the N-type epitaxial region and the P-well outside the first N+ region 02; the remaining portion along the length direction is located on the surface of the second field oxide region 05 near the side of the first field oxide region 03.

[0031] The first isolation structure includes a first P-type buried layer 111 and a first P-type doped region 112. The first P-type doped region 112 is located between the first P-type buried layer 111 and the P-well. The first P-type doped region 112 is located in the N-type epitaxial region. A portion of the first P-type buried layer 111 along the thickness direction is located in the N-type epitaxial region, and the remaining portion along the thickness direction is located in the P-type substrate, so that the first isolation structure is grounded.

[0032] The semiconductor device further includes a second isolation structure 120, which is spaced out from the first isolation structure. The second isolation structure 120 is located in the N-type epitaxial region and P-type substrate below the second field oxide region O5, so that the second isolation structure 120 is grounded. The second isolation structure 120 is arch-shaped, i.e., generally U-shaped, in the U-shaped boost diode 100. The second isolation structure 120 is located in the bottom region of the U-shaped boost diode 100. The larger the opening of the second isolation structure 120, the better to disperse the electric field in the U-shaped boost diode 100. The second isolation structure 120 is grounded so that the high potential across it can disperse the electric field and prevent electric field concentration. This prevents the electric field from concentrating at the source terminal at the bottom of the U-shaped boost diode 100, thereby increasing the breakdown voltage BV of the boost diode in the semiconductor device.

[0033] The second isolation structure 120 includes a second P-type buried layer 121 and a second P-type doped region 122. The second P-type doped region 122 is located above the second P-type buried layer 121, and the second P-type buried layer 121 and the second P-type doped region 122 are in contact. The second P-type doped region 122 is disposed in the same layer as the first P-type doped region 112, that is, the second P-type doped region 122 and the first P-type doped region 112 have the same depth and the same thickness. A portion of the second P-type buried layer 121 along the thickness direction is located in the N-type epitaxial region, and the remaining portion along the thickness direction is located in the P-type substrate. The second P-type buried layer 121 and the first P-type buried layer 111 are disposed in the same layer, that is, the second P-type buried layer 121 and the first P-type buried layer 111 have the same depth and the same thickness.

[0034] The N-type epitaxial region below the second field oxygen region 05 forms a diffusion region. The P+ region 01 is the base terminal, the first N+ region 02 is the source terminal, the first polysilicon gate 04 is the gate contact, and the second polysilicon gate 06 and the second N+ region 07 together serve as the drain terminal.

[0035] In summary, the present invention provides a semiconductor device including a U-shaped boost diode. The U-shaped boost diode includes a substrate and an epitaxial layer located on the substrate. The U-shaped boost diode has a base terminal, a source terminal, a gate contact terminal, and a drain terminal arranged sequentially. The base terminal and the source terminal are located in the epitaxial layer. A portion of the gate contact terminal and the drain terminal are located on the epitaxial layer. A first field oxide region is disposed between the base terminal and the source terminal. A portion of the gate contact terminal and the portion of the drain terminal are located on a second field oxide region. A first isolation structure is disposed below the first field oxide region, the source terminal, and the base terminal. A second isolation structure is disposed below the second field oxide region. The first isolation structure and the second isolation structure are on the same layer and spaced apart. A portion of the first isolation structure along the thickness direction and a portion of the second isolation structure along the thickness direction are both located in the substrate. The remaining portions of the first isolation structure along the thickness direction and the remaining portions of the second isolation structure along the thickness direction are both located in the epitaxial layer. The second isolation structure in this invention allows the high potential across the circuit to disperse the electric field, preventing electric field concentration. This prevents the electric field from concentrating at the source terminal at the bottom of the U-shaped boost diode, thereby increasing the breakdown voltage BV of the boost diode in the semiconductor device.

[0036] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0037] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A semiconductor device, wherein the semiconductor device is a high-voltage ring structure integrating an LDMOS transistor, characterized in that, The semiconductor device includes a U-shaped boost diode, which includes a substrate and an epitaxial layer on the substrate. The U-shaped boost diode has a base terminal, a source terminal, a gate contact terminal, and a drain terminal arranged sequentially. The base terminal and the source terminal are located in the epitaxial layer, and a portion of the gate contact terminal and the drain terminal are located on the epitaxial layer. A first field oxide region is provided between the base terminal and the source terminal, and a portion of the gate contact terminal and a portion of the drain terminal are located on a second field oxide region. A first isolation structure is provided below the first field oxygen region, the source terminal, and the base terminal. A second isolation structure is provided in the N-type epitaxial region and the substrate below the second field oxygen region. The second isolation structure is grounded. The first isolation structure and the second isolation structure are in the same layer and are spaced apart. The portion of the first isolation structure along the thickness direction and the portion of the second isolation structure along the thickness direction are both located in the substrate. The remaining portion of the first isolation structure along the thickness direction and the remaining portion of the second isolation structure along the thickness direction are both located in the epitaxial layer. The second isolation structure is located in the bottom region of the U-shaped boost diode, and the second isolation structure is arch-shaped. The second isolation structure includes a second buried layer and a second doped region. The second doped region is located above the second buried layer and the second buried layer and the second doped region are in contact. The second doped region is located in the epitaxial layer. A portion of the second buried layer along the thickness direction is located in the epitaxial layer, and the remaining portion along the thickness direction is located in the substrate. The second buried layer is a P-type buried layer, the second doped region is a P-type doped region, the substrate is a P-type substrate, and the epitaxial layer is an N-type epitaxial layer. The second isolation structure is grounded.

2. The semiconductor device as claimed in claim 1, characterized in that, The first isolation structure includes a first buried layer and a first doped region, the first doped region being located above the first buried layer and within the epitaxial region, a portion of the first buried layer along the thickness direction being located within the epitaxial region, and the remaining portion along the thickness direction being located within the substrate.

3. The semiconductor device as described in claim 2, characterized in that, The first buried layer is a P-type buried layer, and the first doped region is a P-type doped region.

4. The semiconductor device as described in claim 2, characterized in that, The second doped region has the same depth as the first doped region, the second doped region has the same thickness as the first doped region, the second buried layer has the same depth as the first buried layer, and the second buried layer has the same thickness as the first buried layer.

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