Time reference processing method and device

Abstract

The present invention discloses a time reference processing method, comprising: generating an oscillation signal through a constant temperature crystal oscillator; multiplying the oscillation signal to obtain a first frequency signal, and receiving a second frequency signal from an antenna; constructing a free counter using the first frequency signal to obtain a free count value; obtaining a time error between adjacent pulses of the second frequency signal based on the first frequency signal and the second frequency signal; calculating a time compensation value based on the time error; and accumulating the free count value and the time compensation value to obtain real-time time. The present invention constructs a free counter using the first frequency signal to obtain a free count value, i.e., local time, and calculates a time compensation value based on the time error. The free count value and the time compensation value are then accumulated to achieve full digital time compensation to correct the local time.

Description

Technical Field

[0001] The present invention relates to the technical field of time systems, and in particular to a time reference processing method and device. Background Art

[0002] High-precision time reference units play a crucial role in time-sensitive systems such as power distribution, autonomous driving, and earthquake detection, and are closely linked to frequency sources such as atomic clocks and oven-controlled crystal oscillators. However, the high cost, demanding deployment environments, and bulky size of atomic clocks, with their ultra-high frequency stability, limit their application areas. They are generally deployed only in satellite timing systems and national timing laboratory centers, serving as references for low-level frequency standards. In contrast, oven-controlled crystal oscillators, with their excellent short-term accuracy, low cost, ease of use, and portability, are more suitable for civilian applications such as power grids and autonomous driving. However, due to the aging and temperature characteristics of crystal oscillators, their initial output clock frequency deviates with operating time and ambient temperature fluctuations, resulting in cumulative time errors in the constructed local time reference. Therefore, using the long-term stable satellite timing system time source to calibrate the short-term stable oven-controlled crystal oscillator is a viable approach to establishing a high-precision time reference unit.

[0003] There are two existing time base solutions: voltage-controlled oven-controlled crystal oscillator (VCO) training and direct frequency synthesis (DFS). The VCO training solution uses an antenna and receiver to analyze satellite signals and output a pulse-per-second signal. Simultaneously, a phase-locked loop (PLL) chip multiplies the 10MHz clock output of the OCO to 100MHz, and a field-programmable logic array (FPGA) chip generates another pulse signal. A time-to-digital converter (TDC) then measures the time error between the two pulse signals. Processing by a processor chip generates a voltage control word, which is then input into a digital-to-analog converter (DAC) to adjust the crystal oscillator frequency. This corrected 100MHz clock signal is used to establish a local time base within the FPGA. The DFS solution uses a frequency synthesis chip and uses a frequency tuning word calibration method instead of directly adjusting the crystal oscillator voltage.

[0004] However, the voltage control characteristics of the digital-to-analog converter chip and the frequency tuning characteristics of the frequency synthesis chip are not strictly linear, which will introduce additional errors into the calibration of the time reference.

[0005] Therefore, the existing technology still needs to be improved and developed. Summary of the Invention

[0006] In view of the above-mentioned deficiencies in the prior art, an object of the present invention is to provide a time reference processing method and device to solve the problem in the prior art that additional errors exist when calibrating the time reference due to non-linear frequency modulation.

[0007] The technical solutions of the present invention are as follows:

[0008] A time reference processing method, comprising:

[0009] Generate an oscillation signal through a constant temperature crystal oscillator;

[0010] multiplying the oscillation signal to obtain a first frequency signal, and receiving a second frequency signal from an antenna;

[0011] constructing a free counter by using the first frequency signal to obtain a free count value;

[0012] Acquire a time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal;

[0013] Calculating a time compensation value according to the time error;

[0014] The free count value and the time compensation value are accumulated to obtain the real time.

[0015] According to a further configuration of the present invention, the step of constructing a free counter by using the first frequency signal and obtaining a free count value comprises:

[0016] A second-level free counter and a nanosecond-level free counter are constructed using the first frequency signal, and the second-level free counter and the nanosecond-level free counter are output.

[0017] In a further arrangement of the present invention, the step of obtaining a time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal includes:

[0018] Using the second frequency signal as a reference signal, latching the current rough measurement time point of the free counter;

[0019] A delay chain based on a carry chain is used to obtain a detailed measurement time period;

[0020] The time error between adjacent pulses of the second frequency signal is obtained according to the coarse measurement time point and the fine measurement time period.

[0021] According to a further configuration of the present invention, the step of obtaining the detailed measurement time period by using the delay chain includes:

[0022] inputting the second frequency signal into the delay chain;

[0023] sampling the second frequency signal in the delay chain and outputting a sampling signal to a counting encoder;

[0024] The counting encoder encodes the sampling signal and uses the encoding result as the fine measurement time period.

[0025] According to a further configuration of the present invention, the step of calculating the time compensation value according to the time error includes:

[0026] Taking the time error as initial data;

[0027] The initial data is processed by a Kalman filter algorithm to obtain a second-level phase compensation value, a nanosecond-level phase compensation value, and a nanosecond-level frequency offset compensation value.

[0028] According to a further configuration of the present invention, the step of accumulating the free count value, the phase compensation value, and the frequency offset compensation value to obtain the real time includes:

[0029] Converting the total nanosecond frequency offset compensation value into the nanosecond frequency offset compensation value of a single clock cycle;

[0030] Accumulate the nanosecond free count value, the nanosecond phase compensation value, and the nanosecond frequency offset compensation value of a single clock cycle, and output nanosecond real-time time and second-level carry;

[0031] The second-level carry, the second-level free count value, and the second-level phase compensation value are accumulated to output the second-level real-time time.

[0032] A time reference device used in the high-precision time method as described above, comprising: an oven-controlled crystal oscillator, a receiver, a field programmable gate array, and a processor chip;

[0033] The constant temperature crystal oscillator is connected to the field programmable gate array, and is used to generate an oscillation signal and output it to the field programmable gate array;

[0034] The receiver is connected to the antenna and the field programmable gate array respectively, and is used to receive the second frequency signal from the antenna;

[0035] The field programmable gate array includes a time measurement module, a phase-locked loop module and a time synthesis module;

[0036] The phase-locked loop module is connected to the constant temperature crystal oscillator and the time measurement module respectively, and is used to multiply the frequency of the oscillation signal and output a first frequency signal to the time measurement module;

[0037] The time measurement module is connected to the receiver and the phase-locked loop module respectively, and is used to construct a free counter according to the first frequency signal to obtain a free count value, and to obtain a time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal.

[0038] The processor chips are respectively connected to the time measurement modules, and are used to calculate the time compensation value according to the time error;

[0039] The time synthesis module is connected to the time measurement module and the processor chip respectively, and is used to accumulate the free count value and the time compensation value to obtain real time.

[0040] According to a further configuration of the present invention, the time measurement module includes: a coarse measurement module and a fine measurement module;

[0041] The coarse measurement module is connected to the receiver and the phase-locked loop module respectively, and is used to construct a free counter according to the first frequency signal, obtain a free count value, and latch the current coarse measurement time point of the free counter using the second frequency signal as a reference signal;

[0042] The fine measurement module is connected to the receiver, the phase-locked loop module and the processor chip respectively, and is used to sample the second frequency signal, output a sampling signal according to the first frequency signal, and encode the sampling signal, and output the encoding result as a fine measurement time period to the processor chip.

[0043] A further arrangement of the present invention further comprises: a time compensator;

[0044] The time compensator is connected to the processor chip and the time synthesis module respectively, and is used to convert the total time compensation value into the time compensation value of a single clock cycle.

[0045] According to a further configuration of the present invention, the coarse detection module includes a D flip-flop synchronizer, a free counter and a latch;

[0046] The D-type flip-flop synchronizer is connected to the receiver, the phase-locked loop module and the latch respectively, and is used to stabilize the clock edge of the second frequency signal and use the stabilized signal as the latch signal of the latch;

[0047] The free counter is connected to the phase-locked loop module and the latch respectively, and is used to count according to the first frequency signal and output the counting result to the latch;

[0048] The latch is connected to the D flip-flop synchronizer and the free counter respectively, and is used to latch the counting result according to the latch signal.

[0049] The present invention provides a time base processing method, comprising: generating an oscillation signal through a constant temperature crystal oscillator; multiplying the oscillation signal to obtain a first frequency signal, and receiving a second frequency signal from an antenna; constructing a free counter through the first frequency signal to obtain a free count value; obtaining the time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal; calculating a time compensation value according to the time error; and accumulating the free count value and the time compensation value to obtain real-time time. The present invention constructs a free counter through the first frequency signal to obtain a free count value, i.e., local time. Calculating a time compensation value according to the time error, and then accumulating the free count value and the time compensation value to achieve full digital (linear) time compensation to correct the local time, i.e., obtain the current real-time time, without the need for analog-to-digital conversion such as frequency and voltage, so as to avoid the problem of additional errors when calibrating the time base, thereby further improving time accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0051] Figure 1 It is a flow chart of the time reference processing method in the present invention.

[0052] Figure 2 It is a timing diagram of the time measurement module in the time reference processing method of the present invention.

[0053] Figure 3 This is an experimental data diagram of the time reference processing method in the present invention.

[0054] Figure 4 It is a structural diagram of the time reference processing device in the present invention.

[0055] Figure 5 It is a circuit diagram of the time measurement module in the time reference processing device of the present invention.

[0056] Figure 6 It is a circuit diagram of a delay unit of a delay chain in a time reference processing device in the present invention.

[0057] Figure 7 It is a circuit diagram of the time compensator in the time reference processing device of the present invention. DETAILED DESCRIPTION

[0058] The present invention provides a time reference processing method and apparatus. To clarify the objectives, technical solutions, and effects of the present invention, the present invention is further described below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0059] In the embodiments and patent claims, unless otherwise specified herein, the words "a," "an," "the," and "the" may include plural forms. If the embodiments of the present invention include descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features.

[0060] It should be further understood that the term "comprising" as used in the description of the present invention refers to the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intermediate elements. In addition, "connected" or "coupled" as used herein can include wireless connections or wireless couplings. The term "and / or" as used herein includes all or any units and all combinations of one or more associated listed items.

[0061] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0062] In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0063] Please also see Figures 1 to 3 , the present invention provides a preferred embodiment of a time reference processing method.

[0064] like Figure 1 As shown, the present invention provides a time reference processing method comprising:

[0065] S100, generating an oscillation signal through a constant temperature crystal oscillator.

[0066] The oscillator unit of the oven controlled crystal oscillator 100 placed in a low temperature environment generates an oscillation signal.

[0067] S200 , multiplying the frequency of the oscillation signal to obtain a first frequency signal CLK, and receiving a second frequency signal GNSS from an antenna.

[0068] Specifically, the oscillation signal is input to the phase-locked loop module 320, which multiplies the oscillation signal and outputs a first frequency signal CLK. The phase-locked loop module 320 is a closed-loop control circuit. When operating normally, the output frequency locks the input frequency. When the output signal is divided by N through the frequency divider and then fed back to the input, the output is the N-multiplied frequency. For example, if the frequency of the oscillation signal is 10 MHz and is multiplied by 10 through the phase-locked loop module 320, the output first frequency signal CLK is 100 MHz. By multiplying the oscillation signal to obtain the first frequency signal CLK, the accuracy of subsequent time measurement is improved.

[0069] Since the satellite has a high-stability crystal oscillator with long-term stability, which has outstanding advantages such as low phase noise, high frequency temperature stability, and high frequency accuracy, the antenna and receiver 200 analyze the satellite signal output pulse per second signal as the second frequency signal GNSS to improve stability.

[0070] S300: Construct a free counter using the first frequency signal CLK to obtain a free count value.

[0071] Specifically, please refer to Figure 5 , a free counter 3112 is constructed with the first frequency signal CLK as a clock signal to count, and the counting result of the free counter is used as the free counting value, that is, the current local time.

[0072] In one embodiment, step S300 includes:

[0073] S310: Construct a second-level free counter and a nanosecond-level free counter using the first frequency signal, and output a second-level free count value and a nanosecond-level free count value;

[0074] Specifically, if Figure 5As shown, the free-running counter 3112 is composed of several counting flip-flops. The first frequency signal CLK serves as the clock signal for the counter flip-flops in the nanosecond free-running counter, which count the number of pulses of the first frequency signal CLK. In the nanosecond free-running counter, the nanosecond free-running counter increments by 32'd10 per clock cycle and is reset to zero when the count reaches 32'd999999990, and the count is carried forward to the second free-running counter. In other words, the carry signal output by the nanosecond counter serves as the clock signal for the second free-running counter. When the count reaches 32'd999999990, the data in the nanosecond free-running counter is reset to zero, and the second free-running counter begins counting the number of pulses of the nanosecond counter carry signal. This generates the nanosecond free-running count value and the second free-running count value. Using the first frequency signal CLK to construct the second free-running counter and the nanosecond free-running counter further improves the accuracy of local time and subsequent time measurements.

[0075] S400 : Obtain a time error between adjacent pulses of the second frequency signal GNSS according to the first frequency signal CLK and the second frequency signal GNSS.

[0076] In one embodiment, step S400 includes:

[0077] S410 : Using the second frequency signal GNSS as a reference signal, latching a current coarse measurement time point of the free counter.

[0078] Specifically, using the second GNSS frequency signal as a reference signal, upon the rising edge of the second GNSS frequency signal, the current count value of the free counter is latched, and this count value is used as the coarse time point. It should be noted that the free count value and the coarse time point are not the same time. Since the coarse time point needs to be latched upon the rising edge of the second GNSS frequency signal, the coarse time point is delayed compared to the free count value.

[0079] S420: Obtain a detailed measurement time period using a delay chain constructed based on a carry chain.

[0080] Specifically, the carry chain is a dedicated resource in the field programmable gate array (FPG) for high-speed addition calculations. With a delay time of only tens of picoseconds, the delay chain formed by the carry chain serves as a scale for fine time measurement, achieving picosecond-level time measurement resolution, thereby improving the resolution of time measurement.

[0081] In one embodiment, step S410 includes:

[0082] S411. Input the second frequency signal GNSS into the delay chain; sample the second frequency signal GNSS in the delay chain and output the sampled signal to a counting encoder; the counting encoder encodes the sampled signal and uses the encoding result as a fine measurement time period.

[0083] Specifically, please refer to Figure 5 as well as Figure 6 , the second frequency signal GNSS is a pulse signal, and the second frequency signal GNSS is transmitted to the delay chain in real time through the input terminal CIN (transmission can only be performed when the first enable terminal D0-D3 is "0" and the second enable terminal S0-S3 is "1"), and is valid when the second frequency signal GNSS is "1", that is, the high level is valid. The high level of the second frequency signal GNSS is sampled in real time by the D flip-flop group. Among them, the first frequency signal CLK is used as the clock signal of the D flip-flop group. It can be understood that when the rising edge of the first frequency signal CLK arrives, the D flip-flop group will transmit the sampling signal to the counting encoder, and the counting encoder will encode the sampling signal. The encoding result at this time is the fine measurement time period. By adopting delay chain measurement to improve the accuracy of time measurement, and first sampling through the D flip-flop group and then encoding, the probability of the occurrence of metastable state of the second frequency signal GNSS in the delay chain can be reduced.

[0084] S430: Obtain a time error between adjacent pulses of the second frequency signal GNSS according to the coarse measurement time point and the fine measurement time period.

[0085] Specifically, if Figure 2 As shown, the coarse measurement time points include a first coarse measurement time point tcoarse1 and a second coarse measurement time point tcoarse2. The first coarse measurement time point tcoarse1 is the previous rising edge of the first frequency signal CLK (the count value latched by the free counter 3112 at the previous moment when the rising edge of the second frequency signal GNSS arrives), and the second coarse measurement time point tcoarse2 is the next rising edge of the first frequency signal CLK (the count value latched by the free counter 3112 at the next moment when the rising edge of the second frequency signal GNSS arrives). The fine measurement time period includes a first fine measurement time period tfine1 and a second fine measurement time period tfine2. The first fine measurement time period tfine1 is the previous fine measurement time period corresponding to the first coarse measurement time point tcoarse1, and the second fine measurement time period tfine2 is the next fine measurement time period corresponding to the second coarse measurement time point tcoarse2.

[0086] The first coarse measurement time point tcoarse1 minus the first fine measurement time period tfine1 is used as the first time point t1 of the second frequency signal GNSS; the second coarse measurement time point tcoarse2 minus the second fine measurement time period tfine2 is used as the second time point t2 of the second frequency signal GNSS; the difference between the first time point t1 and the second time point t2 is used as the time error between adjacent pulses of the second frequency signal GNSS.

[0087] S500: Calculate a time compensation value according to the time error.

[0088] The time error is used as initial data, and the initial data is processed by a Kalman filter algorithm to obtain a time compensation value.

[0089] Specifically, the time error is input as initial data into the processor chip 400. The processor chip 400 uses this initial data to obtain the error data between the current first frequency signal CLK and the second frequency signal GNSS. The processor chip 400 then processes this error data using a Kalman filter algorithm to obtain the compensation value required by the free counter 3112 at the next moment, namely, the time compensation value. It should be noted that when constructing the free counter 3112 using the first frequency signal CLK, the first frequency signal CLK is an oscillation signal generated by the oven-controlled crystal oscillator 100. Therefore, the count value obtained by the free counter 3112 is the local time. However, due to temperature or aging effects of the oven-controlled crystal oscillator 100, the local time may be inaccurate. Local time is then compensated using the error data from the second frequency signal GNSS (the second frequency signal GNSS is a satellite signal received by an antenna, and the satellite has a high-stability crystal oscillator with long-term stability, low phase noise, high frequency temperature stability, and high frequency accuracy). Therefore, the time compensation value required by the free counter 3112 is used.

[0090] Among them, the time compensation value includes a phase compensation value and a frequency deviation compensation value. The phase compensation value is the time error that needs to be compensated at the "0" moment of the free counter 3112 cycle at the next moment, and the frequency deviation compensation value is the time error that needs to be compensated for the free counter 3112 cycle at the next moment, that is, the total time error from "0" to "9999999999".

[0091] In one embodiment, step S500 includes:

[0092] S510 , taking the time error as initial data, and processing the initial data through a Kalman filter algorithm to obtain a second-level phase compensation value phase_s, a nanosecond-level phase compensation value phase_ns, and a nanosecond-level frequency offset compensation value freq_ns.

[0093] If the second-level free counter and the nanosecond-level free counter are constructed based on the first frequency signal CLK, that is, when the free counter 3112 with higher precision is available, the initial data can be processed using the Kalman filter algorithm to obtain a second-level phase compensation value phase_s, a nanosecond-level phase compensation value phase_ns, and a nanosecond-level frequency offset compensation value freq_ns, thereby further improving the time accuracy of subsequent real-time time.

[0094] S600: Accumulate the free count value and the time compensation value to obtain real time.

[0095] The free count value is the local time generated by the current constant temperature crystal oscillator 100, and the time compensation value is the time error that needs to be compensated compared to the second frequency signal GNSS received by the antenna. By accumulating the free count value and the time compensation value to correct the local time, accurate real-time time is obtained.

[0096] In one embodiment, step S600 includes:

[0097] S610: Convert the total nanosecond frequency offset compensation value into a nanosecond frequency offset compensation value of a single clock cycle.

[0098] Specifically, since the frequency deviation value of the constant temperature crystal oscillator 100 within one second of local time will not be very large, generally between microseconds and nanoseconds, the frequency deviation compensation value can only obtain a nanosecond-level frequency deviation compensation value, and cannot obtain a second-level frequency deviation compensation value. It should be noted that the frequency deviation compensation value can also reach the picosecond level (the delay chain used by the fine measurement module 312 can reach the picosecond level), but the noise in the current system is only within the nanosecond level, so the picosecond-level frequency deviation compensation value is not used.

[0099] The total nanosecond frequency offset compensation value refers to the total frequency offset compensation value required when the nanosecond free-wheeling counter 3112 counts from "0" to "999999990." However, the phase compensation value obtained is for a single clock cycle. Therefore, the total nanosecond frequency offset compensation value must be converted into the nanosecond frequency offset compensation value for a single clock cycle, that is, the frequency offset compensation value for the current clock cycle. For example, the frequency offset compensation value at "0," "10," "20," and so on, is the frequency offset compensation value for "999999990."

[0100] like Figure 7As shown, the current total nanosecond frequency offset compensation value freq_ns is latched, and the free count value free_ns and the total nanosecond frequency offset compensation value freq_ns are used as multiplier inputs, and the resulting product is divided by 32'd1000000000 to obtain the nanosecond frequency offset compensation value real_freq_ns of the current single clock cycle.

[0101] It should be noted that the total nanosecond-level frequency offset compensation value can be used to obtain not only the nanosecond-level frequency offset compensation value for a single clock cycle, but also the picosecond-level frequency offset nanosecond value for a single clock cycle, and the femtosecond-level frequency offset compensation value for a single clock cycle. The choice can be made based on the actual time accuracy required, and there is no specific limitation.

[0102] Taking the picosecond frequency offset value for a single clock cycle as an example, for example, the total frequency offset compensation value is 1500.125456ns, where 1500 represents nanoseconds, 123 represents picoseconds, and 456 represents femtoseconds. Convert the valid digits to an integer and latch them. That is, 1500.123 is converted to 1500123. Multiply 1500123 by the current free count value and divide by 1000000000 to obtain the picosecond compensation value for each clock cycle.

[0103] S620: Accumulate the nanosecond free count value, the nanosecond phase compensation value, and the nanosecond frequency offset compensation value of a single clock cycle, and output a second-level carry.

[0104] Specifically, the nanosecond free count value is the count value of the current nanosecond free counter 3112, that is, the nanosecond local time generated by the current constant temperature crystal oscillator 100. The nanosecond local time, the nanosecond phase compensation value and the nanosecond frequency deviation compensation value of a single clock cycle are accumulated to correct the nanosecond local time, that is, the current nanosecond real-time time and second carry are obtained.

[0105] S630: Accumulate the second-level carry, the second-level free time value, and the second-level phase compensation value to output the second-level local time.

[0106] Specifically, the second-level free count value is the count value of the current second-level free counter 3112, that is, the second-level local time generated by the current constant temperature crystal oscillator 100. By accumulating the second-level local time, the second-level carry and the second-level phase compensation value, the second-level local time is corrected to obtain the current second-level real-time time. Figure 3 As shown, the maximum time data error within 10,000 seconds does not exceed plus or minus 15ns, most of the data are within 10ns, and the time data error is less than 10ns.

[0107] Please refer to Figure 4The present invention also provides a time reference device, comprising: an oven-controlled crystal oscillator 100, a receiver 200, a field programmable gate array (FPGA), and a processor chip 400; the oven-controlled crystal oscillator 100 is connected to the FPGA and configured to generate an oscillation signal and output it to the FPGA. The receiver 200 is connected to an antenna and the FPGA, respectively, and configured to receive a second frequency signal GNSS from the antenna; the FPGA includes a time measurement module, a phase-locked loop (PLL) module 320, and a time synthesis module 330; the phase-locked loop (PLL) module 320 is connected to the oven-controlled crystal oscillator 100 and the time measurement module, respectively, and configured to multiply the oscillation signal and output a first frequency signal CLK to the time measurement module; the time measurement module is connected to the receiver 200 and the PLL module 320, respectively, and configured to construct a free counter based on the first frequency signal CLK to obtain a free count value, and to obtain a time error between adjacent pulses of the second frequency signal GNSS based on the first frequency signal CLK and the second frequency signal GNSS. The processor chip 400 is connected to the time measurement module respectively, and is used to calculate the time compensation value according to the time error; the time synthesis module 330 is connected to the time measurement module and the processor chip 400 respectively, and is used to accumulate the free count value and the time compensation value to obtain the real-time time.

[0108] The time measurement module is connected to the receiver 200 and the phase-locked loop module 320 to obtain the free count value (the local time currently generated by the oven-controlled crystal oscillator 100) and the time error between adjacent pulses of the second frequency signal GNSS. The processor chip 400 is connected to the time module to calculate a time compensation value based on the time error. The time synthesis module 330 is further connected to the time measurement module and the processor chip 400 to accumulate the free count value and the time compensation value to obtain the real-time time. This fully digital (linear) time compensation is implemented to correct the local time, thereby obtaining the current real-time time. This eliminates the need for analog-to-digital conversion of frequency and voltage, thereby avoiding the problem of additional errors in calibrating the time base and further improving time accuracy.

[0109] The field programmable gate array (FPGA) includes the time measurement module, the phase-locked loop (PLL) module 320, and the time synthesis module 330. It can be understood that the time measurement module, the phase-locked loop (PLL) module 320, and the time synthesis module 330 are integrated within the FPGA. In other words, the entire time reference device consists of only the FPGA chip and the processor chip 400, without requiring other independent chips (e.g., a TDC chip, a DDS chip, a DAC chip, or a PLL chip). This reduces the structural complexity of the time reference device. Furthermore, the reduced number of independent chips facilitates integration into other time-sensitive systems.

[0110] In one embodiment, the time measurement module includes: a coarse measurement module 311 and a fine measurement module 312; the coarse measurement module 311 is respectively connected to the receiver 200 and the phase-locked loop module 320, and is used to construct a free counter based on the first frequency signal CLK, obtain a time count value, and use the second frequency signal GNSS as a reference signal to latch the current coarse measurement time point of the free counter; the fine measurement module 312 is respectively connected to the receiver 200, the phase-locked loop module 320 and the processor chip 400, and is used to sample the second frequency signal GNSS, output a sampling signal based on the first frequency signal CLK, and encode the sampling signal, and output the encoding result as a fine measurement time period to the processor chip 400.

[0111] Specifically, if Figure 5 As shown, the coarse measurement module 311 includes a D-type flip-flop synchronizer 3111, a free counter 3112, and a latch 3113. The D-type flip-flop synchronizer 3111 is connected to the receiver 200, the phase-locked loop module 320, and the latch 3113, respectively, for stabilizing the clock edge of the second frequency signal GNSS and using the stabilized signal as the latch signal of the latch 3113. The free counter 3112 is connected to the phase-locked loop module 320 and the latch 3113, respectively, for counting according to the first frequency signal CLK and outputting the counting result to the processor chip as a free count value. Furthermore, the counting result is output to the latch 3113. The latch 3113 is connected to the D-type flip-flop synchronizer 3111 and the free counter 3112, respectively, for latching the counting result according to the latch signal. The details are as described in the embodiment of a time accuracy method and will not be repeated here.

[0112] like Figure 5 as well as Figure 6As shown, the fine measurement module 312 includes a delay chain, a D-type flip-flop group, and a counting encoder; the delay chain is respectively connected to the receiver 200 for receiving the second frequency signal GNSS in real time; the D-type flip-flop group is connected to the delay chain, the phase-locked loop module 320, and the counting encoder for sampling the second signal and outputting the sampling signal to the counting encoder when the first frequency signal CLK arrives. The counting encoder is connected to the D-type flip-flop group for counting the sampling signal and using the counting result as the fine measurement time period. It should be noted that the details are as described in an embodiment of a high time precision method and will not be repeated here.

[0113] In one embodiment, the time reference device further includes: a time compensator 340;

[0114] The time compensator 340 is connected to the processor chip 400 and the time synthesis module 330 respectively, and is used to convert the total time compensation value into the nanosecond frequency offset compensation value of a single clock cycle.

[0115] In summary, the present invention provides a time base processing method, including: generating an oscillation signal through a constant temperature crystal oscillator; multiplying the oscillation signal to obtain a first frequency signal, and receiving a second frequency signal from an antenna; constructing a free counter through the first frequency signal to obtain a free count value; obtaining the time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal; calculating a time compensation value according to the time error; accumulating the free count value and the time compensation value to obtain real-time time. The present invention constructs a free counter through the first frequency signal to obtain a free count value, i.e., local time, and calculates a time compensation value according to the time error, and then accumulates the free count value and the time compensation value to achieve full digital (linear) time compensation to correct the local time, i.e., obtain the current real-time time, without the need for analog-to-digital conversion such as frequency and voltage, so as to avoid the problem of additional errors when calibrating the time base, thereby further improving time accuracy.

[0116] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A time reference processing method, characterized in that: include: Generate an oscillation signal through a constant temperature crystal oscillator; multiplying the oscillation signal to obtain a first frequency signal, and receiving a second frequency signal from an antenna; constructing a free counter by using the first frequency signal to obtain a free count value; Acquire a time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal; Using the second frequency signal as a reference signal, latching the current rough measurement time point of the free counter; A delay chain based on a carry chain is used to obtain a detailed measurement time period; inputting the second frequency signal into the delay chain; sampling the second frequency signal in the delay chain and outputting a sampling signal to a counting encoder; The counting encoder encodes the sampling signal and uses the encoding result as the fine measurement time period; Obtaining a time error between adjacent pulses of the second frequency signal according to the coarse measurement time point and the fine measurement time period; The coarse measurement time point includes a first coarse measurement time point and a second coarse measurement time point, the first coarse measurement time point being the previous rising edge of the first frequency signal, and the second coarse measurement time point being the next rising edge of the first frequency signal; the fine measurement time period includes a first fine measurement time period and a second fine measurement time period, the first fine measurement time period being the previous fine measurement time period corresponding to the first coarse measurement time point, and the second fine measurement time period being the next fine measurement time period corresponding to the second coarse measurement time point; the first coarse measurement time point minus the first fine measurement time period is used as the first time point of the second frequency signal; the second coarse measurement time point minus the second fine measurement time period is used as the second time point of the second frequency signal; the difference between the first time point and the second time point is used as the time error between adjacent pulses of the second frequency signal; Calculating a time compensation value according to the time error; The free count value and the time compensation value are accumulated to obtain the real time.

2. The time reference processing method according to claim 1, wherein: The step of constructing a free counter by using the first frequency signal to obtain a free count value comprises: A second-level free counter and a nanosecond-level free counter are constructed using the first frequency signal, and the second-level free counter and the nanosecond-level free counter are output.

3. The time reference processing method according to claim 2, wherein: The step of calculating the time compensation value according to the time error comprises: Taking the time error as initial data; The initial data is processed by a Kalman filter algorithm to obtain a second-level phase compensation value, a nanosecond-level phase compensation value, and a nanosecond-level frequency offset compensation value.

4. The time reference processing method according to claim 3, wherein: The step of accumulating the free count value, the phase compensation value, and the frequency offset compensation value to obtain real time includes: Converting the total nanosecond frequency offset compensation value into the nanosecond frequency offset compensation value of a single clock cycle; Accumulate the nanosecond free count value, the nanosecond phase compensation value, and the nanosecond frequency offset compensation value of a single clock cycle, and output nanosecond real-time time and second-level carry; The second-level carry, the second-level free count value, and the second-level phase compensation value are accumulated to output the second-level real-time time.

5. A time reference device applied to the time reference processing method according to any one of claims 1 to 4, characterized in that: include: Oven-controlled crystal oscillators, receivers, field-programmable gate arrays, and processor chips; The constant temperature crystal oscillator is connected to the field programmable gate array, and is used to generate an oscillation signal and output it to the field programmable gate array; The receiver is connected to the antenna and the field programmable gate array respectively, and is used to receive the second frequency signal from the antenna; The field programmable gate array includes a time measurement module, a phase-locked loop module and a time synthesis module; The phase-locked loop module is connected to the constant temperature crystal oscillator and the time measurement module respectively, and is used to multiply the frequency of the oscillation signal and output a first frequency signal to the time measurement module; The time measurement module is connected to the receiver and the phase-locked loop module respectively, and is used to construct a free counter according to the first frequency signal to obtain a free count value, and obtain a time error between adjacent pulses of the second frequency signal according to the first frequency signal and the second frequency signal; The processor chips are respectively connected to the time measurement modules, and are used to calculate the time compensation value according to the time error; The time synthesis module is connected to the time measurement module and the processor chip respectively, and is used to accumulate the free count value and the time compensation value to obtain real time.

6. The time reference device according to claim 5, characterized in that The time measurement module includes: a coarse measurement module and a fine measurement module; The coarse measurement module is connected to the receiver and the phase-locked loop module respectively, and is used to construct a free counter according to the first frequency signal, obtain a free count value, and latch the current coarse measurement time point of the free counter using the second frequency signal as a reference signal; The fine measurement module is connected to the receiver, the phase-locked loop module and the processor chip respectively, and is used to sample the second frequency signal, output a sampling signal according to the first frequency signal, and encode the sampling signal, and output the encoding result as a fine measurement time period to the processor chip.

7. The time reference device according to claim 5, characterized in that Also includes: Time compensator; The time compensator is connected to the processor chip and the time synthesis module respectively, and is used to convert the total time compensation value into the time compensation value of a single clock cycle.

8. The time reference device according to claim 6, characterized in that The coarse detection module includes a D flip-flop synchronizer, a free counter and a latch; The D flip-flop synchronizer is connected to the receiver, the phase-locked loop module and the latch respectively, and is used to stabilize the clock edge of the second frequency signal and use the stabilized signal as the latch signal of the latch; The free counter is connected to the phase-locked loop module and the latch respectively, and is used to count according to the first frequency signal and output the counting result to the latch; The latch is connected to the D flip-flop synchronizer and the free counter respectively, and is used to latch the counting result according to the latch signal.

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