Method for forming a semiconductor structure

Abstract

The present application provides a method for forming a semiconductor structure, by integrating a deep trench isolation mask process into an active area reverse plate mask process, and simultaneously forming an active area reverse plate region and a deep trench isolation region on a substrate through a single mask process. When manufacturing a deep trench isolation structure, there is no need to perform a separate hard mask layer mask process and a hard mask layer etching process for deep trench isolation, thus saving a mask process and related etching processes. By setting a graphic hard mask layer and a first buffer layer to use different materials, active area reverse plate etching and deep trench etching can be achieved by controlling the etching rates of different materials in the etching process. The present application simplifies the process steps, can effectively reduce costs, and improve the competitiveness of the process platform.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Deep Trench Isolation (DTI) is a commonly used high-voltage device isolation structure. It achieves high-voltage isolation by etching a deep trench and filling it with oxide. Currently, deep trench isolation is mainly used in process platforms such as BCD (Bipolar-CMOS-DMOS), Shielded Gate Trench (SGT), and Transient Voltage Suppressor (TVS). Among them, the BCD process is a process technology that integrates bipolar devices, complementary metal oxide semiconductor (CMOS) devices, and double-diffused metal oxide semiconductor (DMOS) devices on the same chip. It has the advantages of bipolar high transconductance and strong load driving capability and CMOS high integration and low power consumption. At the same time, DMOS can operate in switching mode, making the chip power consumption extremely low.

[0003] Please also refer to Figures 1 and 2 ,in, Figure 1 This is a BCD process flow chart without deep trench isolation in the prior art. Figure 2 FIG. 1 is a flow chart of a BCD process with deep trench isolation in the prior art.

[0004] like Figure 1 As shown in the figure, the main process flow of the BCD process without deep trench isolation is: S11, Boro-Phospho-Silicate Glass (BPSG) layer deposition (DEP) process; BPSG is silicon dioxide doped with boron and phosphorus, which is generally used as the first layer of pre-metal dielectric (PMD) and inter-metal dielectric (AVID); S12, isolation layer deposition process; S13, inter-layer dielectric (ILD) layer deposition and chemical mechanical polishing (CMP) process; S14, metal interconnect (CT) process.

[0005] like Figure 2As shown, the main process flow of the BCD process with deep trench isolation is as follows: S21, borophosphosilicate glass layer deposition process; S22, isolation layer deposition process; S23, interlayer dielectric layer deposition and chemical mechanical polishing process; S24, deep trench isolation hard mask layer (HM) photomask (PH) process; S25, hard mask layer etch (ET) process; S26, deep trench isolation etch process; S27, isolation layer fill process; S28, isolation layer chemical mechanical polishing process; S29, metal interconnect process. Among them, steps S24 to S28 are newly added processes for deep trench isolation.

[0006] Depend on Figure 1 and Figure 2 As can be seen from the process flow shown, although the deep trench isolation structure has a good isolation effect, a mask (step S24) and more additional processes (steps S25 to S28) need to be added during the production of the deep trench isolation structure, which complicates the production process and increases product cost.

[0007] Therefore, how to optimize the manufacturing process of the deep trench isolation structure and reduce the cost is a technical problem that needs to be urgently solved in the existing technology. Summary of the Invention

[0008] The technical problem to be solved by the present application is to provide a method for forming a semiconductor structure so as to optimize the manufacturing process of a deep trench isolation structure in the semiconductor structure, reduce costs, and improve the competitiveness of the process platform.

[0009] In order to solve the above problems, the present application provides a method for forming a semiconductor structure, which includes the following steps: providing a base, the base including a semiconductor substrate, a patterned hard mask layer formed on the surface of the semiconductor substrate, a first buffer layer and a patterned photoresist layer, the patterned photoresist layer defines an active area counter-plate area and a deep trench isolation area, and the patterned hard mask layer and the first buffer layer are made of different materials; using the patterned photoresist layer as a mask, etching is performed by an etching process to form deep trenches in the deep trench isolation area and expose the patterned hard mask layer in the active area counter-plate area; planarizing the first buffer layer by a planarization process; depositing an isolation material to form an isolation layer that fills the deep trench and covers the remaining surface of the patterned hard mask layer and the remaining surface of the first buffer layer; planarizing the isolation layer by a planarization process to form a deep trench isolation structure at the deep trench.

[0010] In some embodiments, the etching process has a higher etching rate for the first buffer layer than for the patterned hard mask layer, and a higher etching rate for the semiconductor substrate than for the patterned hard mask layer.

[0011] The above technical solution integrates the deep trench isolation mask process into the active area counter-plate mask process, and simultaneously forms the active area counter-plate area and the deep trench isolation area on the substrate through one mask process. When manufacturing the deep trench isolation structure, there is no need to perform a separate hard mask layer mask process and a hard mask layer etching process for deep trench isolation, thus saving one mask process and related etching process; by setting the graphic hard mask layer and the first buffer layer to use different materials, the active area counter-plate etching and deep trench etching can be achieved by controlling the etching rates of different materials in the etching process; this application simplifies the process steps, which can effectively reduce costs and improve the competitiveness of the process platform.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present application. Technologies, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0014] Figure 1 This is a flow chart of the BCD process without deep trench isolation in the prior art;

[0015] Figure 2 This is a flow chart of the BCD process with deep trench isolation in the prior art;

[0016] Figure 3 is a flow chart of a method for forming a semiconductor structure provided by one embodiment of the present application;

[0017] Figures 4 to 10 This is a schematic diagram of a device structure formed by the main steps of a method for forming a semiconductor structure in one embodiment of the present application. DETAILED DESCRIPTION

[0018] The following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0019] Please also refer to Figures 3 to 10 ,in, Figure 3 is a flow chart of a method for forming a semiconductor structure provided by an embodiment of the present application. Figures 4 to 10 This is a schematic diagram of a device structure formed by the main steps of a method for forming a semiconductor structure in one embodiment of the present application.

[0020] like Figure 3 As shown, the method for forming a semiconductor structure described in this embodiment includes the following steps: S1, providing a base, the base including a semiconductor substrate, a patterned hard mask layer formed on the surface of the semiconductor substrate, a first buffer layer and a patterned photoresist layer, the patterned photoresist layer defines an active area counter-plate area and a deep trench isolation area, and the patterned hard mask layer and the first buffer layer are made of different materials; S2, using the patterned photoresist layer as a mask, etching by an etching process to form a deep trench in the deep trench isolation area and expose the patterned hard mask layer in the active area counter-plate area; S3, planarizing the first buffer layer by a planarization process; S4, depositing an isolation material to form an isolation layer that fills the deep trench and covers the remaining surface of the patterned hard mask layer and the remaining surface of the first buffer layer; and, S5, planarizing the isolation layer by a planarization process to form a deep trench isolation structure at the deep trench.

[0021] Please refer to step S1 and Figure 4 A substrate 400 is provided, the substrate 400 including a semiconductor substrate 41, a patterned hard mask layer 42 formed on the surface of the semiconductor substrate 41, a first buffer layer 43, and a patterned photoresist layer 44. The patterned photoresist layer 44 defines an active area reverse plate region 401 and a deep trench isolation region 402. In this embodiment, a deep trench isolation photomask (DTI PH) process is integrated into an active area reverse plate photomask (ADR PH) process; the active area reverse plate region 401 and the deep trench isolation region 402 are simultaneously formed on the substrate 400 through a single photomask process, eliminating the need for a separate DTI PH process and saving a single photomask process. In this embodiment, the patterned hard mask layer 42 and the first buffer layer 43 are made of different materials, so that in a subsequent etching process, active area reverse plate etching and deep trench etching can be achieved by controlling the etching rates of the different materials.

[0022] In some embodiments, the base 400 is further formed by the following steps: 1) providing the semiconductor substrate 41; 2) forming the patterned hard mask layer 42 on the surface of the semiconductor substrate 41, such as Figure 5A3) etching the semiconductor substrate 41 with the patterned hard mask layer 42 as a mask to form a plurality of first grooves 51, as shown Figure 5B 4) depositing a buffer material to form the first buffer layer 43 filling the first groove 51 and covering the surface of the patterned hard mask layer 42, as shown Figure 5C 5) forming the patterned photoresist layer 44 on the surface of the first buffer layer 43, the patterned photoresist layer 44 having a first opening and a second opening exposing at least a portion of the surface of the first buffer layer 43, wherein the first opening corresponds to the location of the first groove 51 and defines the deep trench isolation region 402, the second opening corresponds to the location of the patterned hard mask layer 42 and defines the active area counter-plate region 401, as shown Figure 4 shown.

[0023] The hard mask layer (HM) is an inorganic thin film material generated by chemical vapor deposition (CVD), and its main components are usually TiN, SiN, SiO2, etc. Specifically, following the above embodiment, the patterned hard mask layer 42 may include a second buffer layer 421 and a barrier layer 422 sequentially formed on the semiconductor substrate 41. In this embodiment, the semiconductor substrate 41 is a silicon (Si) substrate, and the semiconductor substrate 41 can also be made of any semiconductor material suitable for the semiconductor structure (such as Si, SiC, SiGe, etc.). In this embodiment, the material of the second buffer layer 421 is silicon oxide (SiO), which is used to reduce the damage of the stress of the barrier layer 422 to the semiconductor substrate 41. In this embodiment, the material of the barrier layer 422 is silicon nitride (SIN), which serves as a barrier layer for etching and subsequent grinding processes to protect the semiconductor substrate 41. In this embodiment, the material of the first buffer layer is silicon oxide (SiO), so that in the subsequent etching process, active area reverse etching and deep trench etching can be achieved by controlling the etching rates of different materials.

[0024] Specifically, following the above embodiment, the step of forming the patterned hard mask layer 42 on the surface of the semiconductor substrate 41 further includes: 21) forming an initial hard mask layer on the surface of the semiconductor substrate 41; and 22) providing a first photomask and etching the initial hard mask layer using the first photomask as a mask to form the patterned hard mask layer 42. The patterned hard mask layer 42 has a plurality of openings whose bottoms are located on the semiconductor substrate, so that the semiconductor substrate 41 can be subsequently etched using the patterned hard mask layer 42 as a mask to form first recesses 51 at the openings.

[0025] Photoresist (PR), also known as photoresist, is a light-sensitive organic compound whose solubility in the developer changes after being exposed to ultraviolet light. The pattern on the mask can be transferred to the photoresist layer on the top layer of the wafer surface through the photoresist. Specifically, following the above embodiment, the step of forming the patterned photoresist layer 44 on the surface of the first buffer layer 43 further includes: 51) forming an initial photoresist layer on the surface of the first buffer layer 43; 52) providing a second mask, and using the second mask as a mask to expose and develop the initial photoresist layer to form the patterned photoresist layer 44, wherein the patterned photoresist layer 44 defines the active area counterplate region 401 and the deep trench isolation region 402. Compared with the prior art in which the deep trench isolation mask and the active area counter plate mask use different masks respectively, and two different mask processes are required to form the active area counter plate region and the deep trench isolation region on the substrate respectively, this embodiment uses a mask process to simultaneously form the active area counter plate region 401 and the deep trench isolation region 402 on the substrate 400, without the need for a separate DTI PH process, thus saving a mask process.

[0026] Please refer to step S2 and Figure 6 Using the patterned photoresist layer 44 as a mask, an etching process is employed to form deep trenches 61 in the deep trench isolation region 402 and expose the patterned hard mask layer 42 in the active area counter plate region 402. In this embodiment, the deep trench etching and active area counter plate etching are integrated, and by controlling the etching rates of different material layers, the deep trenches 61 are etched in the deep trench isolation region 402, and the patterned hard mask layer 42 is exposed by etching in the active area counter plate region 402. The etching process has a higher etching rate for the first buffer layer 43 than for the patterned hard mask layer 42, and a higher etching rate for the semiconductor substrate 41 than for the patterned hard mask layer 42. As a result, the deep trenches 61 can be etched in the deep trench isolation region 402, and the patterned hard mask layer 42 can be exposed by etching in the active area counter plate region 402. Among them, the patterned hard mask layer 42 serves as an etching barrier layer and has a relatively high thickness (thickness greater than or equal to a preset threshold), so that a certain thickness is retained after etching, protecting the semiconductor substrate 41 in the corresponding area of ​​the patterned hard mask layer 42 from damage.

[0027] In some embodiments, step S2 is further formed by the following steps: 1) using the patterned photoresist layer 44 as a mask, etching the first buffer layer 43 using a first etching process to form a shallow trench 71 with a bottom located on the semiconductor substrate 41 in the deep trench isolation region 402, exposing the patterned hard mask layer 42 in the active area counter plate region 401, and Figure 7A 2) removing the remaining patterned photoresist layer 44, the first buffer layer 43 after etching as a mask, using a second etching process to continue etching, forming a deep trench 61 in the shallow trench 71, thinning the exposed patterned hard mask layer 42, as Figure 7B That is, during the active area reverse etching process, the patterned hard mask layer 42 is used as an etch stop layer to control the etching rates of different materials. During the deep trench etching process, the patterned hard mask layer 42 is also used as an etch stop layer to control the etching rates of different materials, and finally a deep trench 61 is obtained.

[0028] Specifically, the etching rate of the first buffer layer 43 in the first etching process (active area reverse etching process) is higher than the etching rate of the patterned hard mask layer 42; that is, the patterned hard mask layer 42 (mainly the SIN layer therein) is used as an etching stop layer, and by ensuring a certain SIO / SIN etching selectivity ratio (that is, the same etching method has different etching rates for different materials), the etching rate of the first buffer layer 43 is higher, thereby etching a shallow trench 71, and the etching rate of the patterned hard mask layer 42 is lower, so that it can serve as an etching stop layer, so that only the first buffer layer 43 thereon is etched away to expose the patterned hard mask layer 42.

[0029] Specifically, the second etching process (deep trench etching process) has a higher etching rate for the semiconductor substrate 41 than for the patterned hard mask layer 42; that is, after removing the remaining patterned photoresist layer 44, the etched first buffer layer 43 is used as a mask, and the patterned hard mask layer 42 (mainly the SIN layer therein) is used as an etch stop layer. By ensuring a certain SIN / SIN etching selectivity, the etching rate of the semiconductor substrate 41 is high, thereby etching the deep trench 61, and the etching rate of the patterned hard mask layer 42 is low, thereby serving as an etch stop layer, so that the exposed patterned hard mask layer 42 is only thinned to a certain thickness. The patterned hard mask layer 42 still retains a certain thickness after etching to protect the semiconductor substrate 41 in the corresponding area of ​​the patterned hard mask layer 42 from damage.

[0030] In some embodiments, the etching process is a reactive ion etching (RIE) process. Reactive ion etching utilizes chemically reactive gases to generate chemically active groups and ions. These high-energy ions, accelerated by an electric field, bombard the material being etched, damaging the surface, increasing the surface activity of the material being etched, and accelerating the reaction rate with the active etching reactive groups, thereby achieving a higher etching rate. Reactive ion etching offers excellent morphology control (anisotropy), high selectivity, and acceptable etching rates.

[0031] Please refer to step S3 and Figure 8 , a planarization process is used to planarize the first buffer layer 43. Specifically, the planarization process is a chemical mechanical polishing (CMP) process. Chemical mechanical polishing technology combines the advantages of chemical polishing and mechanical polishing, and can obtain a surface with higher flatness while ensuring the efficiency of material removal. Among them, if the patterned photoresist layer 44 is used as a mask to directly etch to form a deep groove 61, then before this step, it is necessary to remove the remaining patterned photoresist layer 44; if the patterned photoresist layer 44 is used as a mask to first etch to form a shallow groove 71, remove the remaining patterned photoresist layer 44 and use the etched first buffer layer 43 as a mask to etch to form a deep groove 61, then before this step, it is not necessary to remove the remaining patterned photoresist layer 44.

[0032] Please refer to step S4 and Figure 9 An isolation material is deposited to form an isolation layer 45 that fills the deep trench 61 and covers the remaining surface of the patterned hard mask layer 42 and the remaining surface of the first buffer layer 43. In some embodiments, the isolation material is deposited using a chemical vapor deposition process. In some embodiments, the isolation layer is made of tetraethoxysilane (TEOS), silicon oxide (SIO), or a dielectric material with a certain dielectric constant. TEOS, also known as tetraethyl silicate, is an organic compound.

[0033] Please refer to step S4 and Figure 10 The isolation layer 45 is planarized using a planarization process to form a deep trench isolation structure 110 at the deep trench. Specifically, the planarization process is a chemical mechanical polishing (CMP) process. At this point, the deep trench isolation structure described in this application has been completed.

[0034] In some embodiments, after forming a deep trench isolation structure in the deep trench, the step further includes forming a transistor structure in the active area counterplate region. The process flow for forming the transistor structure can refer to the existing process flow and will not be repeated here.

[0035] In some embodiments, after forming a deep trench isolation structure in the deep trench, the step further includes: performing a metal interconnection process on the deep trench isolation structure to form a metal interconnection structure. The process flow for forming the metal interconnection structure can refer to the existing process flow and will not be repeated here.

[0036] Compared to Figure 2 The existing deep trench isolation process flow shown requires a separate hard mask layer photomask process and a hard mask layer etching process for deep trench isolation (steps S24 to S25). The above-mentioned embodiment of the present application does not require a separate hard mask layer photomask process and a hard mask layer etching process for deep trench isolation when manufacturing the deep trench isolation structure, thereby saving a photomask process and a related etching process; by setting the graphic hard mask layer and the first buffer layer to use different materials, the active area reverse plate etching and deep trench etching can be achieved by controlling the etching rates of different materials in the etching process; the present application simplifies the process steps, which can effectively reduce costs and improve the competitiveness of the process platform.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments.

[0038] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. It should be noted that those skilled in the art may make improvements and modifications without departing from the principles of the present application, and such improvements and modifications shall also be considered within the scope of protection of the present application.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises the following steps: providing a substrate, the substrate comprising a semiconductor substrate, a patterned hard mask layer formed on the surface of the semiconductor substrate, a first buffer layer and a patterned photoresist layer, the patterned photoresist layer defining an active area counter plate region and a deep trench isolation region, the patterned hard mask layer and the first buffer layer being made of different materials, wherein the substrate is further formed by the following steps: providing the semiconductor substrate, forming the patterned hard mask layer on the surface of the semiconductor substrate, etching the semiconductor substrate using the patterned hard mask layer as a mask to form a plurality of first grooves, depositing a buffer material to form a first groove that fills the first grooves and covers the patterned hard mask layer. The first buffer layer is on the surface of the hard mask layer, and the patterned photoresist layer is formed on the surface of the first buffer layer, and the first groove corresponds to the deep trench isolation area; the patterned photoresist layer is used as a mask and an etching process is adopted to perform etching to form a deep trench in the deep trench isolation area and expose the patterned hard mask layer in the active area counter-plate area; the first buffer layer is planarized by a planarization process; an isolation material is deposited to form an isolation layer that fills the deep trench and covers the remaining surface of the patterned hard mask layer and the remaining surface of the first buffer layer; the isolation layer is planarized by a planarization process to form a deep trench isolation structure at the deep trench.

2. The method according to claim 1, characterized in that The patterned photoresist layer has a first opening and a second opening that expose at least a portion of the surface of the first buffer layer, wherein the first opening corresponds to the location of the first groove and defines the deep trench isolation area, and the second opening corresponds to the location of the patterned hard mask layer and defines the active area counter-plate area.

3. The method according to claim 1, characterized in that The patterned hard mask layer includes a second buffer layer and a blocking layer which are sequentially formed on the semiconductor substrate.

4. The method according to claim 3, characterized in that The semiconductor substrate is a silicon substrate, the material of the second buffer layer is silicon oxide, and the material of the barrier layer is silicon nitride.

5. The method according to claim 1, characterized in that The material of the first buffer layer is silicon oxide, and the material of the isolation layer is tetraethoxysilane or silicon oxide.

6. The method according to claim 1, characterized in that The etching process has a higher etching rate for the first buffer layer than for the patterned hard mask layer, and a higher etching rate for the semiconductor substrate than for the patterned hard mask layer.

7. The method according to claim 1, characterized in that The etching process is a reactive ion etching process, the planarization process is a chemical mechanical polishing process, and the isolation material deposition adopts a chemical vapor deposition process.

8. The method according to claim 1, characterized in that The step of etching using the patterned photoresist layer as a mask and an etching process further includes: using the patterned photoresist layer as a mask, etching the first buffer layer using a first etching process to form a shallow trench with the bottom located on the semiconductor substrate in the deep trench isolation area, and exposing the patterned hard mask layer in the active area counterplate area; removing the remaining patterned photoresist layer, using the etched first buffer layer as a mask, and continuing to etch using a second etching process to form the deep trench at the shallow trench and thin the exposed patterned hard mask layer.

9. The method according to claim 8, characterized in that The etching rate of the first buffer layer in the first etching process is higher than the etching rate of the patterned hard mask layer, and the etching rate of the semiconductor substrate in the second etching process is higher than the etching rate of the patterned hard mask layer.

10. The method according to claim 1, characterized in that After the step of forming a deep trench isolation structure at the deep trench, the method further includes: forming a transistor structure in the active area counterplate region; and / or performing a metal interconnection process at the deep trench isolation structure to form a metal interconnection structure.

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