Method for manufacturing LDMOS integrated device

Abstract

In the method for manufacturing an LDMOS integrated device provided by the present invention, a semiconductor substrate is provided having an NLDMOS region and a PLDMOS region; a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region are then formed on the semiconductor substrate; a stress material layer is formed on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region; a heat treatment is then performed to adjust the stress of the stress material layer; and the stress material layer is then removed. In this manner, the electron mobility of the NLDMOS device and / or the hole mobility of the PLDMOS device can be improved, enabling the simultaneous fabrication of high-performance NLDMOS and high-performance PLDMOS in the same process flow; furthermore, the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, i.e., the thickness of the dielectric layer under the big contact of the NLDMOS region meets its resurf requirements, and the thickness of the dielectric layer under the big contact of the PLDMOS region meets its resurf requirements, thereby overall improving the resurf capability of the big contact of the LDMOS integrated device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing an LDMOS integrated device. Background Art

[0002] BCD process development involves the joint development of multiple devices, including bipolar junction transistors (BJTs), complementary metal oxide semiconductors (CMOS), and double-diffused metal oxide semiconductors (DMOS). DMOS devices can include lateral double-diffused metal oxide semiconductor field-effect transistors (LDMOS) and vertical double-diffused metal oxide semiconductor field-effect transistors (VDMOS). LDMOS devices are more compatible with CMOS processes than VDMOS devices and are therefore widely used in integrated circuit design.

[0003] LDMOS integrated devices include N-channel LDMOS (NLDMOS) devices and P-channel LDMOS (PLDMOS) devices. In the design process of LDMOS integrated devices, how to improve the performance of LDMOS integrated devices remains to be solved. Summary of the Invention

[0004] The present invention provides a method for manufacturing an LDMOS integrated device, which can improve the performance of the LDMOS integrated device.

[0005] In order to achieve the above-mentioned object, the present invention provides a method for manufacturing an LDMOS device. The manufacturing method comprises:

[0006] A semiconductor substrate is provided, comprising an NLDMOS region and a PLDMOS region; a P-type body region and an N-type drift region are formed in the NLDMOS region, an N-type source region is formed on a top portion of the P-type body region, an N-type drain region is formed on a top portion of the N-type drift region, and a first gate structure is formed on the NLDMOS region; an N-type body region and a P-type drift region are formed in the PLDMOS region, a P-type source region is formed on a top portion of the N-type body region, a P-type drain region is formed on a top portion of the P-type drift region, and a second gate structure is formed on the PLDMOS region;

[0007] forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, and forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region;

[0008] performing a heat treatment to adjust the stress of the stress material layer;

[0009] The stressed material layer is removed.

[0010] Optionally, the forming of the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, includes: forming a tensile stress material layer only on the dielectric layer on the NLDMOS region.

[0011] Optionally, forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, includes:

[0012] forming a dielectric material layer covering the semiconductor substrate, the first gate structure, and the second gate structure;

[0013] forming a tensile stress material layer covering the dielectric material layer;

[0014] forming a patterned mask layer on the tensile stress material layer, wherein the mask layer at least exposes the tensile stress material layer on the PLDMOS region, and removing the tensile stress material layer on the PLDMOS region using the mask layer as a mask, so that the remaining tensile stress material layer on the NLDMOS region at least covers the N-type drift region;

[0015] Continuing with the mask layer, the mask layer at least exposes the dielectric material layer on the PLDMOS region, and etching away a portion of the dielectric material layer, so that the thickness of at least the dielectric material layer on the N-type drift region in the NLDMOS region is greater than the thickness of the remaining dielectric material layer on the PLDMOS region, the remaining dielectric material layer on the NLDMOS region being the dielectric layer on the NLDMOS region, and the remaining dielectric material layer on the PLDMOS region being the dielectric layer on the PLDMOS region.

[0016] Optionally, forming a patterned mask layer on the tensile stress material layer, wherein the mask layer at least exposes the tensile stress material layer on the PLDMOS region, and removing the tensile stress material layer on the PLDMOS region using the mask layer as a mask, with the remaining tensile stress material layer on the NLDMOS region at least covering the N-type drift region, comprises:

[0017] The remaining tensile stress material layer on the NLDMOS region further extends from the N-type source region through the first gate structure to cover the N-type drain region.

[0018] Optionally, the thickness of the dielectric layer on the PLDMOS region is 600 angstroms to 1200 angstroms.

[0019] Optionally, the dielectric material layer has a thickness of 1000 angstroms to 1800 angstroms.

[0020] Optionally, the thickness of the tensile stress material layer is 150 angstroms to 600 angstroms.

[0021] Optionally, after removing the stress material layer, the method further comprises:

[0022] Patterning the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region to expose the N-type source region, the N-type drain region, a portion of the first gate structure, the P-type source region, the P-type drain region, and a portion of the second gate structure;

[0023] A suspended conductive plug is formed above the P-type drift region and / or the N-type drift region, wherein the bottom of the suspended conductive plug stays above the P-type drift region and / or the N-type drift region and is spaced a preset distance from the upper surface of the P-type drift region and / or the N-type drift region.

[0024] Optionally, after patterning the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region to expose the N-type source region, the N-type drain region, a portion of the first gate structure, the P-type source region, the P-type drain region, and a portion of the second gate structure,

[0025] Before forming a suspended conductive plug above the P-type drift region and / or the N-type drift region, the method further comprises:

[0026] forming a silicide blocking layer on the patterned dielectric layer on the NLDMOS region and on the dielectric layer on the PLDMOS region;

[0027] forming a metal silicide layer on the upper surfaces of the exposed N-type source region, the N-type drain region, a portion of the first gate structure, the P-type source region, the P-type drain region, and a portion of the second gate structure;

[0028] forming an interlayer dielectric layer on the semiconductor substrate, and forming a contact-type conductive plug penetrating the N-type source region, the N-type drain region, the first gate structure, the P-type source region, the P-type drain region, and the second gate structure through the interlayer dielectric layer;

[0029] The suspended conductive plug is formed simultaneously with the contact conductive plug. The bottom of the suspended conductive plug rests on the upper surface of the silicide barrier layer. The radial dimension of the suspended conductive plug is greater than that of the contact conductive plug.

[0030] Optionally, the forming of a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, includes: forming a compressive stress material layer only on the dielectric layer on the PLDMOS region.

[0031] Optionally, forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, includes:

[0032] forming a dielectric material layer covering the semiconductor substrate, the first gate structure, and the second gate structure;

[0033] forming a compressive stress material layer covering the dielectric material layer;

[0034] forming a patterned mask layer on the compressive stress material layer, wherein the mask layer at least exposes the compressive stress material layer on the NLDMOS region, and removing the compressive stress material layer on the NLDMOS region using the mask layer as a mask, so that the remaining compressive stress material layer on the PLDMOS region at least covers the P-type drift region;

[0035] The mask layer is removed, and an additional dielectric material layer is formed on the dielectric material layer on the NLDMOS region, so that the total thickness of the dielectric material layer on the NLDMOS region and the additional dielectric material layer is greater than the thickness of the dielectric material layer on the PLDMOS region. The dielectric material layer on the NLDMOS region and the additional dielectric material layer together constitute the dielectric layer on the NLDMOS region, and the dielectric material layer on the PLDMOS region constitutes the dielectric layer on the PLDMOS region.

[0036] In the method for manufacturing an LDMOS integrated device of the present invention, a semiconductor substrate includes an NLDMOS region and a PLDMOS region. A dielectric layer over the NLDMOS region and a dielectric layer over the PLDMOS region are formed on the semiconductor substrate. A stress material layer is formed on the dielectric layer over the NLDMOS region and / or the dielectric layer over the PLDMOS region. A heat treatment is then performed to adjust the stress of the stress material layer, thereby improving the electron mobility of the NLDMOS device and / or the hole mobility of the PLDMOS device, thereby improving the performance of the LDMOS integrated device. Furthermore, the thickness of the dielectric layer over the NLDMOS region is greater than the thickness of the dielectric layer over the PLDMOS region. This ensures that the thickness of the dielectric layer under the big contact of the NLDMOS region meets its resurf requirements, and also ensures that the thickness of the dielectric layer under the big contact of the PLDMOS region meets its resurf requirements, thereby improving the resurf capability of the big contact of the LDMOS integrated device as a whole. In addition, the implantation conditions of the LDMOS integrated device can be readjusted based on the thickness of the dielectric layer on the NLDMOS region or the thickness of the dielectric layer on the PLDMOS region, thereby reducing the on-resistance of the LDMOS integrated device. This helps to further improve the performance of the PLDMOS device in the LDMOS integrated device, ultimately achieving the simultaneous fabrication of high-performance NLDMOS and high-performance PLDMOS in the same process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 FIG. 1 is a flow chart of a method for manufacturing an LDMOS integrated device according to an embodiment of the present invention.

[0038] Figures 2 to 5 The figure is a schematic cross-sectional view of a process for manufacturing an LDMOS integrated device using a method for manufacturing an LDMOS integrated device according to an embodiment of the present invention.

[0039] Explanation of the reference numerals: 10-semiconductor substrate; 100a-NLDMOS region; 100b-PLDMOS region; 101-N-type drain region; 102-N-type source region; 103-first gate structure; 104-P-type body region lead-out region; 105-P-type drain region; 106-P-type source region; 107-second gate structure; 108-N-type body region lead-out region; 109-dielectric material layer; 109a-dielectric layer on the NLDMOS region; 109b-dielectric layer on the PLDMOS region; 110-tensile stress material layer; 111-silicide barrier layer; 112-interlayer dielectric layer; 113a-suspended conductive plug; 113b-contact conductive plug; 114-metal silicide. DETAILED DESCRIPTION

[0040] The following is a detailed description of the method for fabricating an LDMOS integrated device according to the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0041] During the design and fabrication of LDMOS integrated devices, the inventors discovered that they could only adjust the process flow primarily based on NLDMOS before developing PLDMOS using the same process flow. This often only resulted in the NLDMOS being developed to its optimal characteristics, while the PLDMOS was not able to achieve the optimal characteristics.

[0042] In addition, the inventors have also discovered that RESURF (reduced surface electric field) technology is often used in the BCD process to reduce the surface electric field of the drift region of PLDMOS or NLDMOS to improve the withstand voltage performance of PLDMOS or NLDMOS. Among them, for the method of using Bigcontact (large contact hole, used to set the conductive plug) to reduce the surface electric field, the thickness of the dielectric layer under the Bigcontact determines the RESURF effect. To ensure that the RESURF effect is not affected, it is necessary to grow a layer of SIN after the SAB OX (silicide blocking oxide layer) as an etch barrier layer for the suspended Bigcontact. In other words, the bottom of the Bigcontact needs to hover on the SIN to prevent the dielectric layer under the Bigcontact from being over-etched, thereby enhancing the RESURF effect and improving the withstand voltage performance of the PLDMOS or NLDMOS.

[0043] However, the aforementioned introduction of SIN will have an additional impact on the device performance of PLDMOS or NLDMOS. This is because when the SIN is annealed, the change in SIN stress will produce a large (+5%) positive current gain for the NLDMOS, but a larger negative current gain (-10% or more, or even failure) for the corresponding PLDMOS current. In other words, during the LDMOS integrated device fabrication process, although the introduction of SIN improves the RESUR capability of the NLDMOS's big contact, and the use of SAB OX layers to apply stress to the wafer also improves NLDMOS performance, it will cause the performance of other devices (such as PLDMOS) to degrade and fail, and cannot meet the requirements of simultaneously fabricating high-performance NLDMOS and high-performance PLDMOS in actual process production.

[0044] In order to improve the performance of LDMOS integrated devices, enhance the resurf capability of the Bigcontact of the LDMOS integrated devices, and realize the simultaneous preparation of high-performance NLDMOS and high-performance PLDMOS, this embodiment provides a method for manufacturing an LDMOS integrated device.

[0045] Figure 1 The process of the method for manufacturing the LDMOS integrated device of this embodiment is shown as follows. Figure 1 As shown, the manufacturing method of the LDMOS integrated device includes:

[0046] S1. Provide a semiconductor substrate, the semiconductor substrate having an NLDMOS region and a PLDMOS region; the NLDMOS region having a P-type body region and an N-type drift region, an N-type source region formed on top of the P-type body region, an N-type drain region formed on top of the N-type drift region, and a first gate structure formed on the NLDMOS region; the PLDMOS region having an N-type body region and a P-type drift region formed on top of the N-type body region, a P-type source region formed on top of the P-type drift region, and a second gate structure formed on the PLDMOS region;

[0047] S2, forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, and forming a stress material layer on the dielectric layer on the NLDMOS region and / or the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region;

[0048] S3, performing heat treatment to adjust the stress of the stress material layer;

[0049] S4, removing the stress material layer.

[0050] Figures 2 to 5 The following is a schematic cross-sectional view of the process of manufacturing an LDMOS integrated device using the manufacturing method of an LDMOS integrated device according to an embodiment of the present invention. Figures 1 to 5 The manufacturing method of the LDMOS integrated device of this embodiment is described.

[0051] like Figure 2 The semiconductor substrate 10 may be a silicon substrate. However, the semiconductor substrate 10 is not limited thereto and may also be a germanium substrate, a silicon-germanium substrate, or a silicon-on-insulator substrate. In this embodiment, the semiconductor substrate 10 is a P-type substrate. In other embodiments, the semiconductor substrate 10 may be an N-type substrate.

[0052] The semiconductor substrate 10 has an NLDMOS region 100 a and a PLDMOS region 100 b . The NLDMOS region 100 a can be used to form an NLDMOS device, and the PLDMOS region 100 b can be used to form a PLDMOS device.

[0053] A P-type body region (Pbody) and an N-type drift region (N-Drift-Area) are formed in the NLDMOS region 100a. An N-type source region 102 is formed on the top of the P-type body region, and an N-type drain region 101 is formed on the top of the N-type drift region. A first gate structure 103 is formed on the NLDMOS region 100a. The first gate structure 103 is formed at least on the upper surface of the semiconductor substrate between the N-type source region 102 and the N-type drift region. The N-type source region 102 can extend laterally below the first gate structure 103. In this embodiment, the N-type drift region surrounds the P-type body region. In other embodiments, the P-type body region and the N-type drift region are adjacent. In other embodiments, the P-type body region and the N-type drift region are spaced apart.

[0054] The PLDMOS region 100b includes an N-type body region (Nbody) and a P-type drift region (P-Drift-Area). A P-type source region 106 is formed on top of the N-type body region, and a P-type drain region 105 is formed on top of the P-type drift region. A second gate structure 107 is formed on the PLDMOS region 100b. The second gate structure 107 is formed at least on the upper surface of the semiconductor substrate between the P-type source region 106 and the P-type drift region. The P-type source region 106 may extend laterally below the second gate structure 107. In this embodiment, the P-type drift region surrounds the N-type body region. In other embodiments, the P-type body region and the N-type drift region are adjacent. In other embodiments, the N-type body region and the P-type drift region are spaced apart.

[0055] like Figure 2 As shown, a P-type body region lead-out region 104 may be further formed on the top of the P-type body region. The P-type body region lead-out region 104 is located on a side of the N-type source region 102 away from the first gate structure 103, and the doping concentration of the P-type body region lead-out region 104 is greater than the doping concentration of the P-type body region. An N-type body region lead-out region 108 may also be formed on the top of the N-type body region. The N-type body region lead-out region 108 is located on a side of the P-type drain region 106 away from the second gate structure 107, and the doping concentration of the N-type body region lead-out region 108 is greater than the doping concentration of the N-type body region.

[0056] refer to Figure 2The NLDMOS region 100a and the PLDMOS region 100b may be isolated from each other by an isolation structure 11. The isolation structure 11 may be a shallow trench isolation (STI), a junction isolation, or a local oxide of silicon isolation (LOCOS).

[0057] In one embodiment, in step S2, the tensile stress material layer may be formed only on the dielectric layer above the NLDMOS region. The following description will take "step S2, forming the tensile stress material layer only on the dielectric layer above the NLDMOS region" as an example.

[0058] refer to Figures 2 to 3 , step S2 may include sub-steps S21 to S24.

[0059] Sub-step S21, such as Figure 2 As shown, a dielectric material layer 109 is formed to cover the semiconductor substrate 10 , the first gate structure 103 , and the second gate structure 107 .

[0060] The dielectric material layer 109 may be made of silicon oxide and may have a thickness of 1000 angstroms to 1800 angstroms, but is not limited thereto. The thickness of the dielectric material layer 109 may be adjusted according to the actual conditions of the NLDMOS device.

[0061] Sub-step S22, such as Figure 2 As shown, a tensile stress material layer 110 is formed to cover the dielectric material layer 109 .

[0062] The material of the tensile stress material layer 110 may include at least one of silicon nitride and silicon oxynitride. The thickness of the tensile stress material layer 110 may be 150 angstroms to 600 angstroms. However, this is not limiting. The thickness of the tensile stress material layer 110 may be adjusted according to the actual situation of the NLDMOS device.

[0063] Sub-step S23, such as Figure 3 As shown, a patterned first mask layer (not shown in the figure) is formed on the tensile stress material layer 110, and the first mask layer at least exposes the tensile stress material layer on the PLDMOS region 100b. The tensile stress material layer on the PLDMOS region 100b is removed using the first mask layer as a mask, and the remaining tensile stress material layer on the NLDMOS region 100a at least covers the N-type drift region.

[0064] In one embodiment, in step S23, the remaining tensile stress material layer on the NLDMOS region 100a can extend from the N-type source region 102 through the first gate structure 103 to cover the N-type drain region 101. In this way, when a subsequent heat treatment is performed, the remaining tensile stress material layer 110 can apply tensile stress to both the N-channel region (located below the first gate structure 103) and the N-type drift region of the NLDMOS device, thereby improving the electron mobility of the N-type drift region and the N-channel region of the NLDMOS device, helping to reduce the on-resistance of the NLDMOS device without reducing the off-state breakdown voltage, improve the saturation current capability of the NLDMOS device, and improve the performance of the NLDMOS device.

[0065] Sub-step S24, such as Figure 3 As shown, based on the first mask layer, the first mask layer at least exposes the dielectric material layer on the PLDMOS region 100b, and a portion of the dielectric material layer is etched away, so that the thickness of at least the dielectric material layer on the N-type drift region in the NLDMOS region 100a is greater than the thickness of the remaining dielectric material layer on the PLDMOS region 100b. The remaining dielectric material layer on the NLDMOS region 100a is the dielectric layer 109a on the NLDMOS region, and the remaining dielectric material layer on the PLDMOS region 100b is the dielectric layer 109b on the PLDMOS region.

[0066] It should be noted that when the first mask layer only covers the N-type drift region and exposes other areas of the NLDMOS region, when the dielectric material layer 109 is etched based on the first mask layer, part of the dielectric material layer in the NLDMOS region 100a that is not covered by the first mask layer will also be etched and removed.

[0067] In steps S23 and S24, only a single photolithography process (using the first mask layer as a mask) and a corresponding single etching process are used to retain the tensile stress material layer on the NLDMOS region 100a and remove the tensile stress material layer on the PLDMOS region 100b. This improves the electron mobility of the NLDMOS while not negatively impacting the device performance of the PLDMOS. Simultaneously, the same first mask layer is used to etch away a portion of the dielectric material layer on the PLDMOS region 100b, ensuring that the thickness of the dielectric layer 109a on the NLDMOS region is greater than the thickness of the dielectric layer 109b on the PLDMOS region. This ensures that the dielectric layer thickness under the big contact of the NLDMOS region and the dielectric layer thickness under the big contact of the PLDMOS region both meet their respective RESURF requirements. In other words, the dielectric layer thickness under the big contact of the NLDMOS region and the dielectric layer thickness under the big contact of the PLDMOS region both meet their respective RESURF requirements.

[0068] In existing LDMOS integrated device fabrication processes, if both the resurf capability of the LDMOS integrated device's Big Contact and the performance of both NLDMOS and PLDMOS devices are to be improved, NLDMOS and PLDMOS need to be fabricated separately. This requires two additional photolithography and etching processes: one photolithography and one etching for the NLDMOS's SiN, and one photolithography and one etching for the PLDMOS's SiN. In steps S23 and S24 of this embodiment, only one additional photolithography and etching process is required, which improves both the resurf capability of the LDMOS integrated device's Big Contact and the performance of both NLDMOS and PLDMOS devices.

[0069] Furthermore, because the thickness of the dielectric layer 109 a on the NLDMOS region is greater than the thickness of the dielectric layer 109 b on the PLDMOS region, the implantation conditions of the PLDMOS device can be readjusted (for example, the doping concentration of the P-type drift region in the PLDMOS device can be appropriately increased), thereby reducing the on-resistance of the PLDMOS device and improving the performance of the PLDMOS device. This helps to simultaneously improve the performance of both the NLDMOS device and the PLDMOS device.

[0070] In one embodiment, an over-etching process can be used to partially remove the thickness of the dielectric material layer 109 on the PLDMOS region 100 b, such that the thickness of the dielectric layer 109 b on the PLDMOS region is less than the thickness of the dielectric layer 109 a on the NLDMOS region. The over-etching process can be implemented by running an OVER ETCH program in an etching machine. For example, the thickness of the dielectric material layer 109 removed from the PLDMOS region 100 b can be controlled by adjusting the over-etching time. In other embodiments, other etching methods known in the art can be used to partially remove the thickness of the dielectric material layer 109.

[0071] In one embodiment, the thickness of the dielectric layer 109b on the PLDMOS region is 600 angstroms to 1200 angstroms, but the present invention is not limited thereto. The remaining thickness of the dielectric layer 109b on the PLDMOS region can be adjusted according to the actual conditions of the PLDMOS device.

[0072] After step S24, the first mask layer on the tensile stress material layer 110 may be removed. In this embodiment, the first mask layer may be removed using a process for removing a mask known in the art.

[0073] Next, step S3 is performed, including performing a thermal treatment to adjust the stress of the remaining tensile stress material layer 110 to improve the electron mobility of the NLDMOS device.

[0074] In this embodiment, the heat treatment process may be a rapid thermal processing (RTA) process or a laser annealing process, but is not limited thereto. Other heat treatment processes known in the art may also be used to heat treat the tensile stress material layer 110 (or the semiconductor substrate 10).

[0075] like Figure 4 As shown, step S4 may include: removing the tensile stress material layer 110. In this embodiment, a wet etching process or a dry etching process may be used to remove the tensile stress material layer 110.

[0076] In another embodiment, in step S2 , the compressive stress material layer may be formed only on the dielectric layer above the PLDMOS region. Step S2 may specifically include: forming a dielectric material layer covering the semiconductor substrate 10, the first gate structure 103, and the second gate structure 107; forming a compressive stress material layer covering the dielectric material layer; forming a patterned second mask layer on the compressive stress material layer, wherein the second mask layer at least exposes the compressive stress material layer on the NLDMOS region 100 a; removing the compressive stress material layer on the NLDMOS region 100 a using the second mask layer as a mask, so that the remaining compressive stress material layer on the PLDMOS region 100 b at least covers the P-type drift region; removing the second mask layer, and forming an additional dielectric material layer on the dielectric material layer on the NLDMOS region 100 a, such that the total thickness of the dielectric material layer on the NLDMOS region 100 a and the additional dielectric material layer is greater than the thickness of the dielectric material layer on the PLDMOS region 100 b, and the dielectric material layer on the NLDMOS region 100 a and the additional dielectric material layer together constitute the dielectric layer on the NLDMOS region, and the dielectric material layer on the PLDMOS region constitutes the dielectric layer on the PLDMOS region.

[0077] In this manner, the subsequent compressive stress material layer on the PLDMOS region 100b can at least apply compressive stress to the P-type drift region, helping to improve the hole mobility of the PLDMOS device without negatively impacting the performance of the NLDMOS device, thereby enhancing the performance of the LDMOS integrated device. Simultaneously, the thickness of the dielectric layer on the NLDMOS region can be greater than that on the PLDMOS region, ensuring that the dielectric layer thickness under the Big Contact of the NLDMOS region and the dielectric layer thickness under the Big Contact of the PLDMOS region both meet their respective RESURF requirements, thereby overall improving the RESURF capability of the Big Contact of the LDMOS integrated device. Furthermore, by adjusting the implantation conditions of the PLDMOS device, the on-resistance of the PLDMOS device can be reduced, further improving the performance of the PLDMOS device in the LDMOS integrated device. In this embodiment, step S3 may include performing a heat treatment to adjust the stress of the compressive stress material layer. Step S4 may include removing the compressive stress material layer.

[0078] After step S4 , the method for manufacturing the LDMOS integrated device may further include steps S5 to S6 .

[0079] Step S5 , patterning the dielectric layer 109 a on the NLDMOS region and the dielectric layer 109 b on the PLDMOS region to expose the N-type source region 102 , the N-type drain region 101 , a portion of the first gate structure 103 , the P-type source region 106 , the P-type drain region 105 , and a portion of the second gate structure 107 .

[0080] Step S6, as Figure 5 As shown, a suspended conductive plug 113a is formed above the P-type drift region and / or the N-type drift region, and the bottom of the suspended conductive plug 113 stays above the P-type drift region and / or the N-type drift region, and is spaced a preset distance from the upper surface of the P-type drift region and / or the N-type drift region.

[0081] After step S5 and before step S6, the method for manufacturing the LDMOS integrated device may further include: Figure 5 As shown, a silicide blocking layer 111 is formed on the patterned dielectric layer 109a on the NLDMOS region and on the dielectric layer 109b on the PLDMOS region, that is, a silicide blocking layer 111 is formed on the dielectric layer 109a on the remaining NLDMOS region and on the dielectric layer 109b on the remaining PLDMOS region; and a metal silicide layer 114 is formed on the upper surfaces of the exposed N-type source region 102, the N-type drain region 101, a portion of the first gate structure 103, the P-type source region 106, the P-type drain region 105, and a portion of the second gate structure 107. Figure 5 Only a portion of the metal silicide layer 114 is shown); an interlayer dielectric layer 112 is formed on the semiconductor substrate 10, and a contact-type conductive plug 113b is formed that penetrates the interlayer dielectric layer 112 and includes the N-type source region 102, the N-type drain region 101, the first gate structure 103, the P-type source region 106, the P-type drain region 105, and the second gate structure 107.

[0082] The suspended conductive plug 113a is formed while the contact conductive plug 113b is formed. The bottom of the suspended conductive plug 113a stays on the upper surface of the silicide blocking layer 111. The radial dimension of the suspended conductive plug 113a is larger than that of the contact conductive plug 113b.

[0083] The thickness of the silicide blocking layer 111 may be 200 angstroms to 300 angstroms, but is not limited thereto. The thickness of the silicide blocking layer 111 may be adjusted as needed. The material of the interlayer dielectric layer 112 may include silicon oxide.

[0084] It should be noted that the suspended conductive plug 113a can be referred to as a field plate (FP), which can be used to reduce the surface electric field of the N-type drift region and / or the P-type drift region. The radial dimensions of the suspended conductive plug 113a are larger than those of the contact-type conductive plug 113b, and the thickness of the dielectric layer 109b on the PLDMOS region is thinner than the dielectric layer 109a on the NLDMOS region. This effectively reduces the surface electric field of the N-type drift region and the P-type drift region, thereby improving the performance of both the NLDMOS and PLDMOS devices. Furthermore, by adjusting the implantation conditions of the P-type drift region of the PLDMOS device, the performance of the PLDMOS device can be further improved.

[0085] The contact-type conductive plug 113 b and the hovering-type conductive plug 113 a can be made of metal materials such as tungsten or aluminum, or metal alloys.

[0086] In the method for manufacturing an LDMOS integrated device of the present invention, a semiconductor substrate 10 includes an NLDMOS region 100a and a PLDMOS region 100b. A dielectric layer 109a on the NLDMOS region and a dielectric layer 109b on the PLDMOS region are formed on the semiconductor substrate 10. A stress material layer is formed on the dielectric layer 109a on the NLDMOS region and / or the dielectric layer 109b on the PLDMOS region. A heat treatment is then performed to adjust the stress of the stress material layer. This can improve the electron mobility of the NLDMOS device and / or the hole mobility of the PLDMOS device, thereby improving the performance of the LDMOS integrated device. Furthermore, the thickness of the dielectric layer 109a on the NLDMOS region is greater than the thickness of the dielectric layer 109b on the PLDMOS region. This ensures that the thickness of the dielectric layer under the Big Contact of the NLDMOS region meets the RESURF requirement, and also ensures that the thickness of the dielectric layer under the Big Contact of the PLDMOS region meets the RESURF requirement, thereby improving the Big Contact of the LDMOS integrated device as a whole. Furthermore, the thickness of the dielectric layer 109a on the NLDMOS region or the thickness of the dielectric layer 109b on the PLDMOS region can be adjusted to adjust the injection conditions of the PLDMOS device, thereby reducing the on-resistance of the LDMOS integrated device. This helps to further improve the performance of the PLDMOS device in the LDMOS integrated device, and ultimately achieves the simultaneous preparation of high-performance NLDMOS and high-performance PLDMOS in the same process flow.

[0087] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing an LDMOS integrated device, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate has an NLDMOS region and a PLDMOS region; A P-type body region and an N-type drift region are formed in the NLDMOS region, an N-type source region is formed on the top of the P-type body region, an N-type drain region is formed on the top of the N-type drift region, and a first gate structure is formed on the NLDMOS region; an N-type body region and a P-type drift region are formed in the PLDMOS region, a P-type source region is formed on the top of the N-type body region, a P-type drain region is formed on the top of the P-type drift region, and a second gate structure is formed on the PLDMOS region; forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, and forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region; performing a heat treatment to adjust the stress of the stress material layer; The stressed material layer is removed.

2. The production method according to claim 1, wherein: The step of forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, includes forming a tensile stress material layer only on the dielectric layer on the NLDMOS region.

3. The production method according to claim 2, characterized in that The method of forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, comprises: forming a dielectric material layer covering the semiconductor substrate, the first gate structure, and the second gate structure; forming a tensile stress material layer covering the dielectric material layer; forming a patterned mask layer on the tensile stress material layer, wherein the mask layer at least exposes the tensile stress material layer on the PLDMOS region, and removing the tensile stress material layer on the PLDMOS region using the mask layer as a mask, so that the remaining tensile stress material layer on the NLDMOS region at least covers the N-type drift region; Continuing with the mask layer, the mask layer at least exposes the dielectric material layer on the PLDMOS region, and etching away a portion of the dielectric material layer, so that the thickness of at least the dielectric material layer on the N-type drift region in the NLDMOS region is greater than the thickness of the remaining dielectric material layer on the PLDMOS region, the remaining dielectric material layer on the NLDMOS region being the dielectric layer on the NLDMOS region, and the remaining dielectric material layer on the PLDMOS region being the dielectric layer on the PLDMOS region.

4. The production method according to claim 3, wherein: The method further comprises forming a patterned mask layer on the tensile stress material layer, wherein the mask layer at least exposes the tensile stress material layer on the PLDMOS region, and removing the tensile stress material layer on the PLDMOS region using the mask layer as a mask, wherein the remaining tensile stress material layer on the NLDMOS region at least covers the N-type drift region. The remaining tensile stress material layer on the NLDMOS region further extends from the N-type source region through the first gate structure to cover the N-type drain region.

5. The production method according to claim 2 or 3, characterized in that: The thickness of the dielectric layer on the PLDMOS region is 600 angstroms to 1200 angstroms.

6. The production method according to claim 3, wherein: The thickness of the dielectric material layer is 1000 angstroms to 1800 angstroms.

7. The production method according to claim 2 or 3, characterized in that: The thickness of the tensile stress material layer is 150 angstroms to 600 angstroms.

8. The production method according to claim 1, wherein: After removing the stress material layer, the method further comprises: Patterning the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region to expose the N-type source region, the N-type drain region, a portion of the first gate structure, the P-type source region, the P-type drain region, and a portion of the second gate structure; A suspended conductive plug is formed above the P-type drift region and / or the N-type drift region, wherein the bottom of the suspended conductive plug stays above the P-type drift region and / or the N-type drift region and is spaced a preset distance from the upper surface of the P-type drift region and / or the N-type drift region.

9. The production method according to claim 8, characterized in that: After patterning the dielectric layer on the NLDMOS region and the dielectric layer on the PLDMOS region to expose the N-type source region, the N-type drain region, a portion of the first gate structure, the P-type source region, the P-type drain region, and a portion of the second gate structure, Before forming a suspended conductive plug above the P-type drift region and / or the N-type drift region, the method further comprises: forming a silicide blocking layer on the patterned dielectric layer on the NLDMOS region and on the dielectric layer on the PLDMOS region; forming a metal silicide layer on the upper surfaces of the exposed N-type source region, the N-type drain region, a portion of the first gate structure, the P-type source region, the P-type drain region, and a portion of the second gate structure; forming an interlayer dielectric layer on the semiconductor substrate, and forming a contact-type conductive plug penetrating the N-type source region, the N-type drain region, the first gate structure, the P-type source region, the P-type drain region, and the second gate structure through the interlayer dielectric layer; The suspended conductive plug is formed simultaneously with the contact conductive plug. The bottom of the suspended conductive plug rests on the upper surface of the silicide barrier layer. The radial dimension of the suspended conductive plug is greater than that of the contact conductive plug.

10. The production method according to claim 1, wherein: The step of forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, includes forming a compressive stress material layer only on the dielectric layer on the PLDMOS region.

11. The production method according to claim 10, characterized in that: The method of forming a dielectric layer on the NLDMOS region and a dielectric layer on the PLDMOS region on the semiconductor substrate, forming a stress material layer on the dielectric layer on the NLDMOS region and / or on the dielectric layer on the PLDMOS region, wherein the thickness of the dielectric layer on the NLDMOS region is greater than the thickness of the dielectric layer on the PLDMOS region, comprises: forming a dielectric material layer covering the semiconductor substrate, the first gate structure, and the second gate structure; forming a compressive stress material layer covering the dielectric material layer; forming a patterned mask layer on the compressive stress material layer, wherein the mask layer at least exposes the compressive stress material layer on the NLDMOS region, and removing the compressive stress material layer on the NLDMOS region using the mask layer as a mask, so that the remaining compressive stress material layer on the PLDMOS region at least covers the P-type drift region; The mask layer is removed, and an additional dielectric material layer is formed on the dielectric material layer on the NLDMOS region, so that the total thickness of the dielectric material layer on the NLDMOS region and the additional dielectric material layer is greater than the thickness of the dielectric material layer on the PLDMOS region. The dielectric material layer on the NLDMOS region and the additional dielectric material layer together constitute the dielectric layer on the NLDMOS region, and the dielectric material layer on the PLDMOS region constitutes the dielectric layer on the PLDMOS region.

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