Orthogonal downconversion method for digital intermediate frequency signals

Abstract

This invention discloses an orthogonal down-conversion method for digital intermediate frequency (IF) signals, primarily addressing the problem of high computational complexity in existing orthogonal digital down-conversion processing methods. The implementation involves decimation and mixing / filtering of the digital IF signal. Decimation occurs every three clock cycles, extracting one-quarter of the digital IF signal. Mixing / filtering involves multiplying the convolution coefficient sequence of a low-pass filter with the sine and cosine local oscillator signals generated by a numerically controlled oscillator (CNC) to obtain the convolution coefficient sequences of the I-path and Q-path filters. These sequences are then convolved with the decimated digital IF signal sequence and summed to obtain the I-path zero-IF signal and Q-path zero-IF signal, which are then transmitted to other signal processing modules in the FPAG system. This invention reduces the computational complexity of orthogonal down-conversion, lowers hardware resource consumption, and can be applied to general radar signal processing systems.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology, specifically relating to a signal orthogonal downconversion method that can be used to process radar intermediate frequency signals. Background Technology

[0002] Digital mixing is a key technology in radar systems. Quadrature digital down-conversion (QDC) is a common type of digital mixing process. QDC can obtain two quadrature zero-IF signals by mixing and decimating the digital intermediate frequency (IF) signal.

[0003] Figure 1 The traditional quadrature digital downconversion processing method is demonstrated, and its processing procedure is as follows:

[0004] First, the sinusoidal local oscillator signal generated by the locally controlled oscillator. Sum of cosine local oscillator signal Multiplying each signal by the intermediate frequency signal IF(n) yields the quadrature mixed I(n) and Q(n) signals, where f s The sampling rate of the intermediate frequency (IF) signal is represented by f0, the frequency of the IF signal is represented by n, and the total number of IF signals is represented by n. This represents the multiplication operation; then, for I(n) respectively... pre Signal and Q(n) pre The signal undergoes FIR filtering to obtain the filtered I(n)' and Q(n)' signals. Finally, the I(n)' and Q(n)' signals are downsampled and decimated to obtain the decimated I-channel zero-IF signal and Q-channel zero-IF signal. The downsampling is typically performed by selecting 1 from 2, retaining either odd-numbered terms or twice the number of even-numbered terms. This traditional quadrature digital downconversion method requires filtering for each intermediate frequency signal after mixing, which not only necessitates significant multiplier hardware resources but also increases the dynamic power consumption of the digital circuitry.

[0005] Patent application CN 104393841A discloses a method for implementing quadrature downconversion of digital intermediate frequency (IF) signals. This method performs a quarter-downconversion on the input IF signal's I and Q channels, then filters one of the downconverted I and Q channels, digitally delays the other, and finally performs downsampling. While this method reduces the number of filters used, the computational complexity of the quadrature digital downconversion process remains significant.

[0006] Therefore, when using FPGAs to implement quadrature digital downconversion processing, reducing the hardware resources and computational load of digital mixing processing has become an urgent technical problem to be solved. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of the prior art by proposing an orthogonal downconversion method for digital intermediate frequency signals, thereby reducing the computational load of digital mixing and lowering hardware resource consumption.

[0008] To achieve the above objectives, the orthogonal down-conversion method for digital intermediate frequency signals of the present invention includes two steps: decimation and filtering, characterized in that:

[0009] The extraction process involves extracting data every three clock cycles, specifically extracting 1 / 4 of the intermediate frequency signal IF(n) to obtain the second digital intermediate frequency signal sequence IF(n). pre ={S1,S2,S3,…,S i ,…,S n}, where i = 1, 2, ..., n, n is the total number of intermediate frequency signal sequences, taking integer values ​​that are multiples of 4, and S i This represents the i-th intermediate frequency signal in the second digital intermediate frequency signal sequence;

[0010] The filtering is implemented as follows:

[0011] Obtain the convolution coefficient sequence x1,x2,x3,…,x of the I-path filter. i ,…,x n The convolution coefficient sequence y1, y2, y3, ..., y of the Q-path filter i ,…,y n ,in,

[0012] The second digital intermediate frequency signal sequence S1, S2, S3, ..., S i ,…,S n Convolve the polynomials with the convolution coefficient sequences of the I-path filter and the Q-path filter respectively to obtain the I0-path polynomial and the Q0-path polynomial.

[0013] By combining like terms in the I0-way polynomial and the Q0-way polynomial respectively, we obtain two simplified sets of polynomials, I1 and Q1:

[0014] The monomials in the simplified I1-way polynomial and Q1-way polynomial are convolved, and the results of the convolution are summed to obtain the I-way zero intermediate frequency signal and the Q-way zero intermediate frequency signal.

[0015] Compared with the prior art, the present invention has the following advantages:

[0016] In the extraction process, this invention reduces the total amount of intermediate frequency signal that needs to be filtered by extracting only 1 / 4 of the intermediate frequency signal data. At the same time, in the filtering process, since the intermediate frequency signal sequence and the filter convolution coefficient sequence are first merged with similar terms and then convolved, half of the multipliers are used. The total number of multipliers used is only 1 / 8 of the total number used in the traditional method, which effectively reduces the computational load of digital mixing and filtering processing and saves resources. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a traditional quadrature digital downconversion processing method.

[0018] Figure 2 This is a schematic diagram of the orthogonal downconversion method for digital intermediate frequency signals according to the present invention.

[0019] Figure 3 This is a schematic diagram of signal extraction in this invention. Detailed Implementation

[0020] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings:

[0021] Digital downconversion technology is a key technology in radar general signal systems. In radar general signal systems, the front-end radio frequency system receives radio frequency signals, performs analog mixing and filtering of the radio frequency signals to obtain intermediate frequency signals, the AD converter samples the intermediate frequency signals to obtain bandwidth digital intermediate frequency signals, and the front-end radio frequency system sends the digital intermediate frequency signals to the FPGA signal processing system.

[0022] In order to obtain a low-speed zero-IF signal, the FPGA signal processing system needs to first perform digital down-conversion processing on the digital intermediate frequency signal, down-converting the digital intermediate frequency signal to a digital zero-IF signal and reducing the sampling rate of the digital signal.

[0023] Reference Figure 2 The quadrature downconversion of the digital intermediate frequency signal in this example includes decimation and mixing filtering of the digital intermediate frequency signal. The specific implementation steps are as follows:

[0024] Step 1: Extract the digital intermediate frequency signal.

[0025] To reduce the total amount of digital intermediate frequency (IF) signal during the mixing and filtering process and to reduce the computational load of the mixing and filtering, it is necessary to first extract the digital IF signal.

[0026] Reference Figure 3 In this example, the digital intermediate frequency (IF) signal IF(n) is decimated every three clock cycles, with the decimated data being 1 / 4 of the IF signal. The resulting decimated digital IF signal sequence is as follows:

[0027] IF(n)′={S1,S2,S3,…,Si ,…,S n},

[0028] Among them, S i This represents the i-th intermediate frequency signal in the extracted digital intermediate frequency signal sequence, where i = 1, 2, ..., n, and n is the total number of intermediate frequency signal sequences, taking integer values ​​that are multiples of 4.

[0029] Step 2: Perform mixing and filtering on the extracted digital intermediate frequency signal.

[0030] To obtain the I and Q channels containing harmonics after filtering out high-frequency signals, the decimated digital intermediate frequency (IF) signal needs to be mixed and filtered. In this example, the convolution coefficient sequence of the low-pass filter is first multiplied by the sine and cosine local oscillator signals generated by the numerically controlled oscillator to generate the convolution coefficient sequences of the I and Q channels. Then, the convolution coefficient sequences of the I and Q channels are convolved with the decimated IF signal sequence and summed to complete the mixing and filtering of the decimated IF signal. The specific filtering and mixing process is as follows:

[0031] 2.1) Obtain the convolution coefficient sequences of the I-path and Q-path filters:

[0032] A sinusoidal local oscillator signal is generated by a local numerically controlled oscillator. Sum of cosine local oscillator signal Among them, f s f0 represents the sampling rate of the intermediate frequency signal, and i = 1, 2, ..., n;

[0033] The sampling rate of the intermediate frequency (IF) signal is set to four times the IF signal frequency. A 45° phase transformation is performed on both the sinusoidal and cosine local oscillator signals, and their amplitudes are amplified. This yields a sinusoidal local oscillator signal. Sum of cosine local oscillator signal

[0034] Substitute the variables i, which take values ​​of 1, 2, 3, ..., n, into the formula. The sinusoidal local oscillator signal sequence 1,1,-1,-1,…,1,1,-1,-1 was calculated.

[0035] Substitute the variables i, which take values ​​of 1, 2, 3, ..., n, into the formula. The cosine local oscillator signal sequence is calculated to be -1,1,1,-1,…,-1,1,1,-1;

[0036] Let the convolution coefficient sequence of the low-pass filter be w1, w2, w3, ..., w i ,…,w n Among them, the convolution coefficient sequence of the low-pass filter has symmetry, i.e., wi =w n-i+1 ;

[0037] Multiplying the convolution coefficient sequence of the low-pass filter with the sinusoidal local oscillator signal sequence 1,1,-1,-1,…,1,1,-1,-1, yields the convolution coefficient sequence x1,x2,x3,…,x of the I-path filter. i ,…,x n ,

[0038] in, This represents the i-th element in the convolution coefficient sequence of the I-path filter;

[0039] Multiplying the convolution coefficient sequence of the low-pass filter with the cosine local oscillator signal sequence -1,1,1,-1,…-1,1,1,-1, yields the convolution coefficient sequence y1,y2,y3,…,y of the Q-path filter. i ,…,y n ,

[0040] in, This represents the i-th element in the convolution coefficient sequence of the Q-path filter;

[0041] 2.2) Construct the I-path polynomial I0 and the Q-path polynomial Q0 using the convolution coefficient sequences of the I-path and Q-path filters:

[0042] The extracted digital intermediate frequency signals S1, S2, S3, ..., S i ,…,S n Convolve the sequences of convolution coefficients of the I-path filter and the Q-path filter respectively to obtain the I-path polynomial I0 and the Q-path polynomial Q0:

[0043] I0 = S1*x1 + S2*x2 + S3*x3 + ... + S i *x i +…+S n *x n

[0044] Q0 = S1*y1 + S2*y2 + S3*y3 + ... + S i *y i +…+S n *y n

[0045] Where * represents convolution operation;

[0046] 2.3) Combine like terms in the polynomials I0 and Q0 respectively to obtain the polynomial I1 simplified by I-path and the polynomial Q1 simplified by Q-path:

[0047] I1 = F1*a1 + F2*a2 + F3*a3 + ... + F j *aj +…+F (n / 2) *a (n / 2)

[0048] Q1 = F1*b1 + F2*b2 + F3*b3 + ... + F j *b j +…+F (n / 2) *b (n / 2)

[0049] in, F j =S i ±S n-i+1 ,j=1,2,...,(n / 2),i=1,2,...,n,F j Represents the coefficient of the j-th monomial in polynomials I1 and Q1;

[0050] 2.4) Perform convolution operations on the monomials in the simplified polynomials I1 and Q1 respectively, and sum the results of the convolution operations to obtain the I-channel zero intermediate frequency signal and the Q-channel zero intermediate frequency signal.

[0051] In target detection applications, the processing system uses an FPGA to perform the above steps to digitally downconvert the digital intermediate frequency signal, obtaining an I-channel zero intermediate frequency signal and a Q-channel zero intermediate frequency signal, which are then provided to other signal processing modules in the FPGA system. The other signal processing modules process the I-channel and Q-channel zero intermediate frequency signals to obtain digital baseband signals, which are then sent to the DSP digital signal processing system. The DSP digital signal processing system processes the received digital baseband signals and sends them to the host computer to obtain information such as the position and velocity of the detected target, thus completing the target detection.

[0052] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and details without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A quadrature downconversion method for digital intermediate frequency signals, comprising decimation and mixing filtering, characterized in that: The extraction refers to extracting the intermediate frequency signal every three clock cycles. One-quarter of the data is used to obtain the extracted digital intermediate frequency signal sequence. Where i = 1, 2, ..., n, n is the total number of intermediate frequency signal sequences, taking integer values ​​that are multiples of 4, and S i This represents the i-th intermediate frequency signal in the extracted digital intermediate frequency signal sequence; The mixing and filtering is implemented as follows: Obtain the convolution coefficient sequence x1, x2, x3 of the I-path filter. ,x i , ,x n The convolution coefficient sequence y1, y2, y3 of the Q-path filter ,y i , ,y n ,in, ; This indicates the sampling rate of the intermediate frequency signal. Indicates the frequency of the intermediate frequency signal; Represents the convolution coefficients of the i-th low-pass filter; The extracted digital intermediate frequency signal sequences S1, S2, S3 ,S i , ,S n Convolve the polynomials I0 and Q0 respectively with the convolution coefficient sequences of the I-path filter and the Q-path filter to obtain the I-path polynomial I0 and the Q-path polynomial Q0. By combining like terms in the I-way polynomial I0 and the Q-way polynomial Q0 respectively, we obtain the simplified I-way polynomial I1 and the Q-way polynomial Q1, which are expressed as follows: I1= F1*a1+F2*a2+F3*a3+…+F j *a j +…+F (n / 2) *a (n / 2) ； Q1=F1*b1+F2*b2+F3*b3+…+F j *b j +…+F (n / 2) *b (n / 2) ； in, , , , j = 1,2,...,(n / 2), i=1,2,...,n, Represents the coefficient of the j-th monomial in polynomials I1 and Q1, and * represents the convolution operation; The monomials in the simplified I-channel polynomial I1 and Q-channel polynomial Q1 are convolved, and the results of the convolution operations are summed to obtain the I-channel zero intermediate frequency signal and the Q-channel zero intermediate frequency signal.

2. The method according to claim 1, characterized in that: The convolution coefficient sequence x1, x2, x3, ..., x of the I-path filter is obtained. i ,…,x n The convolution coefficient sequence y1, y2, y3, ..., y of the Q-path filter i ,…,y n The implementation is as follows: A local numerically controlled oscillator generates a sinusoidal local oscillator signal. Sum and cosine local oscillator signal ; The sampling rate of the intermediate frequency (IF) signal is set to four times the IF signal frequency. A 45° phase transformation is performed on both the sinusoidal and cosine local oscillator signals, and their amplitudes are amplified. This yields a sinusoidal local oscillator signal. Sum and cosine local oscillator signal ; Substitute the variables i, which take values ​​of 1, 2, 3, ..., n, into the formula. The sinusoidal local oscillator signal sequence was calculated. ; Substitute the variables i, which take values ​​of 1, 2, 3, ..., n, into the formula. The cosine local oscillator signal sequence was calculated. ; Let the convolution coefficient sequence of the low-pass filter be w1, w2, w3, ,w i , ,w n Among them, the convolution coefficient sequence of the low-pass filter has symmetry, i.e., w i= w n-i+1 ; The convolution coefficient sequence of the low-pass filter is combined with the sinusoidal local oscillator signal sequence. Multiplying them yields the convolution coefficient sequence x1, x2, x3 of the I-path filter. ,x i , ,x n ; The convolution coefficient sequence of the low-pass filter is combined with the cosine local oscillator signal sequence. Multiplying these results in the convolution coefficient sequence y1, y2, y3 of the Q-path filter. ,y i , ,y n ; Where, x i y represents the i-th element in the convolution coefficient sequence of the I-path filter. i This represents the i-th element in the convolution coefficient sequence of the Q-path filter.

3. The method according to claim 1, characterized in that: The polynomials I0 and Q0 are respectively represented as follows: I0= S1*x1+S2*x2+S3*x3+…+S i *x i +…+S n *x n ； Q0 = S1*y1+S2*y2+S3*y3+…+S i *y i +…+S n *y n ； Where i = 1, 2, ..., n, and * represents convolution operation.

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