Neural network measurement calibration system and method for TDL-TDC

Abstract

The present invention discloses a neural network measurement and calibration system and method for TDL-TDC, the system comprising: a TDL-TDC module, which uses a code density calibration method to complete the initial calibration of the delay chain and obtain an initial calibration value; a temperature sensing module, which collects the system operating temperature on the FPGA chip and obtains operating temperature information; a host computer neural network calibration module, which builds a multi-layer learning network, uses the operating temperature information and the initial calibration value as the input of the network, outputs the delay time of the delay unit, and establishes a corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit. The present invention finds out the corresponding nonlinear change relationship between the delay time data of the delay unit and the temperature data through the learning network, and in actual work, only one calibration and temperature collection are required to obtain a more accurate nonlinear calibration result of each section of the current delay chain.

Description

Technical Field

[0001] The present invention relates to the technical field of signal measurement, and in particular to a neural network measurement and calibration system and method for TDL-TDC. Background Art

[0002] TDC (Time to Digital Converter) is an important part of the detection system. It is often found in electronic instruments and signal processing systems. It is an instrument that converts analog signals into digital signals represented by time. It is widely used in many fields such as laser radar ranging, sonar ranging, remote sensing imaging, etc.

[0003] TDC is generally implemented by ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array). The operating accuracy of TDC depends on the ability of its internal structure to measure time more accurately. Commonly used fine time measurement methods include: multi-phase clock sampling method, vernier method, tap delay chain method, etc. The measurement accuracy that can be achieved by the first two methods is closely related to the system operating frequency, so in TDC systems, the tap delay chain structure is often used.

[0004] At present, the calibration function of TDC built based on tapped delay chain mainly relies on code density calibration method. The code density calibration method takes a long time to calibrate, which will cause the system to have too long dead time. At the same time, since the delay time of TDL-TDC delay unit is related to factors such as PVT (process, voltage, temperature), in actual work, as the operating temperature increases, a large amount of delay time calibration is often required to continue to meet the requirements of working accuracy, which further aggravates the impact of the above problems.

[0005] In the prior art, FPGA is usually used to build a long chain TDC, so that the total delay time of the delay chain in TDL-TDC is longer than the time period of the signal to be tested, so as to achieve the purpose of continuously collecting two consecutive signals to be tested. Under different temperatures, continuous signals to be tested with fixed frequencies are collected respectively to obtain two delay time tap and lap_d values, so that the difference T 0 =lap_d–tap. Different temperatures can be measured to obtain multiple different T 0 As a result, at room temperature T 0(room) As the reference temperature, calculate the temperature coefficient of different temperature differences compared to room temperature. 0(room) / T 0. In actual application, the code density calibration module is first used to collect the initial delay time value of each delay chain delay unit at room temperature, and then the delay time of each delay chain in operation is linearly corrected according to the current temperature coefficient calculated by the reference delay chain, that is, the initial delay time value is multiplied by the temperature coefficient result obtained by the reference delay chain, and then the delay time of each delay chain at the current temperature is obtained. Since the above scheme uses a fixed constant coefficient, after multiplying and calibrating the delay time of delay units in different delay chains and different positions, only the delay time of the delay unit in the middle part of the delay chain meets the working requirements after the delay time calibration. After the delay time of a large number of delay units in the front and rear parts of the delay chain are calibrated, the delay error is still large.

[0006] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0007] The object of the present invention is to provide a neural network measurement calibration system and method for TDL-TDC, which can overcome the problems of fixed calibration coefficient values ​​and large linear calibration errors in the prior art.

[0008] To achieve the above object, an embodiment of the present invention provides a neural network measurement and calibration system for TDL-TDC, comprising:

[0009] The TDL-TDC module is built on the FPGA chip. The TDL-TDC module uses the code density calibration method to complete the initial calibration of the delay chain and obtain the initial calibration value;

[0010] The temperature sensor module collects the operating temperature of the system on the FPGA chip and obtains the operating temperature information;

[0011] The host computer neural network calibration module builds a multi-layer learning network, takes the operating temperature information and the initial calibration value as the network input, outputs the delay time of the delay unit, and establishes the corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit.

[0012] In one or more embodiments, the learning network, whose network training samples include input vector X, expected output t, deviation between network output value Y and expected output value t, adjusts the connection strength Wij between input node and hidden layer node, connection strength Tjk between hidden layer node and output node, and threshold, so that the error decreases along the gradient direction, and after repeated learning and training, the network parameters corresponding to the minimum error are determined, and the training stops.

[0013] In one or more embodiments, the weight updating step of the learning network includes:

[0014] (1) Initialize the connection weights of each layer and set the learning rate and inertia coefficient;

[0015] (2) Input a sample pair and calculate the output value of each layer node;

[0016] (3) According to the gradient descent strategy, the parameters are adjusted in the negative gradient direction of the objective function.

[0017] In one or more embodiments, the learning network uses cumulative errors to update weights, and then updates parameters after reading the entire training set.

[0018] In one or more embodiments, the TDL-TDC module comprises:

[0019] A coarse time measurement module measures the coarse time interval between the Start pulse signal to be tested and the Stop pulse signal to be tested;

[0020] The fine time measurement module uses the tap delay chain method to measure the small time interval between the rising edge of the Start pulse signal to be tested and the rising edge of the Stop pulse signal to be tested and the rising edge of the system clock signal;

[0021] The edge detection module finds the edge transition position of the non-thermometer-coded delay chain output and converts it into a one-hot code;

[0022] The encoder module converts the one-hot code into binary and obtains the total number of signals passing through the delay unit;

[0023] On-chip calibration module, which uses code density calibration method to complete the initial calibration of the delay chain;

[0024] The serial communication module uploads the initial calibration value and operating temperature information to the neural network calibration module of the host computer.

[0025] In one or more embodiments, the TDL-TDC module further includes:

[0026] The Wave-union transmitter module separates the input single Start pulse signal to be measured and the input single Stop pulse signal to be measured into two continuous pulse signals, and inputs the separated pulse signals into the fine time measurement module.

[0027] In one or more embodiments, the TDL-TDC module further includes:

[0028] The oscillation signal generation module generates a random pulse signal independent of the system clock signal, obtains the delay time of each delay unit after on-chip calibration, and uploads it to the neural network calibration module of the host computer.

[0029] In one or more embodiments, the coarse time measurement module uses two inverted Gray code adders to accumulate the time interval to be measured. When the pulse signal to be measured arrives in the first half cycle, the value of the positive phase counter is used, and when the pulse signal to be measured arrives in the second half cycle, the value of the inverted phase counter is used.

[0030] In one or more embodiments, the result of the fine time measurement module is latched using a double-stage flip-flop.

[0031] To achieve the above object, an embodiment of the present invention further provides a neural network measurement and calibration method for TDL-TDC, comprising:

[0032] Build a TDL-TDC module on the FPGA chip, use the code density calibration method to complete the initial calibration of the delay chain, and obtain the initial calibration value;

[0033] Collect the FPGA chip system on chip to obtain the operating temperature information;

[0034] A multi-layer learning network is constructed, the operating temperature information and the initial calibration value are used as the input of the network, the output is the delay time of the delay unit, and a corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit is established.

[0035] Compared with the prior art, the present invention finds out the corresponding nonlinear change relationship between the delay time data and the temperature data of the delay unit through a learning network, and can obtain more accurate nonlinear calibration results of each unit in the current delay chain through only one calibration and temperature collection. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of the principle of a neural network measurement and calibration system for TDL-TDC according to an embodiment of the present invention;

[0037] Figure 2 is a waveform principle diagram of a TDL-TDC system according to an embodiment of the present invention;

[0038] Figure 3 is a schematic diagram of an FPGA tap delay chain according to an embodiment of the present invention;

[0039] Figure 4 is a schematic diagram of a BP neural network model according to an embodiment of the present invention;

[0040] Figure 5 is a schematic diagram of a neural network training process according to an embodiment of the present invention;

[0041] Figure 6 is a schematic diagram of a multi-pulse detection principle according to an embodiment of the present invention;

[0042] Figure 7 is a workflow diagram of a neural network calibration module according to an embodiment of the present invention;

[0043] Figure 8 It is a state transition diagram generated by building a state machine based on the code density calibration principle by an on-chip calibration module according to one embodiment of the present invention. DETAILED DESCRIPTION

[0044] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0045] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0046] According to a preferred embodiment of the present invention, a neural network measurement and calibration system for TDL (tapped delay chain)-TDC is provided, in which TDL-TDC is built on an FPGA platform, and a neural network is built on a host computer. After the host computer network training is completed, the TDL-TDC on the FPGA platform is used for subsequent applications.

[0047] like Figure 1 As shown, the neural network measurement and calibration system for TDL-TDC includes a TDL-TDC module, a temperature sensing module and a host computer neural network calibration module, wherein the TDL-TDC module uses a code density calibration method to complete the initial calibration of the delay chain to obtain an initial calibration value; the temperature sensing module senses the operating temperature of the FPGA chip on-chip system to obtain operating temperature information; the host computer neural network calibration module builds a multi-layer learning network, uses the operating temperature information and the initial calibration value as the input of the network, and outputs the delay time of the delay unit, thereby establishing a corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit.

[0048] The TDL-TDC module includes: Wave-union transmitter module, coarse time measurement module, fine time measurement module, edge detection module, encoder module, on-chip calibration module, serial communication module and oscillation signal generation module.

[0049] Combination Figure 2As shown, the input signal includes the Start pulse signal to be tested and the Stop pulse signal to be tested, which are the starting pulse signal to be tested and the ending pulse signal to be tested of the required timing time interval respectively. The timing starts after the rising edge of the Start signal arrives, and the timing stops after the rising edge of the Stop signal arrives. Clk is the system clock signal.

[0050] The Wave union transmitter module copies the Start pulse signal to be tested and the Stop pulse signal to be tested into two pulse signals, that is, two Start pulse signals to be tested and two Stop pulse signals to be tested. The copied signals are used for multiple measurements to eliminate the influence of errors such as over-wide bit on the accuracy.

[0051] The coarse time measurement module includes a coarse counter and a data processing module, which are used to measure the coarse time interval between the two input pulse signals to be measured, Start and Stop. The coarse time measurement module uses two inverted Gray code adders to accumulate the time interval to be measured. When the pulse signal to be measured arrives in the first half cycle, the value of the positive phase counter is used; when the pulse signal to be measured arrives in the second half cycle, the value of the inverted phase counter is used. The edge detection of the pulse signal to be measured is performed to obtain the interval gate signal Gate between the edges of the two signals. The adder counts the cycle T. When Gate = 1, the total number of adder counts N can be obtained, and the coarse time interval between the Start and Stop pulses is N*T.

[0052] Combination Figure 3 As shown, the fine time measurement module includes a delay chain and a trigger. The fine time measurement module uses a tapped delay chain method to divide the small time interval (△t1, △t2) between the rising edge of the pulse signal to be measured and the rising edge of the system clock signal into a small time (Ti) of the delay unit (adder as a delay unit). The total delay time of the delay chain is the sum of the delay times of the delay units through which the signal passes. The result is latched using a double-stage trigger.

[0053] Ginseng Figure 6 As shown, in some embodiments, multiple Stop pulse signals to be tested are included: Stop1, Stop2, Stop3, Stop4..., and correspondingly, the small time intervals between the rising edge of the Stop pulse signal to be tested and the rising edge of the system clock signal are △t1, △t2, △t3, △t4... The figure uses 4 Stop pulse signals to be tested as an example to illustrate that multiple channels are set up to simultaneously measure the pulse signals of multiple channels.

[0054] The edge detection module finds the edge transition position of the non-thermometer-coded delay chain output and converts it into a one-hot code, and then converts the one-hot code into binary through the encoder module to obtain the total number of signals passing through the delay unit.

[0055] The encoder uses a fat tree structure. The fat tree principle formula is as follows:

[0056]

[0057]

[0058]

[0059] Among them, H[i] is the one-hot code obtained by edge detection, and B[k] is the binary code finally obtained by the encoder.

[0060] The on-chip calibration module builds a state machine on the FPGA chip and uses the code density calibration method to complete the initial calibration of the delay chain.

[0061] The oscillation signal generation module is used to generate a random pulse signal independent of the TDC measurement clock. The delay time of each delay unit after on-chip calibration is obtained, stored in the corresponding address of the storage module and transmitted to the host computer for subsequent use.

[0062] The temperature sensor module is integrated on the FPGA chip to collect the operating temperature of the chip and transmit it to the host computer.

[0063] The serial communication module uploads the initial calibration value and temperature information to the neural network calibration module of the host computer.

[0064] In this embodiment, the fine time measurement module inputs the pulse signal copied by the Wave union transmitter module when working, and inputs the independent pulse signal of the oscillation signal generating module during on-chip calibration. The independent random pulse and the fine time measurement module are used, that is, the code density calibration method is used to obtain the final calibration value in the calibration module, and the calibration value is the minimum delay time of the delay unit.

[0065] The on-chip calibration module builds a state machine based on the code density calibration principle. The state transition diagram generated by the state machine program is as follows: Figure 8 As shown. Among them, S0 is the initial waiting state, and when the calibration trigger signal arrives, it enters the S1 state; in the S1 state, all the calibration data stored in the storage module are cleared to 0, and the storage module data is triggered to enter the S2 state after all the storage module data are cleared to 0; in the S2 state, a statistical histogram is established, and when the random pulse signal finally falls on a certain delay unit, the data of the corresponding address of the storage module (the address obtained by the encoder) is added by 1. When the number of random signals reaches the specified requirement N, it enters the S3 state; in the S3 state, the statistical histogram obtained in S2 is calculated according to the above formula to obtain the delay time after on-chip calibration of each delay unit, which is stored in the corresponding address of the storage module.

[0066] Combination Figure 4 and Figure 5As shown in the figure, the host computer builds a multi-layer BP neural network, takes temperature information and initial calibration values ​​as the input of the network, sets multiple hidden layers, and outputs the delay time of the delay unit. After nonlinear fitting of neurons, the delay time variation trend of the delay unit at different temperatures can be learned. The network training samples include input vector X, expected output t, and the deviation between the network output value Y and the expected output value t. By adjusting the connection strength Wij between the input node and the hidden layer node, the connection strength Tjk between the hidden layer node and the output node, and the threshold, the error is reduced along the gradient direction. After repeated learning and training, the network parameters (weights and thresholds) corresponding to the minimum error are determined, and the training stops. The trained neural network can process the input information of similar samples and output the result information with the minimum error and nonlinear conversion by itself.

[0067] When the host computer neural network is first built, the different temperatures measured multiple times and the corresponding original data samples of the code density calibration module are transmitted to the host computer through the serial communication module; during training, the BP neural network is used to train to obtain the corresponding functional relationship between the delay time and temperature of the delay unit; in actual work, it is only necessary to calibrate and collect the initial delay time value of the delay unit at room temperature when it runs for the first time after power-on and transmit it to the host computer. In subsequent work, the current operating temperature value collected by the temperature sensor is brought into the functional relationship obtained after training, and the delay time under the current temperature conditions can be obtained.

[0068] This embodiment uses the trained neural network results to replace the large number of calibration steps required by the TDC during actual operation. Based on the network calibration results, the delay time of each delay chain delay unit at the current temperature can be obtained, and the fine time measurement results can be calculated from the delay time. In combination with the coarse time measurement results, the time interval of the current pulse to be measured can be obtained for use in the subsequent imaging processing system. The actual working principle flow chart of the neural network calibration module is shown in the figure. Figure 7 shown.

[0069] The steps for updating the weights of the neural network are:

[0070] (1) Initialize the connection weights of each layer and set the learning rate and inertia coefficient.

[0071] (2) Input a sample pair and calculate the output value of each layer node.

[0072] (3) According to the gradient descent strategy, the parameters are adjusted in the negative gradient direction of the objective function.

[0073] The standard BP algorithm updates the connection weights for only one training example at a time, and the parameters are updated very frequently. In addition, the effects of updating different training examples may be "offset". In order to ultimately achieve the minimum error on all training data, the present invention uses the cumulative error to update the weights. After reading the entire training set, the parameters are updated, which can greatly speed up the training speed.

[0074] The corresponding functional relationship between temperature condition and delay time is fitted through the above BP network. When in use, by giving the current operating temperature condition and the initial delay time value obtained by the on-chip calibration module once calibrated at each power-on operation, the delay time of each group of delay units at the current temperature can be directly calculated according to the functional relationship obtained by the trained network.

[0075] The delay time obtained under the current temperature conditions can be directly stored in the host computer and applied to the subsequent data processing system. At the same time, the serial communication module can also be used to transmit the delay time from the host computer back to the embedded board for storage and easy use on the chip.

[0076] The pulse interval time calculation formula is:

[0077] t=N*T+Δt 1 -Δt 2

[0078] Wherein, t is the interval between two pulses, N is the number of coarse counter counts of the corresponding phase, T is the counter counting period, △t1 is the time interval from the Start signal edge to the coarse counter start counting edge (obtained by the total delay time of the internal delay unit), and △t2 is the time interval from the Stop signal edge to the coarse counter stop counting edge (obtained by the total delay time of the internal delay unit).

[0079] According to a preferred embodiment of the present invention, a neural network measurement calibration method for TDL-TDC is also provided, comprising the steps of:

[0080] (1) Build a TDL-TDC module on the FPGA chip, use the code density calibration method to complete the initial calibration of the delay chain, and obtain the initial calibration value;

[0081] (2) Collect the operating temperature of the system on the FPGA chip to obtain operating temperature information;

[0082] (3) Build a multi-layer learning network, take the operating temperature information and the initial calibration value as the input of the network, output the delay time of the delay unit, and establish the corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit.

[0083] The system of this embodiment uses neural network training to obtain the corresponding functional relationship between temperature and delay time, so each delay part of the delay chain can be calibrated nonlinearly, which has smaller errors than the linear calibration in the prior art, and can take into account the inconsistency of the front, middle and back sections of the delay chain; there is no need to stop working on the chip to free up time for the on-chip calibration module to remeasure and update the delay time, thereby reducing the dead time of system operation; when the amount of collected calibration samples of different temperatures and calibration samples of different development board types is large enough, this TDC system based on neural network calibration can be flexibly used under different temperature change conditions, and can be flexibly transplanted in different development board environments, without the need to retrain the network model when the development board is replaced.

[0084] In addition, the system in this embodiment moves complex calculations from on-chip resources to a host computer, completes calibration on the host computer, and subsequently directly performs data processing on the host computer, thereby reducing the occupancy of on-chip resources and making the overall structure easy to implement.

[0085] In another embodiment, the neural network can also be deployed on an FPGA platform. First, the TDL-TDC part is built on the FPGA platform, and then the on-chip calibration module is used to collect different temperatures and corresponding raw data samples to train the optimized network model in the server. Secondly, the network weights, biases and other parameters that have been trained and optimized are extracted, and the relevant parameters are stored and transplanted into the FPGA. Finally, the neural network structure is built on the FPGA platform using the FPGA on-chip structure, resources and previously optimized network parameters. Subsequently, the initial value and temperature are input into the on-chip network, and the delay time of the delay unit can be directly calculated by the TDL-TDC built by the FPGA in conjunction with the FPGA on-chip network. The system in this embodiment is convenient for the transplantation and movement of embedded systems, and the hardware structure can be flexibly configured. When the computer needs to be changed, the FPGA can be reassembled, and the power consumption is lower than that of the host computer.

[0086] In another embodiment, the TDL-TDC and the network structure can be transplanted and solidified in the ASIC, and the entire system can be integrated into a chip. The system in this embodiment has lower power consumption, faster speed, highest energy efficiency, and the functions of embedded devices. It is also more stable and is conducive to mass production applications.

[0087] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A neural network measurement and calibration system for TDL-TDC, characterized in that: include: The TDL-TDC module is built on the FPGA chip. The TDL-TDC module uses the code density calibration method to complete the initial calibration of the delay chain and obtain the initial calibration value; The temperature sensing module collects the operating temperature of the FPGA chip and obtains the operating temperature information; The upper computer neural network calibration module builds a multi-layer BP neural network, takes the operating temperature information and the initial calibration value as the input of the network, and outputs the delay time of the delay unit, establishes the corresponding nonlinear change relationship between the temperature information and the delay time of the delay unit, and the network training samples include the input vector X, the expected output t, the deviation between the network output value Y and the expected output value t. By adjusting the connection strength Wij between the input node and the hidden layer node, the connection strength Tjk between the hidden layer node and the output node, and the threshold, the error is reduced along the gradient direction. After repeated learning and training, the network parameters corresponding to the minimum error are determined, and the training is stopped. The TDL-TDC module includes: A coarse time measurement module measures the coarse time interval between the Start pulse signal to be tested and the Stop pulse signal to be tested; The fine time measurement module uses the tap delay chain method to measure the small time interval between the rising edge of the Start pulse signal to be tested and the rising edge of the Stop pulse signal to be tested and the rising edge of the system clock signal; The edge detection module finds the edge transition position of the non-thermometer-coded delay chain output and converts it into a one-hot code; The encoder module converts the one-hot code into binary and obtains the total number of signals passing through the delay unit; On-chip calibration module, which uses code density calibration method to complete the initial calibration of the delay chain; The serial communication module uploads the initial calibration value and operating temperature information to the neural network calibration module of the host computer; The Wave-union transmitter module separates the input single Start pulse signal to be measured and the input Stop pulse signal to be measured into two continuous pulse signals, and inputs the separated pulse signals into the fine time measurement module; The oscillation signal generation module generates a random pulse signal independent of the system clock signal, obtains the delay time of each delay unit after on-chip calibration, and uploads it to the neural network calibration module of the host computer.

2. The neural network measurement and calibration system for TDL-TDC according to claim 1, characterized in that: The BP neural network, its weight updating step comprises: (1) Initialize the connection weights of each layer and set the learning rate and inertia coefficient; (2) Input a sample pair and calculate the output value of each layer node; (3) According to the gradient descent strategy, the parameters are adjusted in the negative gradient direction of the objective function.

3. The neural network measurement and calibration system for TDL-TDC according to claim 1, characterized in that: The BP neural network uses cumulative errors to update weights, and updates parameters after reading the entire training set.

4. The neural network measurement and calibration system for TDL-TDC according to claim 1, characterized in that: The coarse time measurement module uses two inverted Gray code adders to accumulate the time interval to be measured. When the pulse signal to be measured arrives in the first half cycle, the value of the positive phase counter is used. When the pulse signal to be measured arrives in the second half cycle, the value of the inverted phase counter is used.

5. The neural network measurement and calibration system for TDL-TDC according to claim 1, characterized in that: The result of the fine time measurement module is latched using a double-stage trigger.

6. A neural network measurement and calibration method for TDL-TDC, characterized in that: include: Build a TDL-TDC module on the FPGA chip, use the code density calibration method to complete the initial calibration of the delay chain, and obtain the initial calibration value; Collect the operating temperature of the system on the FPGA chip to obtain the operating temperature information; A multi-layer BP neural network is constructed, and the operating temperature information and the initial calibration value are used as the input of the network, and the output is the delay time of the delay unit. The nonlinear change relationship corresponding to the temperature information and the delay time of the delay unit is established. The network training samples include the input vector X, the expected output t, and the deviation between the network output value Y and the expected output value t. By adjusting the connection strength Wij between the input node and the hidden layer node, the connection strength Tjk between the hidden layer node and the output node, and the threshold, the error is reduced along the gradient direction. After repeated learning and training, the network parameters corresponding to the minimum error are determined, and the training is stopped. The TDL-TDC module includes: A coarse time measurement module measures the coarse time interval between the Start pulse signal to be tested and the Stop pulse signal to be tested; The fine time measurement module uses the tap delay chain method to measure the small time interval between the rising edge of the Start pulse signal to be tested and the rising edge of the Stop pulse signal to be tested and the rising edge of the system clock signal; The edge detection module finds the edge transition position of the non-thermometer-coded delay chain output and converts it into a one-hot code; The encoder module converts the one-hot code into binary and obtains the total number of signals passing through the delay unit; On-chip calibration module, which uses code density calibration method to complete the initial calibration of the delay chain; The serial communication module uploads the initial calibration value and operating temperature information to the neural network calibration module of the host computer; The Wave-union transmitter module separates the input single Start pulse signal to be measured and the input Stop pulse signal to be measured into two continuous pulse signals, and inputs the separated pulse signals into the fine time measurement module; The oscillation signal generation module generates a random pulse signal independent of the system clock signal, obtains the delay time of each delay unit after on-chip calibration, and uploads it to the neural network calibration module of the host computer.

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