A complete non-volatile boolean logic circuit based on 3m-1r memristor and control method

Abstract

The application discloses a kind of based on 3M-1R memristor complete non-volatile Boolean logic circuit and control method, belong to microelectronic device technical field, this logic circuit mainly consists of three memristors and a fixed resistance, the area occupied by circuit is smaller, circuit complexity is lower, wherein, one input P in logic calculation process is defined as the resistance state of input memristor 1, another input Q is defined as the resistance state of input memristor 2, the resistance state of output memristor is as output, by the gating state of control multiplexer, and corresponding voltage is applied to each memristor, namely, one-step calculation operation can realize arbitrary Boolean logic operation, and in the operation process of logic calculation, the resistance state of input memristor 1 and input memristor 2 does not change, input information is completely non-volatile saved in corresponding memristor, can use as few as possible device and operation step number while in the calculation process, the integrity of input information is protected.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of microelectronic devices, and more particularly, relates to a complete non-volatile Boolean logic circuit based on 3M-1R memristor and a control method. BACKGROUND

[0002] Logic computation is the basis of traditional computer systems, with the advantages of high precision and strong versatility. By implementing basic logic operations such as NOT, AND, and OR, different complex logic computations can be derived and implemented using hardware. Traditionally, logic computation is implemented using cascaded transistors, i.e., binary states provided by threshold switching devices, Boolean gates and computing circuits connected in different topologies to implement predefined functions, but the computing results need to be moved to an off-chip memory for storage. In recent years, the introduction of in-memory computing paradigm can realize in-situ logic computation and storage, reducing the amount of data moved on the bus, thus significantly improving computing efficiency and energy consumption.

[0003] Memristor, as a new type of memory device, has become a strong candidate for in-memory computing architecture due to its natural non-volatility in maintaining resistance state after power-off. Logic implementation based on memristor mainly falls into two categories. The first category is state logic, whose input and output are represented in the form of memristor resistance state and saved in the memristor. This scheme is very beneficial for logic cascade, as the input, intermediate, and output signal quantities are all completely preserved, but the number of devices used is larger, and the number of devices used and operation complexity increase with the complexity of logic computation. The second category is sequential logic, i.e., non-state logic. In this method, input variables are not saved in the memristor, and input is applied in the form of voltage to the port of the memristor circuit, and output is represented in the form of resistance state. This scheme greatly reduces the number of devices used and the number of operation steps, but the logic cascade must introduce the process of digital-to-analog conversion, which reduces the computing efficiency. In addition, there is another implementation method that combines the advantages of the above two methods, defining one of the logic inputs as the resistance state of the memristor and the other as the voltage applied to one end of the memristor, and the output is represented in the form of memristor resistance state. This method uses fewer devices and fewer operation steps, and is easy to implement logic cascade. However, this method only saves half of the input information in place, which cannot protect the integrity of the input information and is not conducive to the reuse of input information. Therefore, there is a need to propose a complete logic implementation scheme that saves all input information completely without destroying the integrity of the input data while using as few devices and operation steps as possible, and is easy to implement logic cascade. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a complete non-volatile Boolean logic circuit based on 3M-1R memristor and a control method, which aims to protect the integrity of input information in the calculation process while using as few devices and operation steps as possible.

[0005] To achieve the above-mentioned purpose, the present application provides, in a first aspect, a complete non-volatile Boolean logic circuit based on 3M-1R memristor, which is used for performing logic operation on input logic value P and / or input logic value Q.

[0006] The above-mentioned logic circuit comprises a controller, three identical memristors, a resistor and a multiplexer; the positive poles of the memristors are all connected to the controller, and the negative poles are all connected to the same word line WL; one end of the resistor is connected to the word line WL, and the other end is connected to the multiplexer; the multiplexer comprises a and b two paths, the a path is connected to the controller, and the b path is floating; one of the memristors is used as an output memristor, and the other two are used as input memristors, which are denoted as input memristor 1 and input memristor 2 respectively.

[0007] The controller is used to: set the output memristor to a high resistance state before performing the logic operation; set the input memristor 1 to a resistance state corresponding to the logic value P when the input of the logic circuit comprises the logic value P; set the input memristor 2 to a resistance state corresponding to the logic value Q when the input of the logic circuit comprises the logic value Q; during the logic operation: control the gating state of the multiplexer, apply voltage A to the input memristor 1, apply voltage B to the input memristor 2, and apply voltage V p to the output memristor, and read the resistance state of the output memristor, which is the logic operation result.

[0008] When the multiplexer is gated to the a path, the controller applies voltage D to the resistor; the values of voltages A, B and D are determined according to the logic value P and the logic operation type, or only according to the logic operation type; V set < V P <1.5*V set ; V set is the threshold value of the memristor from high resistance state to low resistance state.

[0009] Further preferably, when the logic operation type is true logic operation, the multiplexer is gated to the a path, voltage A is 0V, voltage B is 0V, and voltage D is 0V;

[0010] When the logic operation type is false logic operation, the multiplexer is gated to the b path, voltage A is V P / 2, and voltage B is V P / 2.

[0011] When the logic operation type is P logic operation, the multiplexer selects the b path; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of 0V, and the voltage B takes the value of 0V.

[0012] When the logic operation type is Q logic operation, the multiplexer selects the b path; and when the memristor M1 is in the high resistance state, the voltage A takes the value of V P / 2, and the voltage B takes the value of 0V; when the memristor M1 is in the low resistance state, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2.

[0013] When the logic operation type is non-P logic operation, the multiplexer selects the a path, the voltage A takes the value of V P / 2, the voltage B takes the value of 0V, and the voltage D takes the value of 0V.

[0014] When the logic operation type is non-Q logic operation, the multiplexer selects the a path, the voltage A takes the value of 0V, the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V.

[0015] When the logic operation type is AND logic operation, the multiplexer selects the b path; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2.

[0016] When the logic operation type is NAND logic operation, the multiplexer selects the a path, the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2.

[0017] When the logic operation type is OR logic operation, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of 0V.

[0018] When the logic operation type is NOR logic operation, the multiplexer selects the a path, the voltage A takes the value of V P / 2, the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V.

[0019] When the logic operation type is material implication logic operation, the multiplexer selects the a path, the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of VP / 2, voltage B is -V P / 2;

[0020] When the logic operation type is negative material implication logic operation, the multiplexer selects the b path, voltage A is 0V, and voltage B is V P / 2;

[0021] When the logic operation type is inverse material implication logic operation, when the logic value P is 0, the multiplexer selects the a path, voltage A is 0V, and voltage B is V P / 2, voltage D is 0V; when the logic value P is 1, the multiplexer selects the b path, voltage A is 0V, and voltage B is 0V;

[0022] When the logic operation type is inverse negative material implication logic operation, the multiplexer selects the b path, voltage A is V P / 2, and voltage B is 0V;

[0023] When the logic operation type is exclusive or logic operation, the multiplexer selects the b path; and when the logic value P is 0, voltage A is 0V, and voltage B is 0V; when the logic value P is 1, voltage A is 0V, and voltage B is V P / 2;

[0024] When the logic operation type is same or logic operation, the multiplexer selects the a path, and voltage D is 0V; and when the logic value P is 0, voltage A is 0V, and voltage B is V P / 2; when the logic value P is 1, voltage A is V P / 2, and voltage B is -V P / 2.

[0025] Further preferably, the above-mentioned memristor comprises a high resistance state and a low resistance state; the high resistance state corresponds to the logic value "0", and the low resistance state corresponds to the logic value "1".

[0026] Further preferably, the resistance value of the resistance is between the high resistance state resistance value and the low resistance state resistance value of the memristor; the resistance value of the resistance is wherein R H is the high resistance state resistance value of the memristor, and R L is the low resistance state resistance value of the memristor.

[0027] In a second aspect, the present application provides a control method of the above-mentioned complete non-volatile Boolean logic circuit, for performing logic operation on the input logic value P and / or the input logic value Q, comprising the following steps:

[0028] S1, before logical operation: set the output memristor to high resistance state; when the input of the logic circuit includes a logic value P, set the input memristor 1 to the resistance state corresponding to the logic value P; when the input of the logic circuit includes a logic value Q, set the input memristor 2 to the resistance state corresponding to the logic value Q;

[0029] S2, during logical operation: control the gating state of the multiplexer, and apply voltage A to the input memristor 1, voltage B to the input memristor 2, and voltage V to the output memristor p ; read the resistance state of the output memristor, which is the result of the logical operation;

[0030] wherein, when the multiplexer is gated on a path, the controller applies voltage D to the resistor; the values of voltages A, B and D are determined according to the logic value P and the type of logical operation, or only according to the type of logical operation; V set <V P <1.5*V set ; V set is the threshold value of the memristor from high resistance state to low resistance state.

[0031] Further preferably, when the type of logical operation is true logical operation, the multiplexer is gated on a path, voltage A has a value of 0V, voltage B has a value of 0V, and voltage D has a value of 0V;

[0032] When the type of logical operation is false logical operation, the multiplexer is gated on b path, voltage A has a value of V P / 2, and voltage B has a value of V P / 2;

[0033] When the type of logical operation is P logical operation, the multiplexer is gated on b path; and when the logic value P is 0, voltage A has a value of 0V, and voltage B has a value of V P / 2; when the logic value P is 1, voltage A has a value of 0V, and voltage B has a value of 0V;

[0034] When the type of logical operation is Q logical operation, the multiplexer is gated on b path; and when the memristor M1 is in high resistance state, voltage A has a value of V P / 2, and voltage B has a value of 0V; when the memristor M1 is in low resistance state, voltage A has a value of V P / 2, and voltage B has a value of -V P / 2;

[0035] When the type of logical operation is not-P logical operation, the multiplexer is gated on a path, voltage A has a value of V P / 2, voltage B has a value of 0V, and voltage D has a value of 0V;

[0036] When the logic operation type is non-Q logic operation, the multiplexer selects the a path, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V.

[0037] When the logic operation type is AND logic operation, the multiplexer selects the b path; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2.

[0038] When the logic operation type is NAND logic operation, the multiplexer selects the a path, and the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2.

[0039] When the logic operation type is OR logic operation, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of 0V.

[0040] When the logic operation type is NOR logic operation, the multiplexer selects the a path, the voltage A takes the value of V P / 2, and the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V.

[0041] When the logic operation type is material implication logic operation, the multiplexer selects the a path, and the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2.

[0042] When the logic operation type is negative material implication logic operation, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2.

[0043] When the logic operation type is inverse material implication logic operation, when the logic value P is 0, the multiplexer selects the a path, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V; when the logic value P is 1, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of 0V.

[0044] When the logic operation type is inverse negative material implication logic operation, the multiplexer selects the b path, the voltage A takes the value of V P / 2, and the voltage B takes the value of 0V.

[0045] When the logic operation type is exclusive-OR logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A takes the value of 0V and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of 0V and the voltage B takes the value of V P / 2;

[0046] When the logic operation type is exclusive-NOR logic operation, the multiplexer is enabled by the a path and the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2 and the voltage B takes the value of -V P / 2.

[0047] Further preferably, the above-mentioned memristor comprises a high resistance state and a low resistance state; the high resistance state corresponds to the logic value "0" and the low resistance state corresponds to the logic value "1".

[0048] In a third aspect, the present application provides a logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, comprising:

[0049] The output memristor in the previous stage logic operation is taken as the input memristor 2 in the current stage logic operation, and the control method provided in the second aspect of the present application is executed, so as to realize the logic cascading;

[0050] Or, the output memristor in the previous stage logic operation is taken as the input memristor 1 in the current stage logic operation; when the current stage logic operation performs an operation related to the logic value P, the logic value corresponding to the resistance state of the output memristor in the previous stage logic operation is read as the input logic value P of the current stage logic operation, and the control method provided in the second aspect of the present application is executed, so as to realize the logic cascading; when the current stage logic operation performs an operation irrelevant to the logic value P, the control method provided in the second aspect of the present application is directly executed, so as to realize the logic cascading.

[0051] In a fourth aspect, the present application further provides a computer readable storage medium comprising a stored computer program, wherein when the computer program is run by a processor, the device where the storage medium is located is controlled to execute the control method of the complete non-volatile Boolean logic circuit provided in the second aspect of the present application and / or the logic cascading method provided in the third aspect of the present application.

[0052] Overall, the above technical solutions conceived by the present application can achieve the following beneficial effects:

[0053] 1. The application provides a complete non-volatile Boolean logic circuit based on 3M-1R memristor, which is mainly composed of three memristors and a fixed resistor (3M-1R), and has small area and low complexity; wherein, one input P in the logic calculation process is defined as the resistance state of the input memristor 1, the other input Q is defined as the resistance state of the input memristor 2, and the resistance state of the output memristor is used as the output; by controlling the gating state of the multi-channel selector and applying corresponding voltage to each memristor, any Boolean logic operation can be realized by one-step calculation operation, and in the operation process of logic calculation, the resistance states of the input memristor 1 and the input memristor 2 do not change, and the input information is completely and non-volatile saved in the corresponding memristor; compared with the existing logic method, the application can protect the integrity of the input information in the calculation process while using as few devices and operation steps as possible.

[0054] 2. The complete non-volatile Boolean logic circuit provided by the application can completely and non-volatile save the input information in the corresponding memristor, and can more efficiently process complex logic operations, for example, the binary adder and the output XOR gate can be executed by (p IMP q) IMP ((q IMP p) IMP 0); however, this composite operation needs to use p and q twice, so if the input information is not saved in the memristor state or the state of the input memristor is destroyed in the calculation process, the two inputs need to be copied to other memristors in the array for reuse in the application scenario. At the same time, the primitive design of the application does not destroy the input information, that is, the input memristor state still maintains the written input information value after the logic calculation is completed.

[0055] 3. The complete non-volatile Boolean logic circuit provided by the application has small area and low complexity, and the entire operation process can guarantee the integrity of the input information, so that the logic cascade operation based on the circuit is simple and easy to implement, and helps to realize more complex logic functions.

[0056] 4. The complete non-volatile Boolean logic circuit provided by the application directly stores the logic output in the memristor after the logic operation is completed according to the non-volatile characteristics of the memristor, without additional data transmission and storage, thereby reducing power consumption and time delay.

[0057] 5. The application provides a logic cascade method based on the complete non-volatile Boolean logic circuit, wherein the resistance state of the output memristor is used as an input of the next logic calculation, and the logic operation is performed according to the same configuration mode, so that the result of the previous logic calculation can be directly used as the input of the next logic operation, and the logic cascade is simple and easy to implement, and helps to realize more complex logic functions. BRIEF DESCRIPTION OF DRAWINGS

[0058] Figure 1 A memristor and a resistance-voltage characteristic test diagram thereof provided by the present application;

[0059] Figure 2 A complete non-volatile Boolean logic circuit schematic diagram provided by an embodiment of the present application;

[0060] Figure 3 A complete non-volatile Boolean logic circuit schematic diagram provided by an embodiment of the present application;

[0061] Figure 4 XOR logic calculation waveform diagrams provided by an embodiment of the present application; wherein (a) is an XOR logic calculation waveform diagram when the logic input P is 0; (b) is an XOR logic calculation waveform diagram when the logic input P is 1;

[0062] Figure 5 Memristor resistance state change comparison results measured before and after operation provided by an embodiment of the present application; wherein (a) is a memristor resistance state change comparison result measured before and after operation when the logic input P is 1 and the logic input Q is 0; (b) is a memristor resistance state change comparison result measured before and after operation when the logic input P is 0 and the logic input Q is 1; (c) is a memristor resistance state change comparison result measured before and after operation when the logic input P is 1 and the logic input Q is 0; (d) is a memristor resistance state change comparison result measured before and after operation when the logic input P is 1 and the logic input Q is 1;

[0063] Figure 6 Memristor current simulation result diagrams in the read circuit before and after XNOR logic calculation provided by an embodiment of the present application; wherein (a) is a memristor current simulation result diagram in the read circuit before and after XNOR logic calculation when the logic input P is 0; (b) is a memristor current simulation result diagram in the read circuit before and after XNOR logic calculation when the logic input P is 1;

[0064] Figure 7 Memristor current simulation result diagrams in the read circuit before and after AND logic calculation provided by an embodiment of the present application; wherein (a) is a memristor current simulation result diagram in the read circuit before and after AND logic calculation when the logic input P is 0; (b) is a memristor current simulation result diagram in the read circuit before and after AND logic calculation when the logic input P is 1;

[0065] Figure 8 Memristor current simulation result diagrams in the read circuit before and after NAND logic calculation provided by an embodiment of the present application; wherein (a) is a memristor current simulation result diagram in the read circuit before and after NAND logic calculation when the logic input P is 0; (b) is a memristor current simulation result diagram in the read circuit before and after NAND logic calculation when the logic input P is 1. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and should not be used to limit the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0067] In order to achieve the above-mentioned object, the present application provides a complete non-volatile Boolean logic circuit based on 3M-1R memristor, which is used for logic operation on input logic value P and / or input logic value Q, comprising: a controller, three identical memristors, a resistor and a multiplexer; the positive electrode of each memristor is connected to the controller, and the negative electrode is connected to the same word line WL; one end of the resistor is connected to the word line WL, and the other end is connected to the multiplexer; the multiplexer includes a and b two paths, the a path is connected to the controller, and the b path is floating; the initial state of each memristor is high resistance state, one of which is an output memristor, and the other two are input memristors, which are denoted as input memristor 1 and input memristor 2 respectively; specifically, as shown in the figure Figure 1 The structure diagram of the memristor used in the circuit and the resistance change I-V characteristic test diagram are shown. The memristor includes two resistance states, high resistance state and low resistance state; when a forward voltage V set is applied across the memristor, the current I cc is limited, the resistance of the memristor is set to low resistance state; when a negative voltage V reset is applied across the memristor, the resistance of the memristor is set to high resistance state; by controlling the voltage across the memristor, the memristor can be switched between high resistance state and low resistance state. Among them, the high resistance state of the memristor corresponds to the logic value "0", and the low resistance state of the memristor corresponds to the logic value "1".

[0068] The controller is used to: set the output memristor to high resistance state before logic operation; set the input memristor 1 to the resistance state corresponding to the logic value P when the input of the logic circuit includes the logic value P; set the input memristor 2 to the resistance state corresponding to the logic value Q when the input of the logic circuit includes the logic value Q; during logic operation: control the gating state of the multiplexer, and apply voltage A to the input memristor 1, voltage B to the input memristor 2, and voltage V p to the output memristor, and read the resistance state of the output memristor, which is the logic operation result; wherein, when the multiplexer selects the a path, the controller applies voltage D to the resistor; the values of voltages A, B and D are determined according to the logic value P and the type of logic operation, or only according to the type of logic operation; V set < V P<1.5*V set V set The threshold for a memristor to transition from a high-resistance state to a low-resistance state.

[0069] To further illustrate the above technical solution, a detailed description is provided below with reference to specific embodiments:

[0070] like Figure 2 As shown, in this embodiment, the complete non-volatile Boolean logic circuit includes three memristors (M1, M2, and M3), a word line (WL), bit lines (BL1, BL2, and BL3), a fixed resistor R, and a multiplexer S. The positive terminal of memristor M1 is connected to the control terminal T1 of the controller via bit line BL1, the positive terminal of memristor M2 is connected to the control terminal T2 of the controller via bit line BL2, and the positive terminal of memristor M3 is connected to the control terminal T3 of the controller via bit line BL3. The negative terminals of each memristor are connected to the same word line WL. One end of the fixed resistor is connected to the word line WL, and the other end is connected to the multiplexer S. The multiplexer S includes two paths, a and b. Path a is connected to the control terminal T4 of the controller, and path b is floating. The resistance value of the resistor is between the high-resistance value and the low-resistance value of the memristor, and it mainly plays the role of voltage division and current limiting in this circuit. In some optional implementations, the resistance value is... R H R is the high-resistance resistance value of the memristor. L This represents the low-resistance resistance value of the memristor. Considering that the memristor exhibits certain fluctuations in both its high and low resistance states, the fixed resistor R can be chosen to be slightly larger than [value missing]. This provides better assurance for the reliability of the circuit. In this embodiment, the resistor R is 10KΩ, and the on / off ratio of the memristor is greater than 100, making it possible to clearly distinguish between the low-resistance state, high-resistance state of the memristor, and the resistance value of the fixed resistor R.

[0071] It should be noted that, Figure 2 This is merely a schematic diagram of this embodiment; the position of resistor R is not limited, and it can also be connected to the end closer to M1, such as... Figure 3 As shown.

[0072] Any two memristors can be selected as input memristors; there is no limitation here. In this embodiment, memristors M1 and M2 are used as input memristor 1 and input memristor 2, respectively; memristor M3 is used as output memristor. The initial state of memristors M1, M2, and M3 is all high impedance.

[0073] Before performing logic operations: Set the output memristor to a high impedance state; when the input of the logic circuit includes the logic value P, set the memristor M1 to the impedance state corresponding to the logic value P; when the input of the logic circuit includes the logic value Q, set the input memristor M2 to the impedance state corresponding to the logic value Q.

[0074] During logical operations: the selection state of the multiplexer is controlled, and when the multiplexer selects channel a, a voltage D is applied to one end of the resistor through control terminal T4; a voltage A is applied to M1 through control terminal T1, a voltage B is applied to M2 through control terminal T2, and a constant operating voltage C = V is applied through control terminal T3. p In one calculation cycle, each control terminal is simultaneously excited to complete the corresponding logic operation. The resistance state of the output memristor M3 is the result of the logic operation.

[0075] The values ​​of voltages A, B, and D are determined by the logic value P and the logic operation type, or solely by the logic operation type; furthermore, the electrical signals used in the logic operation are all voltage pulse signals; to meet the requirements of the logic operation, V P The voltage amplitude should be between V set With 1.5*V set To illustrate this, let's take the XOR logic primitive as an example. When P = 0, the voltages on T1, T2, and T3 are configured as 0, 0, and V, respectively. P When both input memristors are in a high-resistance state (P=0, Q=0), according to Ohm's law and Kirchhoff's laws, the voltage on the common word line WL is theoretically calculated to be V. P / 3, then the voltage drop across the output memristor M3 is 2 / 3*V P To ensure correct output according to the XOR logic truth table, the voltage drop across the output memristor M3 should be less than the memristor's V. set Only in this way can we ensure that M3 remains in a high-impedance state, and the calculated result is 0; when the first input memristor is in a high-impedance state and the second input memristor is in a low-impedance state, i.e., under the input conditions of P=0 and Q=1, the theoretically calculated voltage on the common word line WL is V. P Then the voltage drop across the output memristor M3 is V. P In order to output correctly according to the XOR logic truth table, the voltage drop across the output memristor M3 should be greater than or equal to the memristor's voltage V. set Only then can the M3 state be ensured to switch from high impedance to low impedance, resulting in a calculation of 1. Furthermore, considering the intrinsic randomness of memristor device parameters, therefore, in the embodiment, V... P =1.2*V set The average value.

[0076] Specifically, the complete non-volatile Boolean logic implementation method, without considering initialization and read steps, only requires one calculation step to implement the calculation of 16 complete logics, and meets the requirements of easy implementation of logic cascading and protection of the integrity of input information during the calculation process, as shown in Table 1:

[0077] When the logic operation type is TRUE, the multiplexer selects the a path, and the pulse amplitudes of the voltages A, B and C are all set to 0V; at this time, the resistance states of the memristors M1 and M2 are not required, and can be set to any resistance state according to the P and Q values input by the user;

[0078] When the logic operation type is FALSE, the multiplexer selects the b path, and the pulse amplitudes of the voltages A and B are both set to V P / 2; at this time, the resistance states of the memristors M1 and M2 are not required, and can be set to any resistance state according to the P and Q values input by the user;

[0079] When the logic operation type is COPY P, the multiplexer selects the b path, and the memristor M1 is set to the resistance state corresponding to the logic value P; and when the logic value P is 0, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2; when the logic value P is 1, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to 0V; at this time, the resistance state of the memristor M2 is not required, and can be set to any resistance state according to the Q value input by the user;

[0080] When the logic operation type is COPY Q, the multiplexer selects the b path, and the memristor M2 is set to the resistance state corresponding to the logic value Q; the resistance state of the memristor M1 can be set by the user as needed, and different resistance states of the memristor M1 correspond to different values of the voltages A and B, specifically, when the memristor M1 is in a high resistance state, the pulse amplitude of the voltage A is set to V P / 2, and the pulse amplitude of the voltage B is set to 0V; when the memristor M1 is in a low resistance state, the pulse amplitude of the voltage A is set to V P / 2, and the pulse amplitude of the voltage B is set to -V P / 2;

[0081] When the logic operation type is NOT P, the multiplexer selects the a path, the memristor M1 is set to the resistance state corresponding to the logic value P, the pulse amplitude of the voltage A is set to V P / 2, the pulse amplitude of the voltage B is set to 0V, and the pulse amplitude of the voltage D is set to 0V; at this time, the resistance state of the memristor M2 is not required, and can be set to any resistance state according to the Q value input by the user;

[0082] When the logic operation type is NOT Q, the multiplexer selects the a path, the memristor M2 is set to the resistance state corresponding to the logic value Q, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2, the pulse amplitude of voltage D is set to 0V; at this time, the resistance state of the memristor M2 is not required, and can be set to any resistance state according to the Q value input by the user;

[0083] When the logic operation type is AND, the multiplexer is enabled in the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, and the memristor M2 is set to the resistance state corresponding to the logic value Q; and when the logic value P is 0, the pulse amplitude of voltage A is set to 0V, and the pulse amplitude of voltage B is set to V P / 2; when the logic value P is 1, the pulse amplitude of voltage A is set to V P / 2, and the pulse amplitude of voltage B is set to -V P / 2;

[0084] When the logic operation type is NAND, the multiplexer is enabled in the a path, the pulse amplitude of voltage D is set to 0V, the memristor M1 is set to the resistance state corresponding to the logic value P, and the memristor M2 is set to the resistance state corresponding to the logic value Q; and when the logic value P is 0, the pulse amplitude of voltage A is set to 0V, and the pulse amplitude of voltage B is set to 0V; when the logic value P is 1, the pulse amplitude of voltage A is set to 0V, and the pulse amplitude of voltage B is set to V P / 2;

[0085] When the logic operation type is OR, the multiplexer is enabled in the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, the memristor M2 is set to the resistance state corresponding to the logic value Q, the pulse amplitude of voltage A is set to 0V, and the pulse amplitude of voltage B is set to 0V;

[0086] When the logic operation type is NOR, the multiplexer is enabled in the a path, the memristor M1 is set to the resistance state corresponding to the logic value P, the memristor M2 is set to the resistance state corresponding to the logic value Q, the pulse amplitude of voltage A is set to V P / 2, and the pulse amplitude of voltage B is set to V P / 2, the pulse amplitude of voltage D is set to 0V;

[0087] When the logic operation type is IMP, the multiplexer is enabled in the a path, the memristor M1 is set to the resistance state corresponding to the logic value P, the memristor M2 is set to the resistance state corresponding to the logic value Q, and the pulse amplitude of voltage D is set to 0V; and when the logic value P is 0, the pulse amplitude of voltage A is set to 0V, and the pulse amplitude of voltage B is set to 0V; when the logic value P is 1, the pulse amplitude of voltage A is set to V P / 2, and the pulse amplitude of voltage B is set to -V P / 2;

[0088] When the logic operation type is negative material implication logic operation (NIMP), the multiplexer selects the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, the memristor M2 is set to the resistance state corresponding to the logic value Q, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2.

[0089] When the logic operation type is negative material implication logic operation (NIMP), the multiplexer selects the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, the memristor M2 is set to the resistance state corresponding to the logic value Q, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2, and the pulse amplitude of the voltage D is set to 0V; when the logic value P is 1, the multiplexer selects the b path, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to 0V.

[0090] When the logic operation type is negative material implication logic operation (NIMP), the multiplexer selects the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, the memristor M2 is set to the resistance state corresponding to the logic value Q, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2, and the pulse amplitude of the voltage B is set to 0V.

[0091] When the logic operation type is exclusive or logic operation (XOR), the multiplexer selects the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, and the memristor M2 is set to the resistance state corresponding to the logic value Q; and when the logic value P is 0, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to 0V; when the logic value P is 1, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2.

[0092] When the logic operation type is exclusive or logic operation (XOR), the multiplexer selects the b path, the memristor M1 is set to the resistance state corresponding to the logic value P, and the memristor M2 is set to the resistance state corresponding to the logic value Q; and when the logic value P is 0, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to 0V; when the logic value P is 1, the pulse amplitude of the voltage A is set to 0V, and the pulse amplitude of the voltage B is set to V P / 2; when the logic value P is 1, the pulse amplitude of the voltage A is set to V P / 2, and the pulse amplitude of the voltage B is set to -V P / 2.

[0093] Table 1

[0094]

[0095]

[0096] In order to further the technical solutions provided by the present application, the embodiment provides changes of the states of the memristors in the logic gate measured in the actual circuit in the four input conditions of the XOR logic calculation, wherein each group is tested for 10 times, and the fixed resistance R is 10KΩ. Specifically, as shown in Table 2, it is an XOR logic truth table, wherein the memristor input represents the resistance state of the set memristor before the logic operation is performed, and the memristor output represents the resistance state of the memristor after the logic operation is completed. As shown in Figure 4 Fig. 2 is a waveform diagram of the XOR logic calculation; wherein Fig. (a) is a waveform diagram of the XOR logic calculation when the logic input P is 0, and Fig. (b) is a waveform diagram of the XOR logic calculation when the logic input P is 1. Figure 5 Fig. 3 is a comparison result of the resistance state changes of the memristor measured before and after the operation; wherein Fig. (a) is a comparison result of the resistance state changes of the memristor measured before and after the operation when the logic input P is 1 and the logic input Q is 0; Fig. (b) is a comparison result of the resistance state changes of the memristor measured before and after the operation when the logic input P is 0 and the logic input Q is 1; Fig. (c) is a comparison result of the resistance state changes of the memristor measured before and after the operation when the logic input P is 1 and the logic input Q is 0; and Fig. (d) is a comparison result of the resistance state changes of the memristor measured before and after the operation when the logic input P is 1 and the logic input Q is 1. Specifically, in Fig. 3, M3 represents the resistance state of the memristor M3 measured before the operation, and M3' represents the resistance state of the memristor M3 measured after the operation. It can be seen from the figure that the designed control scheme can accurately realize the XOR logic operation result in the truth table. Figure 5

[0097] Table 2

[0098]

[0099] Similarly, other basic Boolean logic functions can also be realized according to the above method. Figures 6-8 Fig. 4 respectively provides the simulation result diagrams of the memristor current in the reading circuit before and after the XNOR, AND and NAND logic calculation; specifically, Figure 6 Fig. 4(a) is a simulation result diagram of the memristor current in the reading circuit before and after the XNOR logic calculation when the logic input P is 0; and Fig. 4(b) is a simulation result diagram of the memristor current in the reading circuit before and after the XNOR logic calculation when the logic input P is 1. Figure 7 Fig. 5 is a simulation result diagram of the memristor current in the reading circuit before and after the AND logic calculation; wherein Fig. 5(a) is a simulation result diagram of the memristor current in the reading circuit before and after the AND logic calculation when the logic input P is 0; and Fig. 5(b) is a simulation result diagram of the memristor current in the reading circuit before and after the AND logic calculation when the logic input P is 1. Figure 8 ​The figures show the simulation results of the memristor current in the read circuit before and after NAND logic calculation; Figure (a) shows the simulation results of the memristor current in the read circuit before and after NAND logic calculation when the logic input P is 0; Figure (b) shows the simulation results of the memristor current in the read circuit before and after NAND logic calculation when the logic input P is 1. Similarly, it can be seen from the figures that the control scheme designed in this invention can accurately realize the logic operation results of XNOR, AND, and NAND.

[0100] In summary, the logic circuit composed of memristors and fixed resistors provided by this invention, in this embodiment, can implement any 16 Boolean logic functions in a single calculation operation by configuring different operating voltages on the four control terminals (T1, T2, T3, and T4) of the designed Boolean logic circuit. In the logic calculation, one input P is defined in resistance form as the resistance state of memristor M1 and in voltage form as the control terminals T1, T2, and T4; another input Q is defined as the resistance state of memristor M2; and the resistance state of memristor M3 serves as the output. Compared with existing logic methods, this scheme uses fewer calculation steps and fewer devices, while completely storing the input information in the non-volatile memristor state, improving computational efficiency and saving circuit area. Furthermore, the logic implementation method provided by this invention is non-destructive, which helps protect the integrity of the input information.

[0101] Secondly, the present invention provides a control method for the above-mentioned complete non-volatile Boolean logic circuit, used to perform logical operations on the input logic value P and / or the input logic value Q, including the following steps:

[0102] S1. Before performing logic operations: Set the output memristor to a high impedance state; when the input of the logic circuit includes the logic value P, set the input memristor 1 to the impedance state corresponding to the logic value P; when the input of the logic circuit includes the logic value Q, set the input memristor 2 to the impedance state corresponding to the logic value Q.

[0103] S2. During logic operations: control the selection state of the multiplexer, apply voltage A to input memristor 1, apply voltage B to input memristor 2, and apply voltage V to the output memristor. p Reading the resistance state of the output memristor is the result of the logic operation;

[0104] When the multiplexer selects path a, the controller applies voltage D to the resistor; the values ​​of voltages A, B, and D are determined by the logic value P and the type of logic operation, or solely by the type of logic operation; V set <V P <1.5*V set V set The threshold for a memristor to transition from a high-resistance state to a low-resistance state.

[0105] The related technical solutions are the same as the complete non-volatile Boolean logic operation circuit provided in the first aspect of this invention, and will not be described in detail here.

[0106] Thirdly, the present invention provides a logic cascading method based on the above-described complete non-volatile Boolean logic circuit, comprising:

[0107] In each level of logic operation, the output memristor in the previous level of logic operation is used as the input memristor 2 in the current level of logic operation, and the control method provided in the second aspect of the present invention is executed, thereby realizing logic cascading.

[0108] Alternatively, during each level of logic operation, the output memristor in the previous level of logic operation is used as the input memristor 1 in the current level of logic operation; when the current level of logic operation performs an operation related to the logic value P, the logic value corresponding to the resistance state of the output memristor in the previous level of logic operation is read as the input logic value P of the current level of logic operation, and the control method provided in the second aspect of the present invention is executed to realize logic cascading; when the current level of logic operation performs an operation unrelated to the logic value P, the control method provided in the second aspect of the present invention is directly executed to realize logic cascading.

[0109] Specifically, each stage of the cascaded circuit described above is identical to the complete non-volatile Boolean logic circuit provided in the second aspect of this invention. In one optional embodiment, the cascaded circuit can be a memristor array, with one row selected for logic cascading. One end of the word line of this row is connected to a resistor R, and the other end of the resistor is connected to a multiplexer. The multiplexer includes two paths, a and b, where path a is connected to the controller and path b is floating. Each stage of the cascaded circuit is a 3M-1R structure provided in the first aspect of this invention. During the logic operation of each stage, the output memristor in the previous stage's logic operation is used as one of the input memristors in the current stage's logic operation. By activating the bit line corresponding to the memristor array, the other two memristors in that row are selected as the other input memristor and output memristor.

[0110] by Figure 2 When performing logic cascading using the non-volatile Boolean logic circuit shown as an example, the result of the previous logic calculation is directly used as the input of the next logic operation. Since the output of the previous logic operation is stored in memristor M3 in the form of an impedance state, memristor M3, which stores the calculation result of the previous step, can be directly regarded as the input memristor 2 of the next logic calculation.

[0111] The logic cascading method provided by this invention is simple and easy to implement, and helps to realize more complex logic functions.

[0112] The related technical solution is the same as the control method of the complete non-volatile Boolean logic circuit provided in the second aspect of the present application, and will not be described here.

[0113] In a fourth aspect, the present application further provides a computer readable storage medium, which comprises a stored computer program, wherein when the computer program is run by a processor, the device where the storage medium is located is controlled to execute the control method of the complete non-volatile Boolean logic circuit provided in the second aspect of the present application and / or the logic cascading method provided in the third aspect of the present application.

[0114] The related technical solution is the same as the control method of the complete non-volatile Boolean logic circuit provided in the second aspect of the present application and the logic cascading method provided in the third aspect of the present application, and will not be described here.

[0115] Those skilled in the art can easily understand that the above description is only a preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A complete non-volatile Boolean logic circuit based on 3M-1R memristor, characterized by, The application relates to a complete non-volatile Boolean logic circuit for performing logical operation on input logical value P and / or input logical value Q; the complete non-volatile Boolean logic circuit comprises a controller, three identical memristors, a resistor and a multiplexer; the positive poles of the memristors are connected to the controller, and the negative poles are connected to the same word line WL; one end of the resistor is connected to the word line WL, and the other end is connected to the multiplexer; the multiplexer comprises a and b two paths, the a path is connected to the controller, and the b path is floating; one of the memristors is an output memristor, and the other two are input memristors, which are respectively input memristor 1 and input memristor 2. The controller is configured to, before the logic operation: set the output memristor to a high resistance state; when the input of the logic circuit comprises a logic value P, set the input memristor 1 to a resistance state corresponding to the logic value P; when the input of the logic circuit comprises a logic value Q, set the input memristor 2 to a resistance state corresponding to the logic value Q; during the logic operation: control the gating state of the multiplexer, and apply a voltage A to the input memristor 1, a voltage B to the input memristor 2, and a voltage V to the output memristor p , read the resistance state of the output memristor, which is the logic operation result. When the multiplexer selects the a path, the controller applies a voltage D to the resistor; the values of the voltages A, B and D are determined according to the logic value P and the logic operation type, or are determined according to only the logic operation type. ; V set is a threshold value for the memristor to change from a high resistance state to a low resistance state. When the logical operation type is true logical operation, the multiplexer selects the a path, the voltage A is 0V, the voltage B is 0V, and the voltage D is 0V. When the logic operation type is false logic operation, the multiplexer is enabled by the b path, voltage A takes the value of V P / 2, and voltage B takes the value of V P / 2. When the logic operation type is P logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A takes the value of 0V and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of 0V and the voltage B takes the value of 0V; When the logic operation type is Q logic operation, the multiplexer is enabled by the b path; and when the memristor M1 is in a high resistance state, the voltage A takes a value of V P / 2, and the voltage B takes a value of 0V; when the memristor M1 is in a low resistance state, the voltage A takes a value of V P / 2, and the voltage B takes a value of -V P / 2. When the logic operation type is the non-P logic operation, the multiplexer is enabled by the a path, the voltage A has the value of V P / 2, the voltage B has the value of 0V, and the voltage D has the value of 0V. When the logic operation type is non-Q logic operation, the multiplexer is enabled by the a path, voltage A is 0V, voltage B is V P / 2, and voltage D is 0V. When the logic operation type is AND logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A takes the value of 0V and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2 and the voltage B takes the value of -V P / 2. When the logic operation type is NAND logic operation, the multiplexer is enabled by the a path, the voltage D has a value of 0V; and when the logic value P is 0, the voltage A has a value of 0V and the voltage B has a value of 0V; when the logic value P is 1, the voltage A has a value of 0V and the voltage B has a value of V P / 2; When the logical operation type is or logical operation, the multiplexer selects the b path, the voltage A is 0V, and the voltage B is 0V. When the logic operation type is OR operation, the multiplexer is enabled by the a path, voltage A is V P / 2, voltage B is V P / 2, and voltage D is 0V. When the logic operation type is substantial implication logic operation, the multiplexer selects the a path, the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2. When the logic operation type is negative material implication logic operation, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; When the logic operation type is the contrapositive implication logic operation, when the logic value P is 0, the multiplexer selects the a path, the voltage A takes the value of 0V, the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V; when the logic value P is 1, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; When the logic operation type is the inverse negative material implication logic operation, the multiplexer selects the b path, the voltage A takes the value of V P / 2, and the voltage B takes the value of 0V. When the logic operation type is exclusive-OR logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A has a value of 0V and the voltage B has a value of 0V; when the logic value P is 1, the voltage A has a value of 0V and the voltage B has a value of V P / 2; When the logic operation type is the XNOR logic operation, the multiplexer is enabled by the a path, the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2.

2. The complete non-volatile Boolean logic circuit according to claim 1, wherein, The memristor comprises a high-resistance state and a low-resistance state; the high-resistance state corresponds to logical value "0", and the low-resistance state corresponds to logical value "1".

3. The complete non-volatile Boolean logic circuit according to claim 1, wherein, The resistance value of the resistor is between the high-resistance state resistance value and the low-resistance state resistance value of the memristor.

4. The complete non-volatile Boolean logic circuit according to claim 3, wherein, The resistance of the resistor is where R H is the high resistance value of the memristor, R L is the low resistance value of the memristor.

5. The control method of the complete non-volatile Boolean logic circuit according to any one of claims 1-4, which is used for performing logical operation on input logical value P and / or input logical value Q, and comprises the following steps: Before performing the logical operation: setting the output memristor to the high-resistance state; when the input of the logical circuit comprises logical value P, setting the input memristor 1 to the resistance state corresponding to the logical value P; when the input of the logical circuit comprises logical value Q, setting the input memristor 2 to the resistance state corresponding to the logical value Q; In performing a logical operation: control the gating state of the multiplexer, and apply voltage A to the input memristor 1, voltage B to the input memristor 2, and voltage V to the output memristor p , read the resistance state of the output memristor, which is the result of the logical operation. When the multiplexer selects the a path, the voltage D is applied to the resistor; the values of the voltages A, B and D are determined according to the logic value P and the logic operation type, or are determined according to only the logic operation type. ; V set is a threshold value for the memristor to change from a high resistance state to a low resistance state. When the logical operation type is true logical operation, the multiplexer selects the a path, the voltage A is 0V, the voltage B is 0V, and the voltage D is 0V. When the logic operation type is false logic operation, the multiplexer is enabled by the b path, voltage A takes the value of V P / 2, and voltage B takes the value of V P / 2. When the logic operation type is P logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A takes the value of 0V and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of 0V and the voltage B takes the value of 0V; When the logic operation type is Q logic operation, the multiplexer is enabled by the b path; and when the memristor M1 is in a high resistance state, the voltage A takes a value of V P / 2, and the voltage B takes a value of 0V; when the memristor M1 is in a low resistance state, the voltage A takes a value of V P / 2, and the voltage B takes a value of -V P / 2. When the logic operation type is the non-P logic operation, the multiplexer is enabled by the a path, the voltage A is V P / 2, the voltage B is 0V, and the voltage D is 0V. When the logic operation type is non-Q logic operation, the multiplexer is enabled by the a path, voltage A is 0V, voltage B is V P / 2, and voltage D is 0V. When the logic operation type is AND logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A takes the value of 0V and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2 and the voltage B takes the value of -V P / 2. When the logic operation type is NAND logic operation, the multiplexer is enabled by the a path, the voltage D has a value of 0V; and when the logic value P is 0, the voltage A has a value of 0V and the voltage B has a value of 0V; when the logic value P is 1, the voltage A has a value of 0V and the voltage B has a value of V P / 2; When the logical operation type is or logical operation, the multiplexer selects the b path, the voltage A is 0V, and the voltage B is 0V. When the logic operation type is OR operation, the multiplexer is enabled by the a path, voltage A is V P / 2, voltage B is V P / 2, and voltage D is 0V. When the logic operation type is substantial implication logic operation, the multiplexer selects the a path, the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of 0V; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2. When the logic operation type is negative material implication logic operation, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; When the logic operation type is the contrapositive implication logic operation, when the logic value P is 0, the multiplexer selects the a path, the voltage A takes the value of 0V, the voltage B takes the value of V P / 2, and the voltage D takes the value of 0V; when the logic value P is 1, the multiplexer selects the b path, the voltage A takes the value of 0V, and the voltage B takes the value of 0V. When the logic operation type is the inverse negative material implication logic operation, the multiplexer selects the b path, the voltage A takes the value of V P / 2, and the voltage B takes the value of 0V. When the logic operation type is exclusive-OR logic operation, the multiplexer is enabled by the b path; and when the logic value P is 0, the voltage A has a value of 0V and the voltage B has a value of 0V; when the logic value P is 1, the voltage A has a value of 0V and the voltage B has a value of V P / 2; When the logic operation type is the XNOR logic operation, the multiplexer is enabled by the a path, the voltage D takes the value of 0V; and when the logic value P is 0, the voltage A takes the value of 0V, and the voltage B takes the value of V P / 2; when the logic value P is 1, the voltage A takes the value of V P / 2, and the voltage B takes the value of -V P / 2.

6. The control method according to claim 5, characterized by The memristor comprises a high-resistance state and a low-resistance state; the high-resistance state corresponds to logical value "0", and the low-resistance state corresponds to logical value "1".

7. A method of cascading logic based on the complete non-volatile Boolean logic circuit of any one of claims 1-4, wherein, It comprises: Taking the output memristor in the previous logical operation as the input memristor 2 in the current logical operation, and performing the control method according to any one of claims 5-6, so as to realize logical cascade; Or, taking the output memristor in the previous logical operation as the input memristor 1 in the current logical operation; when the current logical operation performs operation related to logical value P, reading the logical value corresponding to the resistance state of the output memristor in the previous logical operation as the input logical value P of the current logical operation, and performing the control method according to any one of claims 5-6, so as to realize logical cascade; when the current logical operation performs operation irrelevant to logical value P, directly performing the control method according to any one of claims 5-6, so as to realize logical cascade.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises a stored computer program, wherein the computer program, when executed by a processor, controls a device in which the storage medium is located to perform the control method of the complete non-volatile Boolean logic circuit according to any one of claims 5-6 and / or the logic cascading method according to claim 7.

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