A wafer

Abstract

The present invention provides a wafer, relating to the field of chip technology, that can address the problem of being unable to fully monitor the thickness of an opaque film layer in an incomplete exposure unit. The wafer includes a first exposure unit and a second exposure unit; the second exposure unit is located at the periphery of the wafer; the number of chips in the second exposure unit is less than the number of chips in the first exposure unit; the wafer also includes: a first process monitoring pattern; at least one of the first process monitoring patterns is provided in the region of each chip in the second exposure unit and / or in the dicing lanes surrounding each chip; and the second exposure unit includes at least two chips.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a wafer. Background Art

[0002] Process monitoring is a crucial step in the wafer fabrication process, providing real-time feedback on the quality of the manufacturing process. This includes overlay accuracy, feature size, film thickness, and electrical properties.

[0003] Among them, the performance of the chip in the wafer is closely related to the thickness of the film layer in the chip. Therefore, during the wafer manufacturing process, the thickness of the film layer needs to be monitored in real time, and the process parameters are adjusted according to the monitoring results to ensure that the film thickness meets the design requirements. At present, the process monitoring method for the film thickness of the metal layer is to set a long strip of process monitoring pattern that is formed synchronously with the metal layer in the exposure unit (shot) processed by the mask on the wafer, and use the process monitoring pattern to monitor the film thickness of the metal layer. Since projection exposure usually uses the same mask to expose multiple exposure units on the wafer in sequence, the position of the process monitoring pattern in the exposure unit is relatively fixed. For an incomplete exposure unit located at the edge of the wafer, since the position of the process monitoring pattern may not be on the wafer, the incomplete exposure unit may not contain the process monitoring pattern. As a result, the film thickness of the metal layer in the incomplete exposure unit cannot be fully monitored. Summary of the Invention

[0004] The embodiments of the present application provide a wafer that can solve the problem of being unable to fully monitor the thickness of an opaque film layer in an incomplete exposure unit.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] An embodiment of the present application provides a wafer, comprising a first exposure unit and a second exposure unit; the second exposure unit is located at the periphery of the wafer, and both the first exposure unit and the second exposure unit cover an area on the wafer through a single exposure using a mask; the number of chips in the second exposure unit is less than the number of chips in the first exposure unit; the wafer further comprises: a first process monitoring pattern; the first process monitoring pattern is used to monitor the thickness of an opaque film layer in the chip, and the first process monitoring pattern is provided on the same layer as the opaque film layer; at least one first process monitoring pattern is provided in the region of each chip in the second exposure unit and / or on the scribe line surrounding each chip; and the second exposure unit comprises at least two chips. Because at least one first process monitoring pattern is provided in the region of each chip in the second exposure unit and / or on the scribe line surrounding each chip, each second exposure unit is provided with a corresponding first process monitoring pattern. Therefore, the thickness of the opaque film layer in each chip contained in the second exposure unit can be monitored by the first process monitoring pattern in the second exposure unit. In this way, the thickness of the opaque film layer in the second exposure unit of the wafer can be fully monitored. In addition, the embodiment of the present application is compatible with current wafer processing processes and does not increase process complexity.

[0007] In one possible embodiment, at least one first process monitoring pattern is provided in the region of each chip and / or on the dicing lanes surrounding each chip in the first exposure unit. Here, the thickness of the opaque film layer in the first exposure unit can be monitored using one or more first process monitoring patterns in the first exposure unit.

[0008] In one possible embodiment, the wafer further includes a second process monitoring pattern; each first exposure unit is provided with a corresponding second process monitoring pattern located on the dicing path; the second process monitoring pattern is used to monitor the thickness of an opaque film layer within the chip contained in the first exposure unit, and the second process monitoring pattern is provided on the same layer as the opaque film layer; the area of ​​the second process monitoring pattern is larger than the area of ​​the first process monitoring pattern. Here, the second process monitoring pattern within the first exposure unit can be used to monitor the thickness of the opaque film layer within the first exposure unit. Furthermore, the second process monitoring pattern can be used as a reference to determine the accuracy of the thickness of the opaque film layer within the first exposure unit obtained using the first process monitoring pattern.

[0009] In one possible embodiment, the wafer further includes a second process monitoring pattern; each second exposure unit is provided with a corresponding second process monitoring pattern located on the cutting path; the second process monitoring pattern is used to monitor the thickness of an opaque film layer in the chip contained in the second exposure unit, and the second process monitoring pattern is provided on the same layer as the opaque film layer; wherein the area of ​​the second process monitoring pattern is greater than the area of ​​the first process monitoring pattern. The second process monitoring pattern provided in the second exposure unit has the same technical effect as the second process monitoring pattern provided in the first exposure unit, and reference may be made to the above embodiment, and no further description is given here.

[0010] In one possible embodiment, the first process monitoring pattern includes a first bounding box and a plurality of parallel light-shielding strips disposed within the first bounding box. The plurality of parallel light-shielding strips are equivalent to a grating. By measuring and recording the diffraction spectrum of the grating and fitting the diffraction spectrum using a computer, the thickness of the light-shielding strips can be determined, thereby determining the thickness of the opaque film layer disposed on the same layer.

[0011] In one possible embodiment, the directions of the light shielding strips in the first process monitoring patterns corresponding to two adjacent opaque film layers are perpendicular to each other, so as to avoid mutual influence between the two adjacent first process monitoring patterns when monitoring the thickness of the corresponding opaque film layers.

[0012] In one possible embodiment, the second process monitoring pattern includes a second bounding box and a plurality of sequentially arranged second process monitoring sub-patterns disposed within the second bounding box; each second process monitoring sub-pattern includes a plurality of parallel light-shielding strips. Each second process monitoring sub-pattern is equivalent to a grating. By measuring and recording the diffraction spectrum of the grating and fitting the diffraction spectrum using a computer, the thickness of the light-shielding strips in the second process monitoring sub-pattern can be determined, thereby determining the thickness of the opaque film layer disposed on the same layer.

[0013] In one possible embodiment, the directions of the light shielding strips in the second process monitoring sub-patterns corresponding to two adjacent opaque film layers are perpendicular to each other, so as to avoid mutual influence between the two adjacent second process monitoring sub-patterns when monitoring the thickness of the corresponding opaque film layers.

[0014] In a possible implementation, the first limiting frame is in a polygonal or circular shape.

[0015] In one possible embodiment, a first process monitoring pattern is provided on each dicing lane around the chip. Thus, the thickness of the opaque film layer in the chip can be monitored using multiple first process monitoring patterns on each dicing lane around the chip, thereby ensuring the accuracy of the thickness of the opaque film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic structural diagram of a wafer provided in an embodiment of the present application;

[0017] Figure 2 A schematic diagram of the structure of a process monitoring graph provided by the prior art;

[0018] Figure 3 A schematic structural diagram of an exposure unit provided by the prior art;

[0019] Figure 4a A schematic diagram of the positional relationship between a first process monitoring pattern and a second exposure unit provided in an embodiment of the present application;

[0020] Figure 4b A schematic diagram of the positional relationship between another first process monitoring pattern and a second exposure unit provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the positional relationship between a first process monitoring pattern and a second exposure unit provided in another embodiment of the present application;

[0022] Figure 6 A schematic structural diagram of a first process monitoring graph provided in an embodiment of the present application;

[0023] Figure 7 A schematic structural diagram of a multi-layer first process monitoring pattern provided in an embodiment of the present application;

[0024] Figure 8 A diagram showing the positional relationship between a second exposure unit, a first process monitoring pattern, and a second process monitoring pattern provided in an embodiment of the present application;

[0025] Figure 9 A schematic structural diagram of a second process monitoring graph provided in an embodiment of the present application;

[0026] Figure 10 A schematic structural diagram of an N-layer second process monitoring pattern provided in an embodiment of the present application;

[0027] Figure 11a A schematic diagram of the positional relationship between a first process monitoring pattern and a first exposure unit provided in an embodiment of the present application;

[0028] Figure 11b A schematic diagram of the positional relationship between another first process monitoring pattern and a first exposure unit provided in an embodiment of the present application;

[0029] Figure 11c A schematic diagram of the positional relationship between a first process monitoring pattern and a first exposure unit provided in another embodiment of the present application;

[0030] Figure 12 A schematic diagram of the positional relationship between a second process monitoring pattern and a first exposure unit provided in an embodiment of the present application;

[0031] Figure 13 A schematic diagram of the positional relationship between a first exposure unit and a first process monitoring pattern and a second process monitoring pattern provided in an embodiment of the present application.

[0032] Reference numerals:

[0033] 10-wafer; 100-exposure unit; 100a-first exposure unit (complete exposure unit); 100b-first exposure unit (incomplete exposure unit); 101-cutting road; 102-process monitoring pattern; 1021-process monitoring sub-pattern; 1022-definition frame; 103-first process monitoring pattern; 1031-light shielding strip; 1032-first definition frame; 104-second process monitoring pattern; 1041-second process monitoring sub-pattern; 1042-second definition frame. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0035] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0036] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more, and "at least one" means one or more.

[0037] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] It should be understood that during wafer fabrication, photolithography is often used to create specific patterns on the wafer's material film layer. This process includes exposure, which can also be called a photocopying process. Exposure processes typically include contact exposure, proximity exposure, and projection exposure. Due to its higher precision, projection exposure is currently the dominant exposure method, particularly in the production of miniaturized chips. The photomask (also known as a reticle) used in projection exposure can only cover a small square area on the wafer at a time (the mask coverage area can be square or rectangular). After exposing one area, the mask moves to the next adjacent area, continuing exposure. This S-shaped scanning or stepping process covers the entire wafer. For a given product, the active area exposed each time is fixed and repeated in the vertical and horizontal directions of the wafer. Each exposed area is called a shot, and the area or coverage area of ​​each exposure can also be called an exposure unit. In projection exposure, each mask layer is aligned with the previous mask layer, and the exposure areas must overlap with each other with high precision. Because each chip (also called a die) has identical circuitry, the pattern on the photomask is identical. By properly designing the number of chips within a shot, the entire wafer can be exposed several times sequentially using the same photomask. Furthermore, since only one photomask is required, costs can be effectively controlled. By properly designing the number of chips within the photomask coverage area, efficiency can be balanced.

[0039] like Figure 1 As shown, since the shape of the wafer 10 is circular, during the exposure process when the wafer 10 is manufactured, the wafer 10 includes not only the complete exposure unit 100a but also an incomplete exposure unit 100b at the edge of the wafer 10. Figure 1 The chip in the complete exposure unit 100a is represented by "1", and the chip in the incomplete exposure unit 100b is represented by "2". In the prior art, the process monitoring method for the film thickness of the metal layer in the wafer 10 is to set a long strip process monitoring pattern in one exposure unit 100. Figure 2 As shown, in the prior art, a long strip of process monitoring pattern (for example, the long strip of process monitoring pattern can be a pad line) 102 includes a limit frame 1022 and a plurality of process monitoring sub-patterns 1021 arranged in sequence along one direction within the limit frame 1022. Figure 2 The diagram shows N process monitoring sub-patterns 1021. Since the process monitoring pattern 102 in the prior art is a long strip pattern including multiple process monitoring sub-patterns 1021 and has a large area, only one process monitoring pattern 102 can be provided in one exposure unit 100.

[0040] Based on the above projection exposure process, it can be seen that since projection exposure usually uses the same mask to sequentially expose multiple exposure units on a wafer, the position of the process monitoring pattern 102 set in each exposure unit 100 is the same. For the exposure unit 100b with an incomplete edge of the wafer 10, since the incomplete exposure unit 100b lacks some chips compared to the complete exposure unit 100a, some incomplete exposure units 100b may not be provided with the process monitoring pattern 102. For example, Figure 3 As shown, exposure unit 100 includes 3*2 (i.e., 3 rows and 2 columns) chips, and a long strip-shaped process monitoring pattern 102 is set on the cutting path 101 below the chip in the first row and first column of each exposure unit 100. However, for an incomplete exposure unit 100b that does not include the chip in the first row and first column, since the process monitoring pattern 102 is not set in the incomplete exposure unit 100b, the film thickness of the metal layer in the incomplete exposure unit 100b cannot be process-monitored. Therefore, the existing film thickness process monitoring method can only monitor the process of the complete exposure unit 100a. For the incomplete exposure unit 100b at the edge of the wafer 10, since some incomplete exposure units 100b are not provided with the process monitoring pattern, the existing technology cannot fully monitor the film thickness of the metal layer at the edge of the wafer 10.

[0041] Based on this, the embodiment of the present application provides a wafer 10, such as Figure 1 As shown, it includes: an exposure unit 100, the exposure unit 100 includes a first exposure unit 100a and a second exposure unit 100b; the second exposure unit 100b is located on the periphery of the wafer 10, and the first exposure unit 100a and the second exposure unit 100b both use a mask to expose the area covered on the wafer 10 in one time; the number of chips in the second exposure unit 100b is less than the number of chips in the first exposure unit 100a.

[0042] Here, the second exposure unit 100b is located at the periphery of the wafer 10, which means that there is no other exposure unit in at least one direction around the second exposure unit 100b. Figure 1 For example, the second exposure unit 100b has no other exposure units on its right side and above. For another example, the second exposure unit 100b' has no other exposure units on its left side and above.

[0043] It should be noted that, in the embodiment of the present application, the chip in the first exposure unit 100a is represented by "1", and the chip in the second exposure unit 100b is represented by "2". Figure 1 There may be incomplete chips on the side of the middle chip 2. For incomplete chips, Figure 1 No indication was given.

[0044] Here, since the number of chips in the second exposure unit 100b is less than the number of chips in the first exposure unit 100a, the second exposure unit 100b can be called an incomplete exposure unit 100b, and the first exposure unit 100a can be called a complete exposure unit 100a. The second exposure unit 100b lacks some chips relative to the first exposure unit 100a.

[0045] Furthermore, to improve exposure efficiency, the first exposure unit 100a includes m rows and n columns of chips, where m ≥ 2, n ≥ 2, and both m and n are positive integers. For example, the first exposure unit 100a includes 3*2 chips, i.e., chips in 3 rows and 2 columns. For another example, the first exposure unit 100a includes 10*8 chips, i.e., chips in 10 rows and 8 columns.

[0046] like Figure 4a 、 Figure 4b as well as Figure 5 As shown, the wafer 10 provided in this embodiment of the present application further includes a first process monitoring pattern 103, which is used to monitor the thickness of the opaque film layer in the chip. The first process monitoring pattern 103 is disposed on the same layer as the opaque film layer. At least one first process monitoring pattern 103 is disposed on the region of each chip and / or the dicing lanes surrounding each chip in the second exposure unit 100b; the second exposure unit 100b includes at least two chips.

[0047] The above-mentioned “opaque film layer” may be, for example, a metal layer or an opaque insulating layer, and the material of the insulating layer may be, for example, black resin or non-conductive graphite.

[0048] Here, for the second exposure unit 100b including only one chip, at least one first process monitoring pattern 103 is provided on the chip region and / or the dicing lanes around the chip in the second exposure unit 100b.

[0049] It should be understood that after the wafer 10 is manufactured, in order to separate multiple chips in the wafer 10, the wafer 10 needs to be cut. Therefore, the wafer 10 includes a cutting road 101 set between two adjacent chips, and the wafer 10 is cut along the cutting road 101 during cutting.

[0050] Here, the wafer 10 includes a plurality of chips and dicing streets 101 for separating the plurality of chips. The area occupied by each chip is referred to as the area of ​​the chip.

[0051] It should be noted that the setting position of the first process monitoring pattern 103 can be as follows: Figure 4aAs shown, at least one first process monitoring pattern 103 is provided in the region of each chip in the second exposure unit 100b, that is, the first process monitoring pattern 103 is provided inside the chip; it may also be as shown in FIG. Figure 4b As shown, at least one first process monitoring pattern 103 is provided on the cutting path 101 around each chip in the second exposure unit 100b; of course, it can also be as follows Figure 5 As shown, each chip in the second exposure unit 100 b is provided with at least one first process monitoring pattern 103 not only in the area where the chip is located, but also on the dicing street 101 around the chip.

[0052] It should be understood that the first process monitoring pattern 103 is disposed on the dicing street 101, that is, the first process monitoring pattern 103 is completely located on the dicing street 101. For a dicing street 101 between two adjacent chips, the first process monitoring pattern 103 on the dicing street 101 can be considered as the first process monitoring pattern 103 disposed on the dicing street 101 surrounding one of the chips, and can also be considered as the first process monitoring pattern 103 disposed on the dicing street 101 surrounding the other chip.

[0053] Furthermore, the first process monitoring pattern 103 may be provided on at least one of the multiple scribe lines 101 around the chip. In some embodiments, each of the multiple scribe lines 101 around the chip is provided with a first process monitoring pattern 103. For example, if there are four scribe lines 101 around the chip, each of the four scribe lines 101 is provided with a first process monitoring pattern 103. In this way, the thickness of the opaque film layer in the chip can be monitored using the multiple first process monitoring patterns 103 on each of the scribe lines 101 around the chip to ensure the accuracy of the thickness of the obtained opaque film layer.

[0054] Here, the first process monitoring pattern 103 is set on the dicing street 101. Since the material on the dicing street 101 is removed after the wafer 10 is cut into chips, the first process monitoring pattern 103 can be prevented from occupying the design space of the chip.

[0055] It should be understood that the first process monitoring pattern 103 provided in the wafer 10 should not affect the circuit design and function of the chip.

[0056] On this basis, the first process monitoring pattern 103 is provided on the same layer as the opaque film layer, that is, the first process monitoring pattern 103 and the opaque film layer are manufactured synchronously. In this way, the first process monitoring pattern 103 and the opaque film layer are made of the same material and have the same thickness.

[0057] It should be noted that when the wafer 10 includes multiple layers of opaque film layers, for the opaque film layers whose thickness needs to be monitored, the first process monitoring graphic 103 can be produced at the same time as the opaque film layers are produced, and after the opaque film layers and the first process monitoring graphic 103 are produced, since at least one first process monitoring graphic 103 is provided in the area of ​​each chip in the second exposure unit 100b and / or on the cutting path 101 around each chip, each second exposure unit 100b corresponds to at least one first process monitoring graphic 103. In this way, the thickness of the opaque film layer in the second exposure unit 100b can be obtained by using the at least one first process monitoring graphic 103 in the second exposure unit 100b, and it can be determined whether the thickness of the obtained opaque film layer meets the design requirements. If not, the process is adjusted according to the thickness of the obtained opaque film layer so that the thickness of the opaque film layer meets the design requirements.

[0058] In some embodiments, as Figure 6 As shown, the structure of the first process monitoring pattern 103 includes a first limiting frame 1032 and a plurality of parallel light shielding strips 1031 disposed in the first limiting frame 1032 .

[0059] Here, the first limiting frame 1032 and the light shielding strip 1031 are made of the same material and are manufactured simultaneously.

[0060] In some embodiments, the shape of the first bounding box 1032 is a polygon or a circle, such as a square or a hexagon.

[0061] Because the first process monitoring pattern 103 comprises multiple parallel light-shielding strips 1031, it is equivalent to a grating. The specific process of "obtaining the thickness of the opaque film layer in the second exposure unit 100b using at least one first process monitoring pattern 103 in the second exposure unit 100b" is as follows: after the opaque film layer and the first process monitoring pattern 103 are simultaneously produced, the first process monitoring pattern 103 is found, aligned with the first process monitoring pattern 103, and the diffraction spectrum of the grating is measured and recorded. Using a computer to fit the diffraction spectrum, the thickness of the light-shielding strips 1031, i.e., the thickness of the first process monitoring pattern 103, can be obtained. Since the first process monitoring pattern 103 and the opaque film layer it monitors have the same thickness, the thickness of the opaque film layer can be obtained.

[0062] In addition, when the opaque film layer in the second exposure unit 100b is arranged in the same layer as the multiple first process monitoring patterns 103, the thickness of the opaque film layer in the second exposure unit 100b can be obtained using one of the first process monitoring patterns 103 in the second exposure unit 100b. Alternatively, multiple thickness values ​​of the opaque film layer in the second exposure unit 100b can be obtained using the multiple first process monitoring patterns 103 in the second exposure unit 100b, and then the multiple thickness values ​​can be averaged to obtain the thickness of the opaque film layer in the second exposure unit 100b. In this way, the accuracy of the obtained thickness of the opaque film layer can be improved.

[0063] Alternatively, the opaque film layer and the first process monitoring pattern 103 may be fabricated illustratively in the following steps: first, forming an insulating film; then, patterning the insulating film to form an insulating layer comprising a first groove, a plurality of parallel second grooves, and a third groove surrounding the second grooves, wherein the first groove and the orthographic projection of the opaque film layer to be formed on the substrate completely overlap; then, forming an opaque film, such as a metal film; and finally, removing the metal film outside the first, second, and third grooves, i.e., forming a metal layer within the first groove, forming metal lines within the second groove, and forming a first limiting frame 1032 within the third groove. The plurality of parallel metal lines and the first limiting frame 1032 surrounding the metal lines constitute the first process monitoring pattern 103. It should be understood that the depth of the first, second, and third grooves should be greater than or equal to the designed thickness of the metal film.

[0064] It should be noted that when the wafer 10 includes multiple layers of stacked opaque film layers, multiple layers of stacked first process monitoring patterns 103 may be provided. Each layer of the first process monitoring pattern 103 is used to monitor the thickness of the opaque film layer provided on the same layer. To avoid the first process monitoring pattern 103 occupying a large space, in some embodiments, the space occupied by the multiple layers of the first process monitoring pattern 103 overlaps.

[0065] On this basis, when the wafer 10 includes multiple layers of stacked opaque film layers and multiple layers of stacked first process monitoring patterns 103, in order to avoid the mutual influence of the two first process monitoring patterns 103 corresponding to the two adjacent opaque film layers when obtaining the thickness of the opaque film layer provided on the same layer using the first process monitoring pattern 103, in some embodiments, the directions of the shading strips 1031 in the first process monitoring patterns 103 corresponding to the two adjacent opaque film layers are not parallel. Furthermore, in order to improve the accuracy of the obtained thickness of the opaque film layer, in some examples, such as Figure 7 As shown, the directions of the shading strips 1031 in the first process monitoring pattern 103 corresponding to two adjacent opaque film layers are perpendicular to each other.

[0066] Figure 7 Six layers of first process monitoring graphics 103 are shown, namely the first layer first process monitoring graphics 103a, the second layer first process monitoring graphics 103b, the third layer first process monitoring graphics 103c, the fourth layer first process monitoring graphics 103d, the fifth layer first process monitoring graphics 103e, and the sixth layer first process monitoring graphics 103f.

[0067] An embodiment of the present application provides a wafer 10, comprising a first exposure unit 100a and a second exposure unit 100b. The second exposure unit 100b is located peripherally of the first exposure unit 100a, and both the first exposure unit 100a and the second exposure unit 100b cover an area on the wafer 10 using a single exposure mask. The number of chips in the second exposure unit 100b is less than the number of chips in the first exposure unit 100a. Wafer 10 also includes a first process monitoring pattern 103, which is used to monitor the thickness of an opaque film layer within the chip, and is disposed on the same layer as the opaque film layer. At least one first process monitoring pattern 103 is disposed in the area of ​​each chip in the second exposure unit 100b and / or on the dicing lanes 101 surrounding each chip. The second exposure unit 100b includes at least two chips. Compared to the prior art method of providing a long strip-shaped process monitoring pattern 102 in one exposure unit 100, since the second exposure unit 100b has fewer chips than the first exposure unit 100a, some second exposure units 100b may not be provided with a process monitoring pattern 102, resulting in an inability to fully monitor the film thickness of the second exposure unit 100b in the wafer 10. In contrast, in the embodiment of the present application, since at least one first process monitoring pattern 103 is provided in the region of each chip in the second exposure unit 100b and / or on the dicing street 101 surrounding each chip, each second exposure unit 100b is provided with a corresponding first process monitoring pattern 103. Therefore, the thickness of the opaque film layer in the chip contained in each second exposure unit 100b can be monitored by the first process monitoring pattern 103 in the second exposure unit 100b. In this way, the thickness of the opaque film layer in the second exposure unit 100b in the wafer 10 can be fully monitored. Furthermore, the embodiment of the present application is compatible with the current wafer 10 processing process and does not increase process complexity.

[0068] In some embodiments, as Figure 8As shown, the wafer 10 also includes a second process monitoring pattern 104; a second process monitoring pattern 104 located on the cutting path 101 is correspondingly set in each second exposure unit 100b; the second process monitoring pattern 104 is used to monitor the thickness of the opaque film layer in the chip contained in the second exposure unit 100b, and the second process monitoring pattern 104 is set in the same layer as the opaque film layer; wherein, the area of ​​the second process monitoring pattern 104 is larger than the area of ​​the first process monitoring pattern 103.

[0069] Here, the second process monitoring pattern 104 is arranged at a position that does not affect the circuit design and function of the chip.

[0070] It should be understood that since the second exposure unit 100b is an incomplete exposure unit, the second exposure unit 100b lacks some chips relative to the first exposure unit 100a, and the position of the second process monitoring pattern 104 in the second exposure unit 100b is fixed, so some second exposure units 100b may not be provided with the second process monitoring pattern 104. For example, refer to Figure 8 In the exposure unit 100, which includes chips in three rows and two columns, a second process monitoring pattern 104 is provided on the dicing street 101 between the chips in the first row and first column and the chips in the second row and first column in the second exposure unit 100b. For the second exposure unit 100b that does not include the chips in the first row and first column and the chips in the second row and first column, no second process monitoring pattern 104 is provided.

[0071] When the second exposure unit 100b includes the second process monitoring pattern 104, the second process monitoring pattern 104 can be used to monitor the thickness of the opaque film layer in the second exposure unit 100b, and the first process monitoring pattern 103 can also be used to monitor the thickness of the opaque film layer in the second exposure unit 100b.

[0072] It should be noted that the second process monitoring pattern 104 in the embodiment of the present application can be the same as the process monitoring pattern 102 in the prior art. Based on this, since the current method of monitoring the thickness of the opaque film layer using the process monitoring pattern 102 is very mature, in the embodiment of the present application, when the second exposure unit 100b includes the first process monitoring pattern 103 and the second process monitoring pattern 104, the second process monitoring pattern 104 can be used as a standard to determine whether the thickness of the opaque film layer in the second exposure unit 100b obtained using the first process monitoring pattern 103 is accurate. Specifically, if the thickness of the opaque film layer in the second exposure unit 100b obtained using the first process monitoring pattern 103 and the second process monitoring pattern 104 does not meet the design requirements, the process needs to be adjusted to ensure that the thickness of the opaque film layer meets the design requirements. If the thickness of the opaque film layer in the second exposure unit 100b obtained using the second process monitoring pattern 104 does not meet the design requirements, while the thickness of the opaque film layer in the second exposure unit 100b obtained using the first process monitoring pattern 103 meets the design requirements; or if the thickness of the opaque film layer in the second exposure unit 100b obtained using the second process monitoring pattern 104 meets the design requirements, while the thickness of the opaque film layer in the second exposure unit 100b obtained using the first process monitoring pattern 103 does not meet the design requirements, then it is necessary to adjust or modify the method of calculating the thickness of the opaque film layer in the second exposure unit 100b using the first process monitoring pattern 103 so that it is the same as the thickness of the opaque film layer in the second exposure unit 100b obtained using the second process monitoring pattern 104.

[0073] In some embodiments, as Figure 9 As shown, the second process monitoring pattern 104 includes a second limiting frame 1042 and a plurality of second process monitoring sub-patterns 1041 arranged in sequence within the second limiting frame 1042 ; wherein each second process monitoring sub-pattern 1041 includes a plurality of light shielding strips 1031 arranged in parallel.

[0074] It should be noted that the light shielding strips 1031 in each second process monitoring sub-pattern 1041 in the second process monitoring pattern 104 are parallel.

[0075] In some embodiments, the second bounding box 1042 is in the shape of a polygon or a circle, such as a square or a hexagon.

[0076] Here, one or more second process monitoring sub-patterns 1041 in the second process monitoring pattern 104 can be used to monitor the thickness of an opaque film layer disposed on the same layer as the second process monitoring pattern 104. Each second process monitoring sub-pattern 1041 is equivalent to a grating. The method for obtaining the thickness of the opaque film layer using the second process monitoring sub-pattern 1041 is the same as the method for obtaining the thickness of the opaque film layer using the first process monitoring pattern 103 described above. For details, please refer to the above description and will not be repeated here.

[0077] In addition, the method for making each second process monitoring sub-pattern 1041 in the second process monitoring pattern 104 may refer to the method for making the first process monitoring pattern 103 , which will not be described in detail here.

[0078] In addition, when the wafer 10 includes multiple stacked opaque film layers, multiple stacked second process monitoring patterns 104 may be provided. One second process monitoring pattern 104 is used to monitor the thickness of an opaque film layer provided on the same layer.

[0079] On this basis, when the wafer 10 includes multiple layers of stacked opaque film layers and multiple layers of stacked second process monitoring patterns 104, in order to avoid mutual influence between the two second process monitoring patterns 104 corresponding to two adjacent opaque film layers when obtaining the thickness of the opaque film layer provided in the same layer using the second process monitoring patterns 104, in some embodiments, the directions of the light-shielding strips 1031 in the second process monitoring patterns 104 corresponding to the two adjacent opaque film layers are non-parallel. Furthermore, in order to improve the accuracy of the obtained thickness of the opaque film layer, in some examples, the directions of the light-shielding strips 1031 in the second process monitoring patterns 104 corresponding to the two adjacent opaque film layers are perpendicular to each other.

[0080] In the case where the wafer 10 includes multiple layers of second process monitoring patterns 104 stacked together, in order to prevent the second process monitoring patterns 104 from occupying a large space, in some embodiments, the spaces occupied by the multiple layers of second process monitoring patterns 104 overlap.

[0081] In some embodiments, if it is necessary to monitor the thickness of N opaque film layers in a chip, Figure 10As shown, the second process monitoring pattern 104 provided on the same layer as the first opaque film layer includes N second process monitoring sub-patterns 1041a arranged in sequence; the second process monitoring pattern 104 provided on the same layer as the second opaque film layer includes N-1 second process monitoring sub-patterns 1041b arranged in sequence, the shading strips in the second process monitoring sub-pattern 1041b are not parallel to the shading strips in the second process monitoring sub-pattern 1041a (for example, perpendicular to each other), and the N-1 second process monitoring sub-patterns 1041b arranged in sequence are not parallel to the shading strips in the second process monitoring sub-pattern 1041a (for example, perpendicular to each other), and the shading strips in ... The space occupied by the N-1 sequentially arranged second process monitoring sub-patterns 1041a overlaps with the space occupied by the N-1 sequentially arranged second process monitoring sub-patterns 1041a; the second process monitoring pattern 104 provided on the same layer as the third opaque film layer includes N-2 sequentially arranged second process monitoring sub-patterns 1041c, the shading strips in the second process monitoring sub-pattern 1041c are not parallel to the shading strips in the second process monitoring sub-pattern 1041b (for example, perpendicular to each other), and the space occupied by the N-2 sequentially arranged second process monitoring sub-patterns 1041c overlaps with the space occupied by the N-2 sequentially arranged second process monitoring sub-patterns 1041a. The space occupied by the second process monitoring sub-pattern 1041b overlaps; and by analogy, the second process monitoring pattern 104 disposed on the same layer as the N-2th opaque film layer includes three second process monitoring sub-patterns 1041d arranged in sequence; the second process monitoring pattern 104 disposed on the same layer as the N-1th opaque film layer includes two second process monitoring sub-patterns 1041e arranged in sequence, and the shading strips in the second process monitoring sub-pattern 1041e are not parallel to the shading strips in the second process monitoring sub-pattern 1041d (for example, perpendicular to each other), and this The space occupied by the two second process monitoring sub-graphics 1041e overlaps with the space occupied by the two second process monitoring sub-graphics 1041d; the second process monitoring graphic 104 arranged on the same layer as the Nth opaque film layer includes one second process monitoring sub-graphic 1041f, the shading strip in the second process monitoring sub-graphic 1041f is not parallel to the shading strip in the second process monitoring sub-graphic 1041e (for example, perpendicular to each other), and the space occupied by the second process monitoring sub-graphic 1041f overlaps with that occupied by one second process monitoring sub-graphic 1041e.

[0082] Based on the above, for the first exposure unit 100a in the wafer 10, the following three methods can be used to set the process monitoring pattern to monitor the thickness of the opaque film layer in the chip included in the first exposure unit 100a.

[0083] Method 1:

[0084] like Figure 11a 、 Figure 11b and Figure 11c As shown, at least one first process monitoring pattern 103 is provided in the region of each chip and / or on the dicing lanes around each chip in the first exposure unit 100 a .

[0085] Here, it can be Figure 11a As shown, at least one first process monitoring pattern 103 is provided in the region of each chip in the first exposure unit 100a, that is, the first process monitoring pattern 103 is provided inside the chip; it may also be as shown in FIG. Figure 11b As shown, at least one first process monitoring pattern 103 is provided on the cutting path 101 around each chip in the first exposure unit 100a; of course, it can also be as follows Figure 11c As shown, each chip in the first exposure unit 100 a is provided with at least one first process monitoring pattern 103 not only in the area where the chip is located, but also on the dicing street 101 around the chip.

[0086] In some embodiments, the sum of the number of first process monitoring patterns 103 provided on the region of any chip on the wafer 10 and the scribe lines 101 surrounding that chip is the same as the number of first process monitoring patterns 103 provided on the region of another chip and the scribe lines 101 surrounding that chip, and the position of the first process monitoring patterns 103 provided on the region of any chip on the wafer 10 and the scribe lines 101 surrounding that chip relative to that chip is the same as the position of the first process monitoring patterns 103 provided on the region of another chip and the scribe lines 101 surrounding that chip relative to that chip. The aforementioned "any chip" and "another chip" can both refer to chips in the first exposure unit 100a; they can also both refer to chips in the second exposure unit 100b; of course, one chip can be in the first exposure unit 100a and the other can be in the second exposure unit 100b.

[0087] It should be noted that since the sum of the number of first process monitoring graphics 103 set on the area of ​​any chip in the wafer 10 and the cutting road 101 around the chip is the same as the number of first process monitoring graphics 103 set on the area of ​​another chip and the cutting road 101 around the chip, and the position of the first process monitoring graphics 103 set on the area of ​​any chip in the wafer 10 and the cutting road 101 around the chip relative to the chip is the same as the position of the first process monitoring graphics 103 set on the area of ​​another chip and the cutting road 101 around the chip relative to the chip, the first process monitoring graphics 103 set on the area of ​​any chip and the cutting road 101 around the chip can be completely overlapped with the first process monitoring graphics 103 set on the area of ​​another chip and the cutting road 101 around the chip after being moved upward, downward, left or right at the same time.

[0088] For example, reference Figure 4a and Figure 11a , a first process monitoring pattern 103 is set in the center area of ​​each chip. Figure 4b and Figure 11b Eight first process monitoring patterns 103 are set on the cutting lanes 101 around each chip, and the eight first process monitoring patterns 103 are respectively located on the four sides of the chip. The first process monitoring patterns 103 on the overlapping sides of two adjacent chips also overlap.

[0089] In the embodiment of the present application, since the sum of the number of first process monitoring graphics 103 set on the area of ​​any chip in the wafer 10 and the cutting road 101 around the chip is the same as the sum of the number of first process monitoring graphics 103 set on the area of ​​another chip and the cutting road 101 around the chip, and the position of the first process monitoring graphics 103 set on the area of ​​any chip in the wafer 10 and the cutting road 101 around the chip relative to the chip is the same as the position of the first process monitoring graphics 103 set on the area of ​​another chip and the cutting road 101 around the chip relative to the chip, during the production process of the wafer 10, the same mask can be used to produce the first process monitoring graphics 103 in the first exposure unit 100a and the second exposure unit 100b, thereby reducing production costs.

[0090] Method 2:

[0091] like Figure 12 As shown, the wafer also includes a second process monitoring pattern 104; a second process monitoring pattern 104 located on the cutting path 101 is correspondingly set in each first exposure unit 100a; the second process monitoring pattern 104 is used to monitor the thickness of the opaque film layer in the chip contained in the first exposure unit 100a, and the second process monitoring pattern 104 is set in the same layer as the opaque film layer; wherein, the area of ​​the second process monitoring pattern 104 is larger than the area of ​​the first process monitoring pattern 103.

[0092] Here, the second process monitoring pattern 104 is arranged at a position that does not affect the circuit design and function of the chip.

[0093] It should be noted that the structure and manufacturing method of the second process monitoring pattern 104 can refer to the above embodiment and will not be described in detail here.

[0094] Method 3

[0095] like Figure 13 As shown, at least one first process monitoring pattern 103 is provided in the area of ​​each chip in the first exposure unit 100a and / or on the cutting path around each chip, and a second process monitoring pattern 104 located on the cutting path 101 is correspondingly provided in each first exposure unit 100a.

[0096] Since the first exposure unit 100a includes the first process monitoring pattern 103 and the second process monitoring pattern 104, the first process monitoring pattern 103 can be used to monitor the thickness of the opaque film layer in the first exposure unit 100a, and the second process monitoring pattern 104 can also be used to monitor the thickness of the opaque film layer in the first exposure unit 100a.

[0097] In some embodiments, the first exposure unit 100a includes a second process monitoring pattern 104, and the second exposure unit 100b includes a first process monitoring pattern 103. In this case, the second process monitoring pattern 104 can be used to monitor the thickness of the opaque film layer in the first exposure unit 100a, while the first process monitoring pattern 103 can be used to monitor the thickness of the opaque film layer in the second exposure unit 100b. Since the first exposure unit 100a is a complete exposure unit, each first exposure unit 100a is provided with a second process monitoring pattern 104. Therefore, the second process monitoring pattern 104 can be used to fully monitor the thickness of the opaque film layer in the first exposure unit 100a. Furthermore, a single second process monitoring pattern 104 can be used to detect the thickness of all opaque film layers in the first exposure unit 100a, thereby improving detection efficiency. At least one first process monitoring pattern 103 is provided in the area of ​​each chip in the second exposure unit 100b and / or on the cutting path 101 around each chip. Therefore, a first process monitoring pattern 103 is provided in each second exposure unit 100b, thereby ensuring that the thickness of the opaque film layer in each second exposure unit 100b is fully monitored.

[0098] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A wafer, characterized in that: include: A first exposure unit and a second exposure unit; wherein the second exposure unit is located at the periphery of the wafer; the number of chips in the second exposure unit is less than the number of chips in the first exposure unit; The wafer further includes: a first process monitoring pattern; Wherein, at least one first process monitoring pattern is provided on the area of ​​each chip in the second exposure unit and / or the cutting lane around each chip; the second exposure unit includes at least two chips; The first process monitoring pattern is used to monitor the thickness of the opaque film layer in the chip, and the first process monitoring pattern and the opaque film layer in the chip are arranged in the same layer.

2. The wafer according to claim 1, wherein: At least one first process monitoring pattern is provided on a region of each chip in the first exposure unit and / or on a cutting path around each chip.

3. The wafer according to claim 1 or 2, characterized in that The wafer further includes a second process monitoring pattern; each of the first exposure units is correspondingly provided with a second process monitoring pattern located on the cutting path; The area of ​​the second process monitoring pattern is larger than the area of ​​the first process monitoring pattern.

4. The wafer according to claim 1 or 2, characterized in that The wafer further includes a second process monitoring pattern; each of the second exposure units is correspondingly provided with a second process monitoring pattern located on the cutting path; The second process monitoring pattern is used to monitor the thickness of an opaque film layer in the chip included in the second exposure unit, and the second process monitoring pattern is provided on the same layer as the opaque film layer; The area of ​​the second process monitoring pattern is larger than the area of ​​the first process monitoring pattern.

5. The wafer according to claim 1 or 2, characterized in that The first process monitoring pattern includes a first limiting frame and a plurality of parallel light-shielding strips arranged in the first limiting frame.

6. The wafer according to claim 5, characterized in that The directions of the shading strips in the first process monitoring pattern corresponding to two adjacent opaque film layers are perpendicular to each other.

7. The wafer according to claim 3, wherein: The second process monitoring graph includes a second limiting frame and a plurality of second process monitoring sub-graphs arranged in sequence and disposed within the second limiting frame; Each of the second process monitoring sub-patterns includes a plurality of light-shielding strips arranged in parallel.

8. The wafer according to claim 7, wherein: The directions of the shading strips in the second process monitoring sub-patterns corresponding to two adjacent opaque film layers are perpendicular to each other.

9. The wafer according to claim 5, characterized in that The first limiting frame is in a polygonal or circular shape.

10. The wafer according to claim 1 or 2, characterized in that The first process monitoring pattern is provided on each of the cutting lanes around the chip.

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