An LVDS pre-emphasis clock driver circuit with a capacitor

Abstract

The present invention relates to an LVDS pre-emphasis clock driver circuit with a capacitor, belonging to the field of microcircuit structures. The present invention includes an LVDS main signal structure path and a pre-emphasis signal path, wherein a capacitor is added to the pre-emphasis signal path. The input signal of the LVDS main path is connected to the input signal of the pre-emphasis path, and similarly, the output signal of the LVDS main path is connected to the output signal of the pre-emphasis path. The present invention has the advantages of simple structure, high efficiency and low power consumption.

Description

Technical Field

[0001] The present invention relates to a microcircuit structure, and in particular to an LVDS pre-emphasis clock driver circuit with adjustable pre-emphasis degree and capacitance. Background Art

[0002] The signal path of the LVDS driver circuit has the characteristic of low-pass. When a periodic square wave signal passes through the LVDS driver circuit, its high-frequency components will be greatly attenuated, and the rise / fall time of each output signal will become larger, and it cannot quickly flip the level following the input square wave signal, which hinders the transmission rate and quality of high-frequency data signals.

[0003] In communication devices and systems, due to the existence of distributed inductance and distributed capacitance in the transmission line during high-frequency transmission, the high-frequency components of the signal will be attenuated during transmission, resulting in the loss of the integrity of the communication signal. Summary of the Invention

[0004] In view of this, the present invention proposes an LVDS pre-emphasis clock driver circuit with capacitance. When the signal passes through the clock driver circuit, the high-frequency components of the signal are pre-enhanced, so as to cancel out the attenuation of the high-frequency components of the signal by the transmission line and ensure the integrity of the signal during transmission.

[0005] In order to achieve the above technical objectives, the technical solution adopted by the present invention is as follows:

[0006] An LVDS pre-emphasis clock driver circuit with capacitance includes an LVDS main path and a pre-emphasis signal path. The first input terminal, the second input terminal, the first output terminal, and the second output terminal of the LVDS main path and the pre-emphasis signal path are respectively connected correspondingly. The input signal passes through both the LVDS main path and the pre-emphasis signal path at the same time. The pre-emphasis signal path pre-emphasizes the signal, and the pre-emphasis signal is superimposed on the main path signal to achieve the pre-emphasis of the signal.

[0007] Further, the LVDS main path includes a first PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a fifth NMOS transistor; the gates of the fourth PMOS transistor and the first NMOS transistor are connected, and the connection end is the first input end of the differential signal. The gates of the fifth PMOS transistor and the second NMOS transistor are connected, and the connection end is the second input end of the differential signal. The drains of the fourth PMOS transistor and the first NMOS transistor are connected, and the connection end is the first output end of the differential signal. The drains of the fifth PMOS transistor and the second NMOS transistor are connected, and the connection end is the second output end of the differential signal. The sources of the fourth PMOS transistor, the fifth PMOS transistor, and the drain of the first PMOS transistor are connected. The gate of the first PMOS transistor is connected to the first EP control signal. The source of the first PMOS transistor is connected to the power supply. The sources of the first NMOS transistor, the second NMOS transistor, and the drain of the fifth NMOS transistor are connected. The gate of the fifth NMOS transistor is connected to the first EN control signal. The source of the fifth NMOS transistor is connected to the ground;

[0008] Further, the pre - emphasis signal path includes a second PMOS transistor, a third PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; the gates of the sixth PMOS transistor and the third NMOS transistor are connected, and the connection end is the first input end of the differential signal. The gates of the seventh PMOS transistor and the fourth NMOS transistor are connected, and the connection end is the second input end of the differential signal. The drains of the sixth PMOS transistor and the third NMOS transistor are connected, and the connection end is the first output end of the differential signal. The drains of the seventh PMOS transistor and the fourth NMOS transistor are connected, and the connection end is the second output end of the differential signal. The drain of the second PMOS transistor, the source of the sixth PMOS transistor, and one end of the first capacitor are connected. The drain of the third PMOS transistor, the source of the seventh PMOS transistor, and one end of the second capacitor are connected. The gates of the second PMOS transistor and the third PMOS transistor are both connected to the second EP control signal. The sources of the second PMOS transistor and the third PMOS transistor are both connected to the power supply. The other end of the first capacitor, the other end of the second capacitor, one end of the first resistor, and one end of the second resistor are connected. The other end of the first resistor is connected to the power supply. The other end of the second resistor is connected to the ground. The source of the third NMOS transistor, the drain of the sixth NMOS transistor, and one end of the third capacitor are connected. The source of the fourth NMOS transistor, the drain of the seventh NMOS transistor, and one end of the fourth capacitor are connected. The other end of the third capacitor, the other end of the fourth capacitor, one end of the third resistor, and one end of the fourth resistor are connected. The other end of the third resistor is connected to the power supply. The other end of the fourth resistor is connected to the ground;

[0009] Further, a 100-ohm fifth resistor is also connected between the differential signal outputs of the LVDS main path and the pre-emphasis signal path. One end of the fifth resistor is connected to the first output terminal, and the other end of the fifth resistor is connected to the second output terminal.

[0010] Compared with the existing pre-emphasis technology, the advantages of the present invention are as follows:

[0011] 1. In the present invention, the degree of pre-emphasis is increased through the charging and discharging processes of multiple capacitors, rather than by adding more current sources.

[0012] 2. During the process of the LVDS signal changing between high and low levels, the capacitors will undergo rapid charging and discharging processes, enabling the signals output by the LVDS driving circuit to achieve the purpose of pre-emphasis.

[0013] 3. The present invention adopts an LVDS pre-emphasis clock driving circuit with capacitors, and obtains a higher pre-emphasis output signal with less power consumption and a simple structure.

[0014] 4. The present invention applies the LVDS pre-emphasis clock driving circuit to interface circuits such as fan-out buffers, multiplexers, and demultiplexers, which can improve their ability to transmit high-frequency signals. The interface circuit can play a buffering and relaying role in large circuits such as frequency synthesizers, data converters, and radio frequency transceiver systems, and can also be widely applied to the clock distribution of high-speed sampling digital frequency storage boards, signal generation boards, high-speed digital circuits, and analog-digital hybrid circuits.

[0015] In summary, the present invention adopts a structure with capacitors, realizes a pre-emphasis signal generation circuit based on a current mode, and has the advantages of simple structure, high efficiency, and low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit of the existing LVDS current pre-emphasis mode.

[0017] Figure 2 It is an LVDS pre-emphasis clock driving circuit with capacitors in the embodiment of the present invention.

[0018] Figure 3 It is an output signal weighted by the present invention. EMBODIMENTS

[0019] In order to make the purpose, technical solutions, and application advantages of the present invention clearer and more understandable, the following further elaborates on the specific embodiments of the present invention with reference to the accompanying drawings.

[0020] As Figure 2As shown, a LVDS pre-emphasis clock driver circuit with a capacitor includes a LVDS main path and a pre-emphasis signal path. A capacitor is added to the pre-emphasis signal path. During signal transmission, signal pre-emphasis is achieved through the charging and discharging of the capacitor. The input signal of the LVDS main path is connected to the input signal of the pre-emphasis path, and similarly, the output signal of the LVDS main path is connected to the output signal of the pre-emphasis path.

[0021] The LVDS main path part includes PMOS transistor MP1, PMOS transistor MP4, PMOS transistor MP5, NMOS transistor MN1, NMOS transistor MN2, and NMOS transistor MN5. The gates of PMOS transistor MP4 and NMOS transistor MN1 are connected, and the connection end is the input IN of one end of the differential signal. The gates of PMOS transistor MP5 and NMOS transistor MN2 are connected, and the connection end is the input IP of the other end of the differential signal. The drains of PMOS transistor MP4 and NMOS transistor MN1 are connected, and the connection end is the output ON of one end of the differential signal. The drains of PMOS transistor MP5 and NMOS transistor MN2 are connected, and the connection end is the output OP of the other end of the differential signal. The sources of PMOS transistor MP4, PMOS transistor MP5, and the drain of PMOS transistor MP1 are connected. The gate of PMOS transistor MP1 is connected to the control signal BIAS_EP1, and the source of PMOS transistor MP1 is connected to the power supply terminal VCC. The sources of NMOS transistor MN1, NMOS transistor MN2, and the drain of NMOS transistor MN5 are connected. The gate of NMOS transistor MN5 is connected to the control signal BIAS_EN1, and the source of NMOS transistor MN5 is connected to the ground terminal GND.

[0022] The pre - emphasis path includes PMOS transistors MP2, MP3, MP6, MP7, NMOS transistors MN3, MN4, MN6, MN7, capacitors C1, C2, C3, C4, resistors R1, R2, R3, R4; the gates of PMOS transistor MP6 and NMOS transistor MN3 are connected and the connection end is the input IN of one end of the differential signal, the gates of PMOS transistor MP7 and NMOS transistor MN4 are connected and the connection end is the input IP of the other end of the differential signal, the drains of PMOS transistor MP6 and NMOS transistor MN3 are connected and the connection end is the output ON of one end of the differential signal, the drains of PMOS transistor MP7 and NMOS transistor MN4 are connected and the connection end is the output OP of the other end of the differential signal, the drain of PMOS transistor MP2, the source of PMOS transistor MP6 and one end of capacitor C1 are connected, the drain of PMOS transistor MP3, the source of PMOS transistor MP7 and one end of capacitor C2 are connected, the gates of PMOS transistor MP2 and PMOS transistor MP3 are both connected to the control signal BIAS_EP2, the sources of PMOS transistor MP2 and PMOS transistor MP3 are both connected to the power supply VCC, the other end of capacitor C1, the other end of capacitor C2, one end of resistor R1 and one end of resistor R2 are connected, the other end of resistor R1 is connected to the power supply VCC, the other end of resistor R2 is connected to the ground GND, the source of NMOS transistor MN3, the drain of NMOS transistor MN6 and one end of capacitor C3 are connected, the source of NMOS transistor MN4, the drain of NMOS transistor MN7 and one end of capacitor C4 are connected, the other end of capacitor C3, the other end of capacitor C4, one end of resistor R3 and one end of resistor R4 are connected, the other end of resistor R3 is connected to the power supply VCC, the other end of resistor R4 is connected to the ground GND.

[0023] The input IN, input IP, output ON, and output OP of the LVDS main path and the pre - emphasis path are connected. A 100 - ohm resistor is connected between the differential signal outputs, which is resistor R5. One end of resistor R5 is connected to ON, and the other end of resistor R5 is connected to OP.

[0024] Figure 1 Shown is a circuit of an existing LVDS current pre - emphasis mode. The LVDS driving circuit is as Figure 1 shown in the LVDS part, and the pre - emphasis part is Figure 1 the latter half. If the existing pre - emphasis circuit wants to achieve a higher degree of pre - emphasis signal, it needs to control the NMOS transistors MN6 and MN7 to increase the current through the BIAS_EN2 signal. This method will increase the power consumption of the overall circuit.

[0025] Figure 2Shown is the innovative LVDS pre - emphasis clock driver circuit with capacitors in this embodiment. During the process of the clock input signal changing between high and low, capacitors C1, C2, C3, and C4 continuously charge and discharge, increasing the voltage at the moment of the high - low switching of the output signal, thereby achieving the goal of increasing the LVDS signal pre - emphasis level without increasing power consumption. Figure 3 That is the waveform of the LVDS output signal after pre - emphasis of the present invention.

[0026] Figure 2 The shown pre - emphasis circuit with capacitors obtains the DC level of one - end plates of appropriate capacitors C1 and C2 by series voltage division of resistors R1 and R2, ensuring the charging and discharging of the capacitors when the signal flips. Similarly, the DC level of one - end plates of appropriate capacitors C3 and C4 is obtained by series voltage division of resistors R3 and R4, ensuring the charging and discharging of the capacitors when the signal flips; when the differential input signal is stable, the capacitors do not charge or discharge, so the differential output is also a stable level. When the differential signal input terminal IN changes from high to low and the differential signal input terminal IP changes from low to high, PMOS transistor MP6 and NMOS transistor MN4 are turned on, and PMOS transistor MP7 and NMOS transistor MN3 are turned off. The LVDS current flow is from PMOS transistor MP6 to output ON, through resistor R5 to output OP, and through NMOS transistor MN4. When PMOS transistor MP6 is turned on, the source voltage of PMOS transistor MP6 decreases, and at this time capacitor C1 discharges. When PMOS transistor MP7 is turned off, the source voltage of PMOS transistor MP7 increases, and at this time capacitor C2 charges. When NMOS transistor MN3 is turned off, the source voltage of NMOS transistor MN3 decreases, and at this time capacitor C3 discharges. When NMOS transistor MN4 is turned on, the source voltage of NMOS transistor MN4 increases, and at this time capacitor C4 charges. Similarly, when the differential signal input terminal IN changes from low to high and the differential signal input terminal IP changes from high to low, capacitors C1 and C3 charge, and capacitors C2 and C4 discharge. The charging and discharging of the capacitors during the change of the level signal will increase the pre - emphasis level of the differential output signal, achieving the purpose of this design. The output signal weighted by the LVDS pre - emphasis clock driver circuit with capacitors is as Figure 3 shown.

[0027] The above - described embodiments are intended to facilitate the understanding of the innovative essence of the present invention, but not to limit the diverse implementation manners and the scope of the claimed rights required by the present invention. Any design that understands the present invention and makes equivalent structural changes or component replacements according to the above - described embodiments and can achieve the same purpose and effect shall be regarded as an infringement of the protected content of this patent application.

Claims

1. An LVDS pre-emphasis clock driver circuit with a capacitor, characterized in that, It includes an LVDS main path and a pre-emphasis signal path. The first input terminals, second input terminals, first output terminals, and second output terminals of the LVDS main path and the pre-emphasis signal path are respectively connected correspondingly. The input signal passes through both the LVDS main path and the pre-emphasis signal path at the same time. The pre-emphasis signal path pre-emphasizes the signal, and the pre-emphasis signal is superimposed on the main path signal to achieve signal pre-emphasis; The LVDS main path includes a first PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a fifth NMOS transistor; the gates of the fourth PMOS transistor and the first NMOS transistor are connected and the connection end is the first input terminal of the differential signal, the gates of the fifth PMOS transistor and the second NMOS transistor are connected and the connection end is the second input terminal of the differential signal, the drains of the fourth PMOS transistor and the first NMOS transistor are connected and the connection end is the first output terminal of the differential signal, the drains of the fifth PMOS transistor and the second NMOS transistor are connected and the connection end is the second output terminal of the differential signal, the sources of the fourth PMOS transistor, the fifth PMOS transistor and the drain of the first PMOS transistor are connected, the gate of the first PMOS transistor is connected to the first EP control signal, the source of the first PMOS transistor is connected to the power supply, the sources of the first NMOS transistor, the second NMOS transistor and the drain of the fifth NMOS transistor are connected, the gate of the fifth NMOS transistor is connected to the first EN control signal, and the source of the fifth NMOS transistor is connected to the ground; The pre-emphasis signal path includes a second PMOS transistor, a third PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; the gates of the sixth PMOS transistor and the third NMOS transistor are connected, and the connection end is the first input end of the differential signal. The gates of the seventh PMOS transistor and the fourth NMOS transistor are connected, and the connection end is the second input end of the differential signal. The drains of the sixth PMOS transistor and the third NMOS transistor are connected, and the connection end is the first output end of the differential signal. The drains of the seventh PMOS transistor and the fourth NMOS transistor are connected, and the connection end is the second output end of the differential signal. The drain of the second PMOS transistor, the source of the sixth PMOS transistor, and one end of the first capacitor are connected. The drain of the third PMOS transistor, the source of the seventh PMOS transistor, and one end of the second capacitor are connected. The gates of the second PMOS transistor and the third PMOS transistor are both connected to the second EP control signal. The sources of the second PMOS transistor and the third PMOS transistor are both connected to the power supply. The other end of the first capacitor, the other end of the second capacitor, one end of the first resistor, and one end of the second resistor are connected. The other end of the first resistor is connected to the power supply, and the other end of the second resistor is connected to the ground. The source of the third NMOS transistor, the drain of the sixth NMOS transistor, and one end of the third capacitor are connected. The source of the fourth NMOS transistor, the drain of the seventh NMOS transistor, and one end of the fourth capacitor are connected. The other end of the third capacitor, the other end of the fourth capacitor, one end of the third resistor, and one end of the fourth resistor are connected. The other end of the third resistor is connected to the power supply, and the other end of the fourth resistor is connected to the ground.

2. The LVDS pre-emphasis clock driving circuit with a capacitor according to claim 1, wherein A 100-ohm fifth resistor is also connected between the differential signal outputs of the LVDS main path and the pre-emphasis signal path. One end of the fifth resistor is connected to the first output end, and the other end of the fifth resistor is connected to the second output end.

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