A small-size storage device adapter plate, PCB board structure and electronic device

Abstract

The application discloses a small-size storage device adapter plate, a PCB structure and electronic equipment, and relates to the technical field of storage devices. The small-size storage device adapter plate comprises a memory chip body, two adapter plates, a measuring point pad and the like. The two adapter plates are stacked, the main surfaces of the adapter plates are attached to the surface of the memory chip body, the measuring point pad is arranged on the side surface of the adapter plate, the side surface is arranged on the edge of the main surface of the adapter plate and is perpendicular to the main surface, the two adapter plates are both provided with the measuring point pad, and all the measuring point pads are not overlapped in the direction perpendicular to the main surface of the adapter plate. In the application, the two adapter plates are stacked, the measuring point pad is arranged on the side surface of the adapter plate, compared with only arranging one adapter plate, the size of the adapter plate can be reduced under the premise of meeting the signal integrity, and sufficient space is reserved for wiring.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage devices, and more particularly to a small-size storage device adapter plate. In addition, the present application also relates to a PCB structure comprising the small-size storage device adapter plate and an electronic device comprising the PCB structure. BACKGROUND

[0002] In the current life, we use various types of functional software in daily life, and whether these software run smoothly often depends on whether the hardware device memory performance is powerful. It is necessary to measure and verify the signal quality of the fourth generation memory (DDR4) bus for designing high-speed and stable memory. Since the dynamic random access memory (DRAM) particles often adopt the top and bottom pasting mode, there is no space for oscilloscope probe point measurement.

[0003] Among the two existing design schemes, the first scheme adopts a two-layer adapter plate design. The first layer PCB ensures that the height is higher than the height of the dynamic random access memory particles, and the second layer PCB is provided with pads on the edge surface of the board as measurement points. In the second scheme, an adapter plate slightly larger than the size of the dynamic random access memory particles is designed, and then pads or half-holes are arranged on the edge surface of the board as measurement points.

[0004] In the first scheme, a two-layer PCB design is adopted. Since the height of the first layer PCB is higher than the height of the DRAM particles, the interference problem of the adapter plate (interposer) with the adjacent DRAM particles is avoided, and the layout space of the layout is not affected. However, this scheme is usually used for logic analyzer testing. The second layer PCB with pads as measurement points is usually designed to be large, and the excessively large PCB leads to excessively long wiring, which degrades the signal to be tested, resulting in low test accuracy.

[0005] In the second scheme, since the number of pads (PAD) / half-hole measurement points needs to be distributed around the DRAM particle entity, the four edge sizes of the adapter plate (interposer) are slightly larger than the size of the DRAM particle body, and the four peripheral soldering operation spaces need to be reserved in the PCB layout, which affects the layout space of the layout.

[0006] In the above two schemes, the four edges of the PCB of the adapter plate (interposer) are larger than the DRAM particle body, resulting in a large overall volume, which limits the structural design.

[0007] In summary, how to reduce the influence of the adapter plate on the wiring design under the premise of ensuring signal integrity is a problem that needs to be solved by the technical personnel in the field at present. SUMMARY

[0008] Therefore, the application aims to provide a small-size storage device adapter plate, two adapter plates are stacked, and test point pads are arranged on the side surfaces of the adapter plates, so that the size of the adapter plate can be effectively reduced and sufficient space can be reserved for wiring under the premise of meeting signal integrity.

[0009] Another object of the application is to provide a PCB structure comprising the small-size storage device adapter plate and an electronic device comprising the PCB structure.

[0010] To achieve the above object, the application provides the following technical solutions.

[0011] A small-size storage device adapter plate comprises:

[0012] a memory chip body;

[0013] adapter plates, two of which are stacked, and the main surfaces of the adapter plates are arranged in close contact with the surface of the memory chip body;

[0014] test point pads arranged on the side surfaces of the adapter plates, the side surfaces being surfaces arranged on the edges of the main surfaces of the adapter plates and arranged perpendicularly to the main surfaces; both of the adapter plates are provided with the test point pads, and there is no overlap between all the test point pads in the direction perpendicular to the main surfaces of the adapter plates.

[0015] Optionally, part of the side surfaces of the adapter plates is provided with the test point pads, and another part of the side surfaces of the adapter plates is not provided with the test point pads.

[0016] Optionally, the main surface of the adapter plate is quadrilateral, and at least one of the side surfaces of the adapter plate is not provided with the test point pads.

[0017] Optionally, the first side surface of the adapter plate is provided with a plurality of test point pads, both of the side surfaces connected to the first side surface are provided with a plurality of test point pads, and the plurality of test point pads are located close to the first side surface, so that one side of the central axis of the adapter plate is provided with the test point pads, and the other side is not provided with the test point pads.

[0018] Optionally, both of the side surfaces of the adapter plate are provided with the test point pads, and the other two side surfaces are not provided with the test point pads.

[0019] Optionally, one diagonal line of the adapter plate is a boundary, two side surfaces located on one side of the diagonal line are provided with the test point pads, and two side surfaces located on the other side of the diagonal line are provided with the test point pads.

[0020] Optionally, the test point pads are uniformly arranged along the side surfaces.

[0021] Optionally, the two adapter plates are of the same size, and the edges of the adapter plates are arranged in alignment, and the test point pads on the two adapter plates are arranged alternately along the circumferential direction of the adapter plates.

[0022] Optionally, the main surface of the adapter plate is of a size less than or equal to that of the surface of the memory chip body.

[0023] Optionally, the PCB structure further comprises at least one adapter plate, and all the adapter plates are arranged in stack.

[0024] A PCB structure, comprising a PCB, and the top surface and / or the bottom surface of the PCB is provided with the small-size storage device adapter plate according to any one of the above.

[0025] An electronic device, comprising a PCB structure, and the PCB structure is the PCB structure according to the above.

[0026] In the use of the small-size storage device adapter plate provided by the application, the small-size storage device adapter plate comprises a memory chip body, two adapter plates arranged in stack, and a main surface of the adapter plate arranged in abutment with a surface of the memory chip body; a test point pad arranged on a side surface of the adapter plate, the side surface being a surface arranged in perpendicular to the edge of the main surface of the adapter plate; and the two adapter plates are both provided with test point pads, and in the direction perpendicular to the main surface of the adapter plate, there is no overlap between all the test point pads.

[0027] Due to the arrangement of the two adapter plates in stack and the arrangement of the test point pads on the side surface of the adapter plate, compared with the arrangement of only one adapter plate, the size of the adapter plate can be reduced under the premise of meeting the signal integrity, and sufficient space is reserved for wiring.

[0028] The application further provides a PCB structure comprising the small-size storage device adapter plate and an electronic device comprising the PCB structure. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only belong to the embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings.

[0030] Figure 1 Structure diagram of the small-size storage device adapter plate provided by the application;

[0031] Figure 2 Structure diagram of the test point PCB structure provided by the application.

[0032] Figures 1-2 In the core of the present application is to provide a small size storage device adapter plate, two adapter plates are stacked, and a measurement point pad is arranged on the side surface of the adapter plate, which can effectively reduce the size of the adapter plate under the premise of meeting the signal integrity, and provide sufficient space for wiring.

[0033] 1 is a memory chip body, 2 is an adapter plate, 3 is a measurement point pad, and 4 is a PCB. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0035] The core of the present application is to provide a small size storage device adapter plate, two adapter plates are stacked, and a measurement point pad is arranged on the side surface of the adapter plate, which can effectively reduce the size of the adapter plate under the premise of meeting the signal integrity, and provide sufficient space for wiring.

[0036] Another core of the present application is to provide a PCB structure comprising the above-mentioned small size storage device adapter plate and an electronic device comprising the above-mentioned PCB structure.

[0037] Please refer to Figures 1-2 .

[0038] The specific embodiment discloses a small size storage device adapter plate, comprising: a memory chip body 1; an adapter plate 2, two adapter plates 2 are stacked, and the main surface of the adapter plate 2 is arranged in close contact with the surface of the memory chip body 1; a measurement point pad 3 is arranged on the side surface of the adapter plate 2, the side surface is a surface arranged on the edge of the main surface of the adapter plate 2 and arranged perpendicularly thereto; both of the two adapter plates 2 are provided with the measurement point pad 3, and in the direction perpendicular to the main surface of the adapter plate 2, there is no overlap between all the measurement point pads 3.

[0039] It should be noted that in the specific embodiment, in the direction perpendicular to the main surface of the adapter plate 2, there is no overlap between all the measurement point pads 3, which specifically means that in the direction perpendicular to the main surface of the adapter plate 2, there is no two completely overlapping measurement point pads 3, so that the measurement point pads 3 on the stacked adapter plates 2 are not completely stacked, the number of measurement point pads 3 can be increased, and appropriate space is reserved for the connection of the measurement point pads 3, facilitating the connection of the measurement point pads 3.

[0040] The measuring point pad 3 in the embodiment is arranged on the side surface of the adapter plate 2. In the specific arrangement process, the measuring point pad 3 needs to be arranged on both of the two adapter plates 2 arranged in a stack to meet the requirement of the number of measuring point pads 3. The measuring point pad 3 can be arranged on part of the side surface of the adapter plate 2, or the measuring point pad 3 can be arranged on all the side surfaces of the adapter plate 2. The specific arrangement is determined according to the actual situation.

[0041] The number of the adapter plates 2 in the embodiment can be two or more than two. The specific number is determined according to the actual situation.

[0042] The two adapter plates 2 in the embodiment are arranged in a stack. Specifically, one of the two adapter plates 2 is arranged on the upper part of the other adapter plate 2. The sizes of the two adapter plates 2 can be the same, and the projections of the two adapter plates 2 on the horizontal plane completely coincide to minimize the planar area occupied by the two adapter plates 2. Of course, the projections of the two adapter plates 2 on the horizontal plane can partially coincide in the process of stacking the two adapter plates 2 to reduce the planar area occupied by the two adapter plates 2.

[0043] Because the two adapter plates 2 are arranged in a stack, and the measuring point pad 3 is arranged on the side surface of the adapter plate 2, compared with arranging only one adapter plate 2, the size of the adapter plate 2 can be reduced to reserve sufficient space for wiring under the premise of meeting the signal integrity.

[0044] In an embodiment, the adapter plate 2 can be arranged in a quadrilateral shape, and the shapes of the two adapter plates 2 arranged in a stack are the same. Of course, the adapter plate 2 can also be in other required shapes, such as a triangular shape, a pentagonal shape, a polygonal shape, an irregular shape, etc. The specific shape is determined according to the actual situation. In the specific arrangement process, the shapes of the two adapter plates 2 arranged in a stack can be the same or different. The specific arrangement is determined according to the actual situation, and will not be described here.

[0045] In an embodiment, part of the side surface of the adapter plate 2 is provided with the measuring point pad 3, and the other part of the side surface of the adapter plate 2 is not provided with the measuring point pad 3.

[0046] Specifically, the main surface of the adapter plate 2 can be arranged in a quadrilateral shape and has four side surfaces. The measuring point pad 3 can be arranged on only one of the side surfaces, and the measuring point pad 3 is not arranged on the other three side surfaces. The surface provided with the measuring point pad 3 can be one of the front side surface, the rear side surface, or the left and right side surfaces of the adapter plate 2. The specific surface is determined according to the actual situation.

[0047] The main surface of the adapter plate 2 can also be quadrilateral, has four side surfaces, and the measurement point pads 3 are arranged on only two of the side surfaces, and the other two side surfaces are not provided with the measurement point pads 3. The surfaces provided with the measurement point pads 3 can be two opposite side surfaces or two adjacent side surfaces, which is determined according to actual conditions and will not be described here.

[0048] The main surface of the adapter plate 2 can also be quadrilateral, has four side surfaces, and the measurement point pads 3 are arranged on only three of the side surfaces, and the other one side surface is not provided with the measurement point pads 3. The surface not provided with the measurement point pads 3 can be one of the front side surface, the rear side surface or the left and right side surfaces of the adapter plate 2, which is determined according to actual conditions and will not be described here.

[0049] In the embodiment, the measurement point pads 3 are arranged on only part of the side surfaces of the adapter plate 2, and under the premise of meeting the number of measurement point pads 3, the remaining side surfaces can be used for wiring to facilitate wiring.

[0050] The main surface of the adapter plate 2 can also be pentagonal, has five side surfaces, and the measurement point pads 3 are arranged on only one of the side surfaces, and the other four side surfaces are not provided with the measurement point pads 3. The surface provided with the measurement point pads 3 can be any one of the side surfaces of the adapter plate 2, which is determined according to actual conditions and will not be described here.

[0051] The main surface of the adapter plate 2 can also be pentagonal, has five side surfaces, and the measurement point pads 3 are arranged on only two of the side surfaces, and the other three side surfaces are not provided with the measurement point pads 3. The surfaces provided with the measurement point pads 3 can be two opposite side surfaces, two adjacent side surfaces, or two side surfaces arranged at intervals, which is determined according to actual conditions and will not be described here.

[0052] The main surface of the adapter plate 2 can also be pentagonal, has five side surfaces, and the measurement point pads 3 are arranged on only three of the side surfaces, and the other two side surfaces are not provided with the measurement point pads 3. The surfaces not provided with the measurement point pads 3 can be two opposite side surfaces, two adjacent side surfaces, or two side surfaces arranged at intervals of the adapter plate 2, which is determined according to actual conditions and will not be described here.

[0053] The main surface of the adapter plate 2 can also be pentagonal, has five side surfaces, and the measurement point pads 3 are arranged on only four of the side surfaces, and the other one side surface is not provided with the measurement point pads 3. The surface not provided with the measurement point pads 3 can be any one of the five side surfaces, which is determined according to actual conditions and will not be described here.

[0054] In the specific embodiment, the side surface opposite to the adjacent adapter plate 2 in the adapter plate 2 is not provided with the measurement point pad 3, so as to avoid the interference of the measurement point pad 3 in the adjacent adapter plate 2 in the process of use; in the specific setting process, the main surface of the adapter plate 2 can also be other polygons or irregular shapes, which is determined according to the actual situation and will not be described here.

[0055] In a specific embodiment, the first side surface of the adapter plate 2 is provided with a plurality of measurement point pads 3, the two side surfaces connected with the first side surface are both provided with a plurality of measurement point pads 3, and the plurality of measurement point pads 3 are located close to the first side surface, so that one side of the central axis of the adapter plate 2 is provided with the measurement point pad 3, and the other side is not provided with the measurement point pad 3.

[0056] As shown in Figure 1 , the measurement point pad 3 can be arranged on the first side surface of the adapter plate 2, that is, the front side surface of the adapter plate 2, the measurement point pads 3 are arranged on the two side surfaces adjacent to the first side surface, and the measurement point pads 3 are arranged in the length direction of the first side surface, and the other two side surfaces adjacent to the first side surface are only arranged close to the first side surface. In this specific embodiment, the central axis of the adapter plate 2 refers to the central axis that divides the two side surfaces adjacent to the first side surface in half, in this specific embodiment, the first side surface on one side of the central axis and the two side surfaces adjacent to the first side surface are provided with the measurement point pad 3, and the side surface opposite to the first side surface on the other side of the central axis and the two side surfaces adjacent to the first side surface are not provided with the measurement point pad 3; so as to avoid affecting the arrangement of the adjacent memory chip body 1.

[0057] In the specific embodiment, as shown in Figure 1 , the size of the adapter plate 2 can be set to be smaller than the size of the memory chip body 1, so that the projection of the memory chip body 1 on the adapter plate 2 completely covers the adapter plate 2, specifically, the main surface of the adapter plate 2 can be set as a quadrilateral, the memory chip body 1 is a cuboid, and the two side surfaces of the adapter plate 2 are arranged close to the two adjacent side surfaces of the memory chip body 1, as shown in Figure 1 , so as to reserve enough space on the other side of the adapter plate 2 for wiring.

[0058] In a specific embodiment, the main surface of the adapter plate 2 can be set as a quadrilateral, and the two side surfaces of the adapter plate 2 are provided with the measurement point pad 3, and the other two side surfaces are not provided with the measurement point pad 3, wherein the two side surfaces provided with the measurement point pad 3 can be adjacent side surfaces or opposite side surfaces, which is determined according to the actual situation. As shown in Figure 1 , the two adjacent side surfaces of the adapter plate 2 are provided with the measurement point pad 3.

[0059] The main surface of the adapter plate 2 can also be hexagonal, and two side surfaces of the adapter plate 2 are provided with the measurement point pads 3, and the other four side surfaces are not provided with the measurement point pads 3. Two side surfaces provided with the measurement point pads 3 can be adjacent side surfaces, or opposite side surfaces, or side surfaces separated by one side surface. When the adapter plate 2 is hexagonal, the memory chip body 1 can be set as a corresponding hexagonal shape or other shapes that meet the requirements. Of course, the main surface of the adapter plate 2 can also be hexagonal, and three side surfaces of the adapter plate 2 are provided with the measurement point pads 3, and the other three side surfaces are not provided with the measurement point pads 3. Three side surfaces provided with the measurement point pads 3 can be adjacent side surfaces, or side surfaces provided with the measurement point pads 3 and side surfaces not provided with the measurement point pads 3 are separated. The specific arrangement is determined according to the actual situation, which will not be described here.

[0060] The main surface of the adapter plate 2 can also be other shapes that meet the requirements, which will not be described here.

[0061] In a specific embodiment, the main surface of the adapter plate 2 can be set as a quadrilateral, and the diagonal of the main surface of the adapter plate 2 is a boundary, two side surfaces on one side of the diagonal are provided with the measurement point pads 3, and the other two side surfaces on the other side of the diagonal are not provided with the measurement point pads 3. Specifically, the measurement point pads 3 in two side surfaces can be close to each other. Specifically, the measurement point pads 3 can be arranged close to the position of the other side surface provided with the measurement point pads 3 in one side surface, so that the measurement point pads 3 in two side surfaces are adjacent, and the measurement point pads 3 in at least one side surface are arranged only at part of the position of the side surface. In the case of meeting the number of measurement point pads 3, the length of the side surface occupied by the measurement point pads 3 is reduced as much as possible to avoid interference between adjacent memory chip bodies 1.

[0062] The main surface of the adapter plate 2 can also be hexagonal, and three side surfaces on one side of the diagonal of the main surface of the adapter plate 2 are provided with the measurement point pads 3, and the other three side surfaces on the other side of the diagonal are not provided with the measurement point pads 3. Specifically, the side surfaces provided with the measurement point pads 3 on one side of the diagonal can be divided into a middle side surface and two side surfaces on both sides. When the measurement point pads 3 are arranged, the measurement point pads 3 are arranged along the length direction of the middle side surface and are uniformly distributed in the length direction of the middle side surface. When the adapter plate 2 is two layers of adapter plates 2 arranged in a stacked manner, the middle side surface of the upper adapter plate 2 and the middle side surface of the lower adapter plate 2 are both provided with the measurement point pads 3. The other two side surfaces are also provided with the measurement point pads 3. The measurement point pads 3 can be uniformly arranged along the length direction of the two side surfaces, or the measurement point pads 3 can be arranged only at positions close to the middle side surface of the two side surfaces. The specific arrangement is determined according to the actual situation, which will not be described here. When the adapter plate 2 is two layers of adapter plates 2 arranged in a stacked manner, the two side surfaces of the upper adapter plate 2 and the two side surfaces of the lower adapter plate 2 are both provided with the measurement point pads 3.

[0063] In the specific embodiment, the measurement point pads 3 are arranged only on one side of the diagonal of the adapter plate 2, and the side surfaces on the other side of the diagonal of the adapter plate 2 are not provided with the measurement point pads 3. This can effectively avoid interference between the measurement point pads 3 corresponding to adjacent memory chip bodies 1 during installation, and can reserve sufficient wiring space. In addition, each layer of the adapter plates 2 arranged in a stacked manner is provided with the measurement point pads 3, which can meet the requirement of the number of measurement point pads 3.

[0064] In a specific embodiment, the measurement point pads 3 can be uniformly arranged on the side surfaces of the adapter plate 2. Specifically, two adapter plates 2 can be arranged in a stacked manner. The measurement point pads 3 are uniformly arranged on the side surfaces of the upper adapter plate 2, and the measurement point pads 3 are also uniformly arranged on the side surfaces of the lower adapter plate 2. In addition, the spacing between adjacent two measurement point pads 3 in the upper adapter plate 2 is the same as the spacing between adjacent two measurement point pads 3 in the lower adapter plate 2, so that the arrangement density of the measurement point pads 3 in the stacked adapter plates 2 is the same, and the measurement point pads 3 are reasonably arranged to make full use of the area of the side surfaces of the adapter plate 2.

[0065] The main surface of the adapter plate 2 in the embodiment can be quadrilateral. In the specific arrangement, the measurement point pads 3 are arranged on the four side surfaces of the adapter plate 2, and the measurement point pads 3 are uniformly arranged on the four side surfaces. The intervals between any two adjacent measurement point pads 3 on the side surface are the same, so that the measurement point pads 3 are uniformly distributed on the four side surfaces of the adapter plate 2. Of course, the measurement point pads 3 can be arranged on only three side surfaces of the adapter plate 2, and the intervals between any two adjacent measurement point pads 3 on the three side surfaces are the same, so that the measurement point pads 3 are uniformly distributed on the three side surfaces of the adapter plate 2. Or the measurement point pads 3 can be arranged on only two side surfaces of the four side surfaces. The two side surfaces can be two adjacent side surfaces or two opposite side surfaces. The intervals between any two adjacent measurement point pads 3 on the two side surfaces are the same, so that the measurement point pads 3 are uniformly distributed on the two side surfaces of the adapter plate 2. Or the measurement point pads 3 can be arranged on only one side surface of the four side surfaces, and the measurement point pads 3 are uniformly distributed in the length direction of the side surface. When the adapter plate 2 is two layers arranged in a stack, the side surfaces of the upper adapter plate 2 and the lower adapter plate 2 on which the measurement point pads 3 are arranged are the same. That is, when one of the side surfaces of the adapter plate 2 arranged in a stack is provided with the measurement point pads 3 on the upper adapter plate 2, the lower adapter plate 2 is also provided with the measurement point pads 3. When the other side surface of the adapter plate 2 arranged in a stack is not provided with the measurement point pads 3 on the upper adapter plate 2, the lower adapter plate 2 is also not provided with the measurement point pads 3.

[0066] Specifically, the adapter plate 2 can include three layers of adapter plates 2 arranged in a stack. The measurement point pads 3 are uniformly arranged on the side surfaces of the upper adapter plate 2, the lower adapter plate 2, and the middle adapter plate 2. The intervals between any two adjacent measurement point pads 3 on the upper adapter plate 2, the middle adapter plate 2, and the lower adapter plate 2 are the same, so that the arrangement density of the measurement point pads 3 in the adapter plates 2 arranged in a stack is the same, and the measurement point pads 3 are reasonably arranged to fully utilize the area of the side surfaces of the adapter plate 2.

[0067] When the adapter plate 2 comprises three adapter plates 2 arranged in a stack, and the main surfaces of the adapter plates 2 are arranged in quadrilateral, in the process of arranging the measuring point pads 3, the side surfaces of the upper adapter plate 2, the middle adapter plate 2 and the lower adapter plate 2, on which the measuring point pads 3 are arranged, are the same, that is, when the upper adapter plate 2 corresponding to one of the side surfaces is arranged with the measuring point pads 3, the lower adapter plate 2 and the middle adapter plate 2 are also arranged with the measuring point pads 3, and when the upper adapter plate 2 corresponding to the other side surface is not arranged with the measuring point pads 3, the lower adapter plate 2 and the middle adapter plate 2 are also not arranged with the measuring point pads 3. In this way, the measuring point pads 3 in the stacked adapter plates 2 are concentrated on one side surface or several side surfaces as much as possible, the space occupied by the measuring point pads 3 in the adapter plate 2 is reduced as much as possible, and the size of the adapter plate 2 is reduced as much as possible under the premise of meeting the number of measuring point pads 3.

[0068] In an embodiment, the two adapter plates 2 are the same size, and the edges of the adapter plates 2 are arranged in alignment. Along the circumferential direction of the adapter plate 2, the measuring point pads 3 on the two adapter plates 2 are arranged alternately.

[0069] Specifically, as shown in FIG. 1, the two adapter plates 2 are arranged in a stack, and the edges of the two adapter plates 2 are arranged in alignment. Along the circumferential direction of the adapter plate 2, the measuring point pads 3 on the upper adapter plate 2 and the measuring point pads 3 on the lower adapter plate 2 are arranged alternately to avoid interference between the measuring point pads 3 on the adjacent two adapter plates 2. Figure 1

[0070] Preferably, when the adapter plate 2 is two layers arranged in a stack, the measuring point pads 3 can be evenly distributed on the side surfaces of the upper adapter plate 2, and the measuring point pads 3 can also be evenly distributed on the side surfaces of the lower adapter plate 2 adjacent to the upper adapter plate 2. In addition, the interval between the two adjacent measuring point pads 3 in the upper adapter plate 2 is equal to the interval between the two adjacent measuring point pads 3 in the lower adapter plate 2, and the measuring point pad 3 in the lower adapter plate 2 is located at the middle position between the two adjacent measuring point pads 3 in the upper adapter plate 2. Of course, the measuring point pad 3 in the lower adapter plate 2 can also be arranged in a staggered manner with the measuring point pad 3 in the upper adapter plate 2, and not located at the middle position between the two adjacent measuring point pads 3 in the upper adapter plate 2. The specific arrangement is determined according to the actual situation, which will not be described here.

[0071] In the embodiment, the measuring point pads 3 in the adjacent two side adapter plates 2 are arranged in a staggered manner, which can avoid interference between the measuring point pads 3 in the adjacent two side adapter plates 2, and facilitate the connection and use of the measuring point pads 3.

[0072] ​In a specific embodiment, the adapter plate 2 can be arranged to include three layers of adapter plates 2 arranged in a stack, specifically, the interval between two adjacent test point pads 3 in the upper layer of adapter plates 2 is equal to the interval between two adjacent test point pads 3 in the middle layer of adapter plates 2, and the interval between two adjacent test point pads 3 in the lower layer of adapter plates 2 is equal to the interval between two adjacent test point pads 3 in the middle layer of adapter plates 2, and the test point pad 3 in the middle layer is located at the middle position between two adjacent test point pads 3 in the upper layer, and the test point pad 3 in the lower layer is located at the middle position between two adjacent test point pads 3 in the middle layer.

[0073] The adapter plate 2 can also be arranged to include four layers of adapter plates 2 arranged in a stack, including the upper layer of adapter plates 2, the middle upper layer of adapter plates 2 adjacent to the upper layer of adapter plates 2, the middle lower layer of adapter plates 2 adjacent to the middle upper layer of adapter plates 2, and the lower layer of adapter plates 2 located at the lower part of the middle lower layer of adapter plates 2, the interval between two adjacent test point pads 3 in the upper layer of adapter plates 2, the interval between two adjacent test point pads 3 in the lower layer of adapter plates 2, the interval between two adjacent test point pads 3 in the middle upper layer of adapter plates 2, and the interval between two adjacent test point pads 3 in the middle lower layer of adapter plates 2 are all equal, and the test point pad 3 in the middle upper layer is located at the middle position between two adjacent test point pads 3 in the upper layer, the test point pad 3 in the middle lower layer is located at the middle position between two adjacent test point pads 3 in the middle upper layer, and the test point pad 3 in the lower layer is located at the middle position between two adjacent test point pads 3 in the middle lower layer.

[0074] Of course, the adapter plate 2 can also be of other layers arranged in a stack, which is specifically determined according to the actual situation, and will not be described here.

[0075] In a specific embodiment, the size of the main surface of the adapter plate 2 can be less than or equal to the size of the surface of the memory chip body 1, and in the specific arrangement process, the memory chip body 1 can completely cover the adapter plate 2, avoid the additional occupation of the planar space by the adapter plate 2, and stack the adapter plate 2, which can increase the number of test point pads 3 by increasing the number of layers of the adapter plate 2 to meet the setting requirements of the number of test point pads 3.

[0076] In this application, the adapter plate 2 is arranged to be at least two layers arranged in a stack, which can reduce the length of the side surface of the adapter plate 2 by half under the condition of ensuring the same number of test point pads 3, and the test point pads 3 are arranged on the outer side of the adapter plate 2, avoiding the influence of the test point pads 3 on the adjacent memory chip body 1.

[0077] In addition to the above-mentioned small-size storage device adapter plate, the present application also provides a PCB board structure including the above-mentioned small-size storage device adapter plate disclosed in the embodiments, which includes a PCB board 4, and the top surface and / or bottom surface of the PCB board 4 is provided with the above-mentioned small-size storage device adapter plate.

[0078] As shown in Figure 2 The PCB structure includes a PCB 4, and the upper surface and the lower surface of the PCB 4 are provided with small-size storage device adapter boards. In the specific setting process, the small-size storage device adapter board on the upper surface of the PCB 4 can be oppositely arranged with the small-size storage device adapter board on the lower surface. When the upper surface of the PCB 4 is provided with a plurality of small-size storage device adapter boards, there is sufficient space for installing wiring between adjacent small-size storage device adapter boards. Specifically, the adapter board 2 can be arranged away from the adjacent memory chip body 1, as shown in Figure 2 .

[0079] When the main surface of the adapter board 2 arranged in a stack is a quadrilateral, the test point pad 3 can be arranged on two opposite side surfaces of the adapter board 2, and both of the two side surfaces are not directed to the adjacent memory chip body 1, as shown in Figure 2 After the adapter board 2 is arranged in a stack, the size of the adapter board 2 provided with the test point pad 3 can be reduced to the original size. The additional wiring introduced is relatively short, which improves the test accuracy. At the same time, since the test point pad 3 is located on the outside, the space on the outside is relatively large, and the spacing between the adjacent memory chip bodies 1 does not need to be enlarged when wiring. There is sufficient space for welding of the adapter board 2, which can effectively avoid the problem of structural interference.

[0080] In a specific embodiment, according to the needs of the wiring, the PCB 4 can be set to an 8-layer PCB made of ordinary FR4 material. Of course, according to the actual wiring situation, the PCB 4 can be set to other layers that meet the requirements, and the specific determination is based on the actual situation, which will not be described here.

[0081] In a specific embodiment, the size of the adapter board 2 is selected to be 11mm*9mm PIN size, which is slightly smaller than the size of the memory chip body. Since the half-hole almost does not occupy space, a hole diameter of 0.45mm and a center distance of 0.9mm are adopted. The space occupied by the test point pad 3 is saved in the processing process, and the test point pads 3 on the adapter boards 2 arranged in a stack can be arranged in a staggered manner. Under the condition that the number of test point pads 3 does not change, the size of the adapter board 2 provided with the test point pad 3 can be effectively reduced. When the main surface of the adapter board 2 is a quadrilateral, the width of the adapter board 2 can be reduced to half of the original size. Two adapter boards 2 with a width of half of the original size are arranged in a stack, so that the planar area occupied by the adapter board 2 is reduced. The test point pad 3 is arranged in the direction of the larger particle space of the memory chip body 1, which can obviously improve the wiring space.

[0082] It needs to be explained that in the process of specific setting, in order to prevent the setting of the adapter plate 2 from causing deterioration of the memory timing, it is required to make all signals equal in length, specifically, making DQ / DQS equal in length <1mil, and making Clock and address control signals equal in length <1mil.

[0083] In a specific embodiment, in order to properly increase the size of the adapter plate 2, GND VIA (ground hole) can also be added between signals. If there is no GND VIA on the adapter plate 2, GND VIA on the PCB 4 needs to be welded. The welding of GND VIA is relatively far away, which is not convenient for simultaneous welding. Due to the long distance, it will also cause the signal reflow path to be far away, affecting the test precision. Therefore, by setting GND VIA on the adapter plate 2, the SI (signal integrity) performance can be effectively improved and the test convenience can be improved.

[0084] As shown in Figure 2 In a specific embodiment, the PCB 4 is provided with an 8-layer structure, and the upper layer and the lower layer of the PCB 4 are provided with a plurality of small-size storage device adapter plates mentioned above. Specifically, the adapter plate 2 in the small-size storage device adapter plate is connected with the PCB 4, and the small-size storage device adapter plate is arranged between the PCB 4 and the memory chip body 1. The main surface size of the adapter plate 2 is slightly smaller than the size of the memory chip body 1, so that the memory chip body 1 can completely cover the adapter plate 2, and at least one side of the adapter plate 2 is aligned with the outer side of the memory chip body 1. The outer side of the memory chip body 1 mentioned here refers to the side of the memory chip body which is not opposite to the adjacent memory chip body 1, so that the side of the memory chip body 1 close to the adjacent memory chip body 1 is provided with the adapter plate 2. When the main surface of the adapter plate 2 is a quadrilateral structure, the test point pad 3 is arranged on the two opposite side surfaces, and the side surfaces provided with the test point pad 3 are not opposite to the adjacent memory chip body 1, so as to reserve enough space for the arrangement and wiring of the test point pad 3.

[0085] In a specific embodiment, the small-size storage device adapter boards on the upper surface and the lower surface of the same PCB 4 have the same number of stacked adapter boards 2, for example, the small-size storage device adapter board on the upper layer of the PCB 4 has two stacked adapter boards 2, and the small-size storage device adapter board on the lower layer of the PCB 4 also has two stacked adapter boards 2; according to the number of actual measurement point pads 3, the small-size storage device adapter boards on the upper surface and the lower surface of the same PCB 4 can have different numbers of stacked adapter boards 2; for example, the small-size storage device adapter board on the upper layer of the PCB 4 has two stacked adapter boards 2, and the small-size storage device adapter board on the lower layer of the PCB 4 has three stacked adapter boards 2; or the small-size storage device adapter board on the upper layer of the PCB 4 has three stacked adapter boards 2, and the small-size storage device adapter board on the lower layer of the PCB 4 has four stacked adapter boards 2; or the small-size storage device adapter board on the upper layer of the PCB 4 has three stacked adapter boards 2, and the small-size storage device adapter board on the lower layer of the PCB 4 has two stacked adapter boards 2; of course, other settings are also possible, which will not be described here.

[0086] Preferably, the main surface of the adapter board 2 is square or long, of course, the main surface of the adapter board 2 can also be other shapes that meet the requirements, which will be determined according to the actual situation, which will not be described here.

[0087] In addition to the above-mentioned PCB structure, the present application also provides an electronic device comprising the above-mentioned PCB structure, which can be an electronic communication device, an electronic display device, or other types of electronic devices such as a wristband electronic device, which will be determined according to the actual situation, which is different from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0088] The small-size storage device adapter board, the PCB structure, and the electronic device provided by the present application are described in detail above. This article applies specific examples to explain the principles and implementation methods of the present application, and the above description of the embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the principles of the present application, the present application can be improved and modified, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A small-size storage device adapter board, characterized in that, include: Memory chip body (1); Adapter board (2), two adapter boards (2) are stacked, and the main surface of the adapter board (2) is attached to the surface of the memory chip body (1); The test pad (3) is provided on the side surface of the adapter plate (2). The side surface is the surface provided on the edge of the main surface of the adapter plate (2) and perpendicular to it. Both adapter plates (2) are provided with the test pad (3). In the direction perpendicular to the main surface of the adapter plate (2), all the test pads (3) do not overlap. The adapter board (2) has a portion of its side surface with the test point pad (3), and another portion of its side surface without the test point pad (3). The side surface without the test point pad (3) is used for wiring. The two adapter plates (2) are the same size and their edges are aligned. The measuring pads (3) on the two adapter plates (2) are alternately arranged along the circumferential direction of the adapter plates (2).

2. The small-size storage device adapter board according to claim 1, characterized in that, The main surface of the adapter plate (2) is quadrilateral, and at least one of the side surfaces of the adapter plate (2) is not provided with the measuring point pad (3).

3. The small-size storage device adapter board according to claim 2, characterized in that, The first side surface of the adapter plate (2) is provided with a plurality of measurement pads (3), and the two side surfaces connected to the first side surface are each provided with a plurality of measurement pads (3), and the plurality of measurement pads (3) are located close to the first side surface, so that the measurement pads (3) are provided on one side of the central axis of the adapter plate (2), and the measurement pads (3) are not provided on the other side.

4. The small-size storage device adapter board according to claim 2, characterized in that, The adapter plate (2) has two side surfaces with the measuring pads (3), and the other two side surfaces do not have the measuring pads (3).

5. The small-size storage device adapter board according to claim 2, characterized in that, The adapter plate (2) has a diagonal line as a boundary, and the two side surfaces on one side are provided with the measuring point pads (3), and the two side surfaces on the other side are provided with the measuring point pads (3).

6. The small-size storage device adapter board according to claim 1, characterized in that, The measuring pads (3) are uniformly arranged along the side surface.

7. The small-size storage device adapter board according to claim 1, characterized in that, The size of the main surface of the adapter board (2) is less than or equal to the size of the surface of the memory chip body (1).

8. The small-size storage device adapter board according to claim 1, characterized in that, It also includes at least one of the adapter plates (2), and all the adapter plates (2) are stacked.

9. A PCB board structure, characterized in that, Includes a PCB board (4), the top and / or bottom surfaces of which are provided with a small-size storage device adapter board as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, It includes a PCB board structure, wherein the PCB board structure is the PCB board structure described in claim 9.

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