Method of manufacturing trench isolation structure

Abstract

The application discloses a trench isolation structure manufacturing method, which comprises the following steps: forming a trench on a first surface of a wafer by photoetching and etching; filling the trench with insulating isolation material; coating photoresist on the first surface of the wafer, and making the residual photoresist form an inclination angle with the first surface of the wafer by exposure and development, wherein the inclination angle is 50-60 degrees, and the residual photoresist extends from an active region to the top surface of the insulating isolation material in the trench; taking the residual photoresist as an etching stop layer, dry etching the insulating isolation material, and forming a recess on the surface of the insulating isolation material; removing the residual photoresist, and removing the excess insulating isolation material outside the trench by wet etching. The application can improve the surface topography of the insulating isolation material by dry etching the insulating isolation material through forming a special photoresist topography, and can obtain a relatively flat insulating isolation material surface topography in combination with a wet etching process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a trench isolation structure. Background Technology

[0002] As CMOS device dimensions shrink and channel lengths shorten, the "short-channel effect" becomes increasingly pronounced. Meanwhile, shallow trench isolation (STI) structures play a crucial role in the gate control voltage (Vt) and leakage current (Ig / Id) performance of these devices. The "short-channel effect" becomes increasingly severe in small-sized CMOS devices with a critical dimension (CD) below 90nm, leading to more significant leakage current. Therefore, the morphology of the corner trench oxide in STI structures is extremely critical for the electrical performance of small-sized advanced technology node (<28nm) CMOS devices. Furthermore, the morphology of the corner oxide in other trench isolation structures, such as deep trench isolation and FinFET isolation structures, also affects the electrical performance of semiconductor devices, necessitating improvements in short-channel effect suppression.

[0003] The exemplary STI fabrication process exhibits a divot phenomenon in the STI corner trench oxide, leading to thinning of the subsequent gate oxide growth. This "double hump" phenomenon causes leakage current in the device, such as... Figure 1 As shown. Figure 1 The position of the dashed box is the position of the divot. Figure 1 The white squares in the image represent post-processing. Corner trench oxide divot and double hump phenomena also occur in other trench isolation structures, leading to device leakage. Summary of the Invention

[0004] Therefore, it is necessary to provide a method for manufacturing a trench isolation structure that can improve the morphology of the trench isolation structure at the corner.

[0005] A method for manufacturing a trench isolation structure includes: forming a trench on a first side of a wafer by photolithography and etching; filling the trench with an insulating material; coating the first side of the wafer with photoresist, and then exposing and developing the residual photoresist to form an angle between the residual photoresist and the first side of the wafer, the angle being 50-60 degrees, the residual photoresist extending from the active region to the top surface of the insulating material in the trench; using the residual photoresist as an etching barrier layer, dry etching the insulating material to form a depression on the surface of the insulating material; removing the residual photoresist, and then removing excess insulating material outside the trench by wet etching.

[0006] The above-mentioned method for manufacturing trench isolation structures can improve the surface morphology of insulating isolation materials by dry etching through the formation of special photoresist morphology. Combined with wet etching process, a relatively smooth surface morphology of insulating isolation materials can be obtained.

[0007] In one embodiment, the trench isolation structure is a shallow trench isolation structure.

[0008] In one embodiment, during the step of forming a depression on the surface of the insulating material, the angle between the insulating materials on both sides of the depression and the surface of the insulating material at the bottom of the depression is 50 to 60 degrees.

[0009] In one embodiment, the depth of the recess is

[0010] In one embodiment, the opening area of ​​the recess accounts for 45% to 65% of the opening area of ​​the groove.

[0011] In one embodiment, in the step of forming an angle between the residual photoresist and the first surface of the wafer through exposure and development, the lateral distance between the edge of the exposed area and the edge of the active area is [missing information].

[0012] In one embodiment, in the step of forming an angle between the residual photoresist and the first surface of the wafer through exposure and development, the exposure focal length is 0.3 micrometers to 0.5 micrometers.

[0013] In one embodiment, after the step of removing excess insulating material outside the trench by wet etching is completed, the top of the insulating material is higher than the top of the active region.

[0014] In one embodiment, prior to the step of forming a trench on the first side of the wafer by photolithography and etching, the method further includes forming a pad oxide layer on the substrate of the wafer and forming a silicon nitride layer on the pad oxide layer; the step of forming a trench on the first side of the wafer by photolithography and etching includes performing photolithography on the silicon nitride layer and etching the silicon nitride layer, the pad oxide layer and the substrate to form the trench; the step of removing the residual photoresist and removing excess insulating material outside the trench by wet etching includes removing the silicon nitride layer and the pad oxide layer outside the trench.

[0015] In one embodiment, after the step of filling the trench with insulating material and before the step of coating the first side of the wafer with photoresist, a step of chemically and mechanically planarizing the first side of the wafer is further included.

[0016] In one embodiment, when chemical mechanical planarization is complete, the top of the insulating material is lower than the top of the silicon nitride layer.

[0017] In one embodiment, after the step of forming trenches on the first side of the wafer by photolithography and etching and before the step of filling the trenches with insulating material, the method further includes: forming a first oxide layer on the inner wall of the trenches by thermal oxidation; performing a first thermal annealing on the wafer; after the step of filling the trenches with insulating material and before the step of chemical mechanical planarization on the first side of the wafer, the method further includes a second thermal annealing on the wafer; wherein, the step of filling the trenches with insulating material includes filling the trenches with silicon oxide by high-density plasma chemical vapor deposition.

[0018] In one embodiment, during the step of filling the trench with silicon oxide by high-density plasma chemical vapor deposition, the top RF power of the sputtering menu is 2700 W to 2800 W, the bottom RF power is 2700 W to 2800 W, the side RF power is 750 W to 850 W, the oxygen flow rate is 100 sccm to 140 sccm, the helium flow rate is 100 sccm to 125 sccm, and the pressure is 2.5 HMOTO to 3.5 HMOTO.

[0019] In one embodiment, the temperatures of the first and second thermal annealings are 1100–1150°C.

[0020] In one embodiment, the first and second thermal annealings are performed in a nitrogen atmosphere.

[0021] In one embodiment, the nitrogen flow rate for the first and second thermal annealing is 15 ml / min to 20 ml / min.

[0022] In one embodiment, the annealing time for the first and second thermal annealing is 2 hours.

[0023] In one embodiment, in the step of filling the trench with silicon oxide by high-density plasma chemical vapor deposition, the sputtering gas source includes helium and oxygen, but does not include hydrogen and argon; after the step of filling the trench with silicon oxide by high-density plasma chemical vapor deposition is completed, the thickness of the first oxide layer is...

[0024] In one embodiment, in the step of removing excess insulating material outside the trench by wet etching, the etchant used in the wet etching is dilute hydrofluoric acid, the reaction temperature is 20-45°C, the corrosion rate ratio of the wet etching to the silicon oxide and the pad oxide layer is 1.5:1-5.5:1, and the corrosion rate ratio of the wet etching to the silicon oxide and the first oxide layer is 1.5:1-5.5:1.

[0025] In one embodiment, after the step of removing excess insulating material outside the trench by wet etching, the method further includes the step of forming a gate oxide layer on the surface of the active region, and the step of forming a polysilicon gate on the gate oxide layer. Attached Figure Description

[0026] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0027] Figure 1 This is a microscope image of an exemplary STI structure trench corner “hump”;

[0028] Figure 2 This is a flowchart of a method for manufacturing a trench isolation structure in one embodiment;

[0029] Figures 3a to 3g Is adopted Figure 2 The diagram shows a cross-sectional view of the wafer during the manufacturing process of STI using the method shown.

[0030] Figure 4 This is a schematic diagram of the insulating material in the dry etching trench;

[0031] Figure 5This is a schematic diagram illustrating the difference in corrosion rate of wet corrosion on different morphological structures.

[0032] Figure 6 This is a schematic diagram illustrating the principle of using HDPCVD process plasma sputter to repair the morphology of a trench corner structure. Detailed Implementation

[0033] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0039] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0040] Figure 2 This is a flowchart of a method for manufacturing a trench isolation structure in one embodiment, including the following steps:

[0041] S110 forms trenches on the front side of the wafer through photolithography and etching.

[0042] In one embodiment of this application, a pad oxide layer 22 is first formed on the substrate 10 of the wafer, then a hard mask 30 is formed on the pad oxide layer 22, and finally a photoresist 92 is coated on the hard mask 30. See [link to relevant documentation]. Figure 3a In one embodiment of this application, the hard mask 30 is a silicon nitride layer. In one embodiment of this application, the thickness of the pad oxide layer 22 is... In one embodiment of this application, the substrate 10 is a semiconductor substrate, and its material can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc., or it can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. Figure 3a In the embodiment shown, the substrate 10 is made of monocrystalline silicon.

[0043] In one embodiment of this application, step S110 involves exposing the photoresist 92 using an active area photomask, followed by development to form trench etching windows. The hard mask 30, the pad oxide layer 22, and the substrate are etched through these windows to form trenches 21 with different density patterns. These trenches 21 are used to fabricate shallow trench isolation structures. (See also...) Figure 3b In other embodiments of this application, trench 21 can also be used to fabricate deep trench isolation structures or FinFET isolation structures.

[0044] S120, filling the trench with insulating material.

[0045] In one embodiment of this application, before step S120, the method further includes removing the photoresist 92 and forming a first oxide layer 24 on the inner wall of the trench 21 by thermal oxidation. See [link to previous embodiment]. Figure 3c The first oxide layer 24 is a linear oxide layer, and its material is silicon oxide, such as silicon dioxide. In one embodiment of this application, the first oxide layer 24 is formed using a furnace tube process. See also... Figure 3d After the first oxide layer 24 is formed, an insulating material 26 is deposited on the front side of the wafer, and the insulating material 26 fills the trench 21. Figure 3d(Not shown in the text). In one embodiment of this application, the insulating material is silicon oxide, such as silicon dioxide.

[0046] S130 uses exposure and development to create an angle between the photoresist and the front side of the wafer.

[0047] In one embodiment of this application, a chemical mechanical planarization (CMP) step is included before step S130. The surface of the hard mask 30 can be used as the termination point of CMP. The purpose of CMP is to remove excess insulating material 26 from the front side of the wafer. In one embodiment of this application, CMP can use endpoint detection to stop the grinding termination point on the surface of the hard mask 30. In one embodiment of this application, after CMP, the height of the top of the insulating material 26 is lower than the top of the hard masks 30 on both sides (i.e., the hard masks 30 on the active regions).

[0048] In one embodiment of this application, step S130 involves coating photoresist onto the front side of the wafer, and then using a patterned photomask to remove a portion of the photoresist directly above the trenches through exposure and development. See also Figure 3e The residual photoresist 94 forms an angle with the front side of the wafer, with an angle of 50 to 60 degrees. The residual photoresist 94 extends from the active area to the trench 21. Figure 3e The top surface of the insulating material 26 (not indicated in the text).

[0049] S140, dry etching of insulating material to form depressions on the surface of insulating material.

[0050] Using the residual photoresist 94 as an etching barrier layer, the insulating isolation material 26 is dry-etched to form a depression on the surface of the insulating isolation material 26. Since the residual photoresist 94 forms an angle with the front side of the wafer, the depression formed by dry etching with it as the etching barrier layer will also form a corresponding angle θ, that is, the insulating isolation material 26 on both sides of the depression and the surface of the insulating isolation material at the bottom of the depression form an angle θ. Figure 4 This is a partial schematic diagram of the STI structure after step S140 in one embodiment. In this embodiment, the tilt angle θ is 50–60 degrees, and the depth of the depression is… The lateral distance W between the edge of the exposed area and the edge of the active area is

[0051] S150 removes photoresist and removes excess insulating material outside the trench by wet etching.

[0052] In one embodiment of this application, residual photoresist 94 is removed by wet stripping, and hard mask 30 is removed by wet etching. See [link to relevant documentation]. Figure 3fThe wet adhesive removal and wet etching removal of the hard mask 30 can be performed using the same process or different processes (different etchants). After the hard mask 30 is removed, excess insulating material 26 outside the trench 21 is removed by wet etching. See [link to relevant documentation]. Figure 3g Different oxide layers exhibit different corrosion rates under the same wet corrosion conditions, and the same oxide layer also shows rate differences in different directions depending on its angular structural morphology. Figure 5 As shown. The height difference between the top of the insulating material 26 and the top of the active region can be controlled by controlling the etching time of the wet etching process. In one embodiment of this application, after the excess insulating material 26 is removed by wet etching, the top of the insulating material 26 is higher than the top of the active region.

[0053] The above-mentioned method for manufacturing trench isolation structures involves dry etching of insulating isolation materials by forming special photoresist morphology, modifying the morphology of the insulating isolation materials at the trench corners, which can improve the surface morphology of the insulating isolation materials. This results in the insulating isolation materials at the trench corners exhibiting a reverse double hump after dry etching. Combined with wet etching processes, a relatively smooth surface morphology of the insulating isolation materials can be obtained.

[0054] In one embodiment of this application, step S150 is followed by a step of forming a gate oxide layer on the surface of the active region, and a step of forming a polysilicon gate on the gate oxide layer.

[0055] In one embodiment of this application, the opening area of ​​the recess formed in step S140 accounts for 45% to 65% of the opening area of ​​the trench 21, that is, the area of ​​the exposed pattern in step S130 accounts for 45% to 65% of the opening area of ​​the trench 21. The exposure focal length in step S130 is 0.3 micrometers to 0.5 micrometers.

[0056] In one embodiment of this application, after forming the first oxide layer 24 and before filling the insulating material 26 in step S120, a step of thermal annealing the wafer is included. Furthermore, after step S120 and before CMP removal of excess insulating material 26, the wafer is thermally annealed again. In one embodiment of this application, the temperature for both thermal annealings is 1100–1150°C. In one embodiment of this application, the duration for both thermal annealings is approximately 2 hours. In one embodiment of this application, both thermal annealings are performed in a nitrogen atmosphere. In one embodiment of this application, the nitrogen flow rate during annealing is 15 ml / min–20 ml / min.

[0057] Through creative efforts, the inventors discovered that the wet etching of SiO2 in step S150 is affected by the surface roughness of the SiO2 film. When the surface roughness of the SiO2 film is large, the etching rate at different points on the surface is inconsistent. During the etching process, the difference in etching rate between concave and convex points continuously increases, leading to irregular protrusions. Two thermal annealing processes can improve the roughness on both sides of the trench corner, improve the stress at the trench corner and the density of the oxide layer, thereby improving the morphology of the silicon oxide surface after wet etching in step S150. Furthermore, using two thermal annealing processes (one after the formation of the first oxide layer 24 and before step S120, and another after step S120 and before CMP removal of excess insulating material 26) is more effective than a single annealing process.

[0058] In one embodiment of this application, step S120, filling the trench with insulating material 26, is performed using a high-density plasma chemical vapor deposition (HDPCVD) process.

[0059] See Figure 5 In one embodiment of this application, the wet etching in step S150 removes not only the insulating material 26 but also the gasket oxide layer 22, and may partially etch the first oxide layer 24. The etchant used in this wet etching is dilute hydrofluoric acid, such as commercially available hydrofluoric acid (approximately 40%–50% by mass) diluted with water at a volume ratio of 1:50 to 1:100. In one embodiment of this application, the reaction temperature for this wet etching is 20–45°C. After the aforementioned two annealing processes, the etching rate ratio of the silicon oxide formed by the wet etching process to that formed by thermal oxidation (mainly the gasket oxide layer 22) is 1.5:1 to 5.5:1.

[0060] The morphology improvement scheme of this application, which combines two thermal annealing processes with dry and wet etching, can improve the morphology of the "double hump" on both sides of the trench corner and the rough surface of the insulating isolation material 26 (silicon dioxide). It avoids the silicon dioxide at the trench corner from being recessed due to the isotropic wet etching (the wet etching amount of the oxide layer on both sides of the trench corner is higher than that in the central area, resulting in the formation of divot on both sides). This avoids the situation where the grown gate oxide is too thin at the trench corner and is prone to breakdown, leading to leakage current in the device gate.

[0061] During the HDPCVD process in step S120, the thickness and morphology of the first oxide layer 24 at the trench corner can be repaired by controlling plasma sputtering, avoiding excessive damage to the first oxide layer 24 at the trench corner caused by sputtering. (Refer to...) Figure 6In one embodiment of this application, the sputtering gas source includes helium and oxygen, but excludes hydrogen and argon. This is because hydrogen, under the influence of plasma, can enter the Si lattice and form charge traps, affecting the electrical performance of the device; while argon, due to its strong bombardment capability, can generate redeployment on the sidewalls of trench 21, and simultaneously causes excessive reduction of the first oxide layer 24 at the trench corners. In one embodiment of this application, the RF-TOP (top RF) power, RF-BIAS (bottom RF) power, and RF-SIDE (side RF) power in the HDPCVD sputtering menu of step S120 are 2700 W to 2800 W, 2700 W to 2800 W, 750 W to 850 W, oxygen flow rate is 100 sccm to 140 sccm, helium flow rate is 100 sccm to 125 sccm, and pressure is 2.5 HToR to 3.5 HToR. The thickness of the first oxide layer 24 after HDPCVD is [not specified].

[0062] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0063] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0064] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0065] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for manufacturing a trench isolation structure, comprising: Trenches are formed on the first side of the wafer through photolithography and etching. Fill the trench with insulating material; Photoresist is coated on the first surface of the wafer. Exposure and development are performed to create an angle between the remaining photoresist and the first surface of the wafer, the angle being 50–60 degrees. The remaining photoresist extends from the active region to the top surface of the insulating material in the trench. The lateral distance between the edge of the exposed area and the edge of the active region is [missing information]. Using the residual photoresist as an etching barrier layer, the insulating material is dry-etched to form a depression on the surface of the insulating material. The opening area of ​​the depression accounts for 45% to 65% of the opening area of ​​the trench. Remove the residual photoresist and remove excess insulating material outside the trench by wet etching.

2. The manufacturing method of the trench isolation structure according to claim 1, characterized in that, In the step of forming a depression on the surface of the insulating material, the angle between the insulating materials on both sides of the depression and the surface of the insulating material at the bottom of the depression is 50 to 60 degrees.

3. The manufacturing method of the trench isolation structure according to claim 2, characterized in that, The depth of the depression is 4. The method for manufacturing the trench isolation structure according to claim 1 or 2, characterized in that, In the step of forming an angle between the residual photoresist and the first surface of the wafer through exposure and development, the exposure focal length is 0.3 micrometers to 0.5 micrometers.

5. The method for manufacturing the trench isolation structure according to claim 1, characterized in that, After the step of removing excess insulating material outside the trench by wet etching is completed, the top of the insulating material is higher than the top of the active region.

6. The method for manufacturing the trench isolation structure according to claim 1, characterized in that, The trench isolation structure is a shallow trench isolation structure. Before the step of forming the trench on the first side of the wafer by photolithography and etching, the method further includes the steps of forming a pad oxide layer on the substrate of the wafer and forming a silicon nitride layer on the pad oxide layer. The step of forming trenches on the first side of a wafer by photolithography and etching includes performing photolithography on the silicon nitride layer and etching the silicon nitride layer, the pad oxide layer and the substrate to form the trenches; The steps of removing the residual photoresist and removing excess insulating material outside the trench by wet etching include removing the silicon nitride layer and the pad oxide layer outside the trench.

7. The method for manufacturing the trench isolation structure according to claim 6, characterized in that, After the step of filling the trench with insulating material and before the step of coating the first side of the wafer with photoresist, the method further includes a step of chemically and mechanically planarizing the first side of the wafer.

8. The method for manufacturing the trench isolation structure according to claim 7, characterized in that, After the step of forming trenches on the first side of the wafer by photolithography and etching, and before the step of filling the trenches with insulating material, the method further includes: A first oxide layer is formed on the inner wall of the trench by thermal oxidation; The wafer is subjected to a first thermal annealing; After the step of filling the trench with insulating material and before the step of chemically and mechanically planarizing the first side of the wafer, the wafer is further subjected to a second thermal annealing step. The step of filling the trench with insulating material includes filling the trench with silicon oxide by high-density plasma chemical vapor deposition.

9. The method for manufacturing the trench isolation structure according to claim 8, characterized in that, The temperatures for the first and second heat annealings are 1100–1150°C.

10. The method for manufacturing the trench isolation structure according to claim 8, characterized in that, In the step of filling the trench with silicon oxide by high-density plasma chemical vapor deposition, the gas source used for sputtering includes helium and oxygen, but does not include hydrogen and argon. After the step of filling the trench with silicon oxide by high-density plasma chemical vapor deposition is completed, the thickness of the first oxide layer is 11. The method for manufacturing the trench isolation structure according to claim 8 or 9, characterized in that, In the step of removing excess insulating material outside the trench by wet etching, the etchant used in wet etching is dilute hydrofluoric acid, the reaction temperature is 20-45°C, the corrosion rate ratio of the silicon oxide to the gasket oxide layer is 1.5:1 to 5.5:1, and the corrosion rate ratio of the silicon oxide to the first oxide layer is 1.5:1 to 5.5:1.

Images