Sense element applied to non-volatile memory

Abstract

A sensing element applied to a non-volatile memory, comprising: a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first end of the first switch is connected to the first node, and a control end of the first switch receives an inverted reset pulse. A first end of the second switch is connected to the first node, a second end of the second switch receives a ground voltage, and a control end of the second switch receives a reset pulse. The sensing circuit is connected between a second end of the first switch and a second node. The sensing circuit generates a first sensing current. The judging circuit is connected to the second node. The judging circuit receives the first sensing current and generates output data according to the first sensing current.

Description

Technical Field

[0001] The present invention relates to a sensing device, and more particularly to a sensing device applied to a non-volatile memory. Background Art

[0002] As is well known, non-volatile memories have been widely applied to various electronic products. For example, SD cards, solid state drives (SSDs), and so on. Basically, a memory array in a non-volatile memory includes a plurality of memory cells. And each memory cell has a floating gate transistor. Among them, the floating gate in the floating gate transistor can store hot carriers, and the storage state of the floating gate transistor can be determined according to the amount of hot carriers stored. Furthermore, the floating gate transistor can also be called a storage transistor.

[0003] Generally, when hot carriers are injected into the floating gate transistor, the threshold voltage (abbreviation: V T ) of the floating gate transistor changes according to the amount of hot carriers injected. Therefore, a floating gate transistor with a higher threshold voltage requires a higher gate voltage to turn on the floating gate transistor; conversely, a floating gate transistor with a lower threshold voltage can be turned on with a lower gate voltage.

[0004] During the program cycle of the non-volatile memory, the amount of hot carriers injected into the floating gate can be controlled, thereby changing the threshold voltage of the floating gate transistor. And during the sense cycle, a read voltage is provided to the floating gate transistor, and a cell current, or called a read current, can be generated. And according to the magnitude of the cell current, it can be known whether the storage state of the floating gate transistor (i.e., the memory cell) is in the on state or the off state.

[0005] For example, when a read voltage is applied to a floating-gate transistor with a low threshold voltage, the floating-gate transistor turns on, generating a relatively high cell current. Conversely, when a read voltage is applied to a floating-gate transistor with a high threshold voltage, the floating-gate transistor fails to turn on and remains off, generating a cell current that is nearly zero. That is to say, during the sensing cycle, an on-state memory cell generates a relatively high cell current, while an off-state memory cell generates a relatively low cell current.

[0006] Of course, in a non-volatile memory, it is more necessary to provide a sensing device to receive the cell current generated by the memory cell and determine the storage state in the memory cell.

[0007] Please refer to FIG. 1, which shows a schematic diagram of a known sensing device. The sensing device 100 includes a transistor M1, a transistor M2, a current source 110, an operational amplifier 120, and a judging element 130.

[0008] The transistor M1 and the operational amplifier 120 are connected to form a voltage clamping circuit. The drain of the transistor M1 is connected to a data line (DL) to receive the cell current Icell output by the memory cell. The gate of the transistor M1 is connected to the output terminal of the operational amplifier 120, and the source of the transistor M1 receives a ground voltage GND. Furthermore, the first input terminal of the operational amplifier 120 receives a clamping voltage V CLP , and the second input terminal of the operational amplifier 120 is connected to the drain of the transistor M1. Therefore, when the voltage clamping circuit is in a normal operating state, the data line voltage V DL on the drain of the transistor M1 is equal to the clamping voltage V CLP .

[0009] The current source 110 is connected between a supply voltage Vdd and a judging node s. The current source 110 can generate a reference current I REF . The drain of the transistor M2 is connected to the judging node s. The drain of the transistor M2 receives the reference current I REF , the gate of the transistor M2 is connected to the gate of the transistor M1, and the source of the transistor M2 receives a ground voltage GND. Among them, the supply voltage Vdd is greater than the clamping voltage V CLP , and the clamping voltage V CLPGreater than the ground voltage GND. For example, the supply voltage Vdd is 3.3V to 5V, and the clamping voltage V CLP is 0.2V to 0.4V.

[0010] Furthermore, the input terminal of the judging element 130 is connected to the judging node s to receive the judging voltage V JUDGE on the judging node, and the output terminal of the judging element 130 generates the output data Dout. For example, the judging element 130 includes logic buffers 132 and 134, which are connected in series between the input terminal and the output terminal of the judging element 130. Therefore, during the sensing period, the storage cell can be judged to be in the on state or the off state according to the output data Dout of the judging element 130. Among them, each logic buffer 132, 134 can be formed by connecting two NOT gates in series.

[0011] During the sensing period, the data line DL is connected to the storage cell and receives the storage cell current Icell. When the storage cell current Icell on the data line DL is greater than the reference current I REF , the judging voltage V JUDGE will be pulled down to the ground voltage GND. Therefore, the judging element 130 outputs the output data Dout of the first logic level (for example, logic low level), indicating that the storage cell is in the on state. On the contrary, when the storage cell current Icell on the data line DL is less than the reference current I REF , the judging voltage V JUDGE will be pulled up to the supply voltage Vdd. Therefore, the judging element 130 outputs the output data Dout of the second logic level (for example, logic high level), indicating that the storage cell is in the off state.

[0012] As can be seen from the above description, the sensing element 100 can judge the storage state of the storage cell according to the storage cell current Icell generated by the storage cell.

[0013] However, the known sensing element 100 has its defects. As described above, the operational amplifier 120 of the sensing element 100 is connected to the data line DL. Since the operational amplifier 120 is connected as a negative feedback amplifier, the high gain of the amplifier will also amplify the noise and affect the judging voltage V JUDGE of the judging node s. For example, the amplifier amplifies the ground noise, resulting in the instability of the judging voltage V JUDGE of the judging node s, causing the judging element 130 to make a misjudgment. SUMMARY OF THE INVENTION

[0014] The present invention relates to a sensing element applied to a non-volatile memory. The non-volatile memory includes a memory cell. During a sensing cycle, the memory cell is connected to a data line. The sensing element includes: a first current source connected between a supply voltage and a first node, the first current source generating a reference current; a first current mirror, an input end of the first current mirror connected to the first node, a mirror end of the current mirror connected to a second node, and the second node connected to the data line; a first switch, a first end of the first switch connected to the second node, a control end of the first switch receiving an inverted reset pulse; a second switch, a first end of the second switch connected to the second node, a second end of the second switch receiving a ground voltage, a control end of the second switch receiving a reset pulse; a first transistor, a drain of the first transistor connected to a third node, a source of the first transistor connected to a second end of the first switch, a gate of the first transistor receiving a clamping voltage; a second current mirror, an input end of the second current mirror connected to the third node, a mirror end of the second current mirror connected to a fourth node; a third current mirror, an input end of the third current mirror connected to the fourth node, a mirror end of the third current mirror connected to a judgment node; a second current source connected between the supply voltage and the judgment node, the second current source generating a judgment current; and a judgment element, an input end of the judgment element connected to the judgment node, an output end of the judgment element generating an output data.

[0015] The present invention relates to a sensing element applied to a non-volatile memory. The non-volatile memory includes a storage cell. During a sensing period, the storage cell is connected to a data line and generates a storage cell current to a first node. The sensing element includes: a reference circuit connected to the first node, and the reference circuit provides a reference current; a first switch, a first end of the first switch is connected to the first node, and a control end of the first switch receives an inverted reset pulse; a second switch, a first end of the second switch is connected to the first node, a second end of the second switch receives a ground voltage, and a control end of the second switch receives a reset pulse, wherein the reset pulse and the inverted reset pulse are complementary; a sensing circuit connected between a second end of the first switch and a second node, and the sensing circuit generates a first sensing current according to the difference between the storage cell current and the reference current; a judgment circuit connected to the second node, the judgment circuit receives the first sensing current and generates an output data according to the first sensing current; wherein, when a storage cell current of the storage cell is greater than the reference current, the first sensing current is substantially zero, and the output data is a first logic level; wherein, when a storage cell current of the storage cell is less than the reference current, the first sensing current is greater than zero, and the output data is a second logic level. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to have a better understanding of the above and other aspects of the present invention, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows:

[0017] Figure 1 Schematic diagram of a known sensing element;

[0018] Figure 2 The first embodiment of the sensing element of the present invention;

[0019] Figure 3 The second embodiment of the sensing element of the present invention;

[0020] Figures 4A to 4C Schematic diagram of the operation of the sensing element of the second embodiment of the present invention during a sensing period;

[0021] Figure 4D Figure and Figure 4E Schematic diagram of related signals of the sensing element of the second embodiment of the present invention during a sensing period;

[0022] Figure 5A The first example of the voltage clamping circuit applied to the sensing element of the second embodiment of the present invention;

[0023] Figure 5B The second example of the voltage clamping circuit applied to the sensing element of the second embodiment of the present invention; and

[0024] Figure 6A And Figure 6B It is a reset pulse generator for a sensing element applied to a second embodiment and a schematic diagram of related signals.

[0025] Symbol Explanation

[0026] 100, 200, 300: Sensing element

[0027] 110, 210, 310, 350, 412, 422: Current source

[0028] 120, 414, 424: Operational amplifier

[0029] 130, 230, 360: Judgment element

[0030] 132, 134, 362, 364: Logic buffer

[0031] 232: Comparator

[0032] 320, 330, 340: Current mirror

[0033] 370: Reference circuit

[0034] 380: Sensing circuit

[0035] 390: Judgment circuit

[0036] 410, 420: Voltage clamping circuit

[0037] 600: Reset pulse generator

[0038] 610: Delay adjustment circuit

[0039] 612: Word line driver

[0040] 620: Word line load

[0041] 630: Combinational logic circuit

[0042] 631 - 63n: Combinational logic elements Detailed implementation manner

[0043] Please refer to Figure 2 , which shows the first embodiment of the sensing element of the present invention. The sensing element 200 can be applied to a non - volatile memory (not shown). The sensing element 200 includes transistor M1, transistor M2, transistor M3, current source 210, switch SW, and judgment element 230.

[0044] The source of transistor M1 is connected to the data line (DL) to receive the memory cell current Icell output from the memory cell, and the gate of transistor M1 receives a clamping voltage V CLP , and the drain of transistor M1 is connected to a decision node s. During the sensing period, the memory cell is connected to the data line DL, and the data line voltage V DL is (V CLP - V T ). Wherein, V T is the threshold voltage of transistor M1.

[0045] The current source 210 is connected between the supply voltage Vdd and the node a, and the current source 210 can generate a reference current I REF . Furthermore, transistor M2 and transistor M3 form a current mirror. The drain of transistor M2 is connected to the decision node s, the gate of transistor M2 is connected to the node a, and the source of transistor M2 receives the ground voltage GND. The drain of transistor M3 is connected to the node a, the gate of transistor M3 is connected to the node a, and the source of transistor M3 receives the ground voltage GND.

[0046] The first end of the switch SW is connected to the decision node s, the second end of the switch SW receives the ground voltage GND, and the control end of the switch SW receives a reset pulse Rst.

[0047] Furthermore, the input end of the decision element 230 is connected to the decision node s to receive the decision voltage V JUDGE on the decision node, and the output end of the decision element 230 generates the output data Dout. For example, the decision element 230 includes a comparator 232. The first input end of the comparator 232 is connected to the decision node s to receive the decision voltage V JUDGE , the second input end of the comparator 232 receives a comparison voltage V CMP , and the output end of the comparator 232 generates the output data Dout. Wherein, the comparison voltage V CMP is greater than the ground voltage GND, and the comparison voltage V CMP is less than the supply voltage Vdd.

[0048] At the beginning of the sensing period, the switch SW receives the reset pulse Rst to make the switch SW in the closed state, and the decision voltage V JUDGE on the decision node s is discharged to the ground voltage GND. After the reset pulse Rst, the switch SW becomes in the open state, and the decision voltage V JUDGEVaries according to the magnitude of the memory cell current Icell, such that the determination element 230 determines the storage state of the memory cell according to the determination voltage V JUDGE to determine the storage state of the memory cell.

[0049] For example, when the memory cell current Icell on the data line DL is greater than the reference current I REF the determination voltage V JUDGE will be charged to a higher voltage, such as the supply voltage Vdd. Since the supply voltage Vdd is greater than the determination voltage V CMP , the determination element 230 outputs output data Dout of a first logic level (e.g., logic low level), indicating that the memory cell is in the on state. Conversely, when the memory cell current Icell on the data line DL is less than the reference current I REF the determination voltage V JUDGE is maintained at the ground voltage GND, so the determination element 230 outputs output data Dout of a second logic level (e.g., logic high level), indicating that the memory cell is in the off state.

[0050] Of course, the present invention is not limited to using the comparator 232 to form the determination element 230. The determination element 230 can also be replaced by a logic buffer. For example, two NOT gates are connected in series to form a logic buffer, the input terminal of the logic buffer is connected to the determination node s, and the output terminal of the logic buffer generates the output data Dout. Therefore, during the sensing period, the storage cell can be determined to be in the on state or the off state according to the output data Dout of the determination element 230.

[0051] In the sensing element 200 of the first embodiment of the present invention, there is no operational amplifier, so the sensing element 200 is less sensitive to noise. However, since the transistor M1 is connected between the data line DL and the determination node s, the gate-source voltage V gs of the transistor M1 will affect the read speed of the sensing element 200. For example, assume that the gate-source voltage V gs is -1V. During the sensing period, the clamping voltage V CLP is the lowest ground voltage GND, then the data line voltage V DL is 1V, that is, V DL = V CLP - V gs = [0V - (-1V)] = 1V. And the data line voltage V of 1V DLBeing too high will affect the read speed of the sensing element 200. Additionally, the variation in the pulse width of the reset pulse Rst will also affect the output data Dout of the sensing element 200.

[0052] Please refer to Figure 3 which illustrates a second embodiment of the sensing element of the present invention. The sensing element 300 includes a reference circuit 370, two switches SW1 and SW2, a sensing circuit 380, and a judging circuit 390.

[0053] The data line DL is connected to node b to receive the memory cell current Icell generated by the memory cell in the non-volatile memory. The reference circuit 370 is connected to node b, and the reference circuit 370 can provide a reference current I REF2 to node b.

[0054] The first end of the switch SW1 is connected to node b, the second end of the switch SW1 is connected to the sensing circuit 380, and the control end of the switch SW1 receives an inverted reset pulse Rstb. The first end of the switch SW2 is connected to node b, the second end of the switch SW2 receives the ground voltage GND, and the control end of the switch SW2 receives a reset pulse Rst. Among them, the reset pulse Rst and the inverted reset pulse Rstb are in a complementary relationship.

[0055] The sensing circuit 380 is connected between the second end of the switch SW1 and node d. The sensing circuit 380 can generate a sensing current I REF2 based on the difference between the memory cell current Icell and the reference current I SEN_b .

[0056] The judging circuit 390 is connected to node d. The judging circuit 390 receives the sensed current I SEN_b and can generate the output data Dout based on the sensed current I SEN_b .

[0057] According to the second embodiment of the present invention, when the memory cell current Icell is greater than the reference current I EF2 , the sensing current I SEN_b is substantially equal to zero, and the output data Dout is at the first logic level. Additionally, when the memory cell current Icell is less than the reference current I EF2 , the sensing current I SEN_bGreater than zero, and the output data Dout is at the second logic level.

[0058] The reference circuit 370 includes a current source 310 and a current mirror 370. The input terminal of the current mirror 320 is connected to node a, and the mirroring terminal of the current mirror 320 is connected to node b. The current source 310 is connected between the supply voltage Vdd and node a, and the current source 310 generates a reference current I REF1 , such that the input terminal of the current mirror 320 receives the reference current I REF1 , and such that the mirroring terminal of the current mirror 320 generates the reference current I REF2 .

[0059] The current mirror 320 includes transistors M2 and M3. The drain of transistor M2 is connected to node a, the gate of transistor M2 is connected to node a, and the source of transistor M2 receives the ground voltage GND. The drain of transistor M3 is connected to node b, the gate of transistor M3 is connected to node a, and the source of transistor M3 receives the ground voltage GND. In one embodiment, transistors M2 and M3 have the same size, such that the reference current I received at the input terminal of the current mirror 320 REF1 and the reference current I flowing through the mirroring terminal REF2 are of the same magnitude, where the reference current I REF2 flows from node b to transistor M3. Of course, in other embodiments, transistors M2 and M3 may also have different sizes, such that the reference current I received at the input terminal of the current mirror 320 REF1 and the reference current I flowing through the mirroring terminal REF2 have a specific proportional relationship.

[0060] The sensing circuit 380 includes a current mirror 330 and a transistor M1. Transistor M1 serves as a clamping transistor. The drain of transistor M1 is connected to node c, the gate of transistor M1 receives a clamping voltage V CLP , and the source of transistor M1 is connected to the second terminal of the switch SW1. Wherein, the source of transistor M1 can receive the sensing current I SEN_a . Furthermore, the clamping voltage V CLP is generated by a voltage clamping circuit. The detailed voltage clamping circuit will be disclosed in Figure 5A and Figure 5B .

[0061] The input terminal of the current mirror 330 is connected to node c for receiving the sensing current I SEN_a。The mirroring terminal of current mirror 330 is connected to node d to generate a sense current I SEN_b 。Among them, current mirror 330 includes transistors M4 and M5. The drain of transistor M4 is connected to node c, the gate of transistor M4 is connected to node c, and the source of transistor M4 receives the supply voltage Vdd. The drain of transistor M5 is connected to node d, the gate of transistor M5 is connected to node c, and the source of transistor M5 receives the supply voltage Vdd. In one embodiment, transistors M4 and M5 have the same size, so that the sense current I flowing through the input terminal of current mirror 330 SEN_a is the same as the sense current I flowing through the mirroring terminal SEN_b in magnitude. Of course, in other embodiments, transistors M4 and M5 can also have different sizes, so that the sense current I flowing through the input terminal of current mirror 330 SEN_a has a specific proportional relationship with the sense current I flowing through the mirroring terminal SEN_b .

[0062] The judgment circuit 390 includes a current mirror 340, a current source 350, and a judgment element 360. The input terminal of current mirror 340 is connected to node d to receive the sense current I SEN_b 。The mirroring terminal of current mirror 340 is connected to the judgment node s to generate a sense current I SEN_c 。The current source 350 is connected between the supply voltage Vdd and the judgment node s, and the current source 350 generates a judgment current I JUDGE 。

[0063] Current mirror 340 includes transistors M6 and M7. The drain of transistor M6 is connected to node d, the gate of transistor M6 is connected to node d, and the source of transistor M6 receives the ground voltage GND. The drain of transistor M7 is connected to the judgment node s, the gate of transistor M7 is connected to node d, and the source of transistor M7 receives the ground voltage GND. In one embodiment, transistors M6 and M7 have the same size, so that the sense current I received at the input terminal of current mirror 340 SEN_b is the same as the sense current I flowing through the mirroring terminal SEN_c in magnitude. Of course, in other embodiments, transistors M6 and M7 can also have different sizes, so that the sense current I received at the input terminal of current mirror 340 SEN_b has a specific proportional relationship with the sense current I flowing through the mirroring terminal SEN_c .

[0064] The input terminal of the judgment element 360 is connected to the judgment node s to receive the judgment voltage V on the judgment node JUDGE, the output terminal of the determination element 360 generates the output data Dout. For example, the determination element 360 includes logic buffers 362 and 364, which are connected in series between the input terminal and the output terminal of the determination element 360.

[0065] Please refer to Figures 4A to 4C , which shows the operation schematic diagram of the sensing element of the second embodiment of the present invention during the sense cycle. Figure 4D and Figure 4E is the schematic diagram of the related signals of the sensing element of the second embodiment of the present invention during the sense cycle.

[0066] According to an embodiment of the present invention, when the storage unit connected to the data line DL is in the off state, the operation of the sensing element 300 is as Figure 4A , Figure 4B and Figure 4D shown. Basically, a sense cycle includes a reset phase P1, a pre-charge phase P2, and a sense phase P3.

[0067] First, as Figure 4A and Figure 4D shown, at the beginning of the sense cycle, between time point ta and time point tb is the reset phase P1 of the sense cycle. The switch SW2 receives the reset pulse Rst, making the switch SW2 in the closed state, and the switch SW1 receives the inverted reset pulse Rstb, making the switch SW1 in the open state. Therefore, the data line voltage V DL is reset to the ground voltage GND, that is, V DL = 0V.

[0068] As Figure 4B and Figure 4D shown, between time point tb and time point tc is the pre-charge period P2 of the sense cycle. The signal of the reset pulse Rst drops, making the switch SW2 in the open state and the switch SW1 in the closed state. Since the storage unit connected to the data line DL is in the off state, the storage unit current Icell is very small, almost zero (Icell = 0). Moreover, since the reference circuit 320 generates the reference current I REF2 , the transistor M1 is turned on, and the sensing current I SEN_a generated by the transistor M1 is equal to the reference current I REF2 , and the data line DL will be pre-charged to the voltage (VCLP -V gs1 ). Among them, the voltage V gs1 is the gate-source voltage of the transistor M1 that generates the sense current I SEN_a . That is to say, when the pre-charge period P2 ends, the target voltage required on the node b can be adjusted by using the clamping voltage V CLP .

[0069] As Figure 4B and Figure 4D shown, the sensing stage P3 of the sensing period is between the time point tc and the time point td. Since the storage state of the storage cell is in the off state, the storage cell current Icell on the data line DL is very small and almost zero (Icell = 0). Therefore, during the sensing stage P3 between the time point tc and the time point td, the sense current I SEN_a is equal to the reference current I REF2 , and the voltage on the data line DL remains unchanged and is maintained at the voltage (V CLP -V gs1 ).

[0070] In addition, according to the sense current I SEN_a , the mirror end of the current mirror 330 will generate a sense current I SEN_b flowing to the node d and inputting to the input end of the current mirror 340. And the current mirror 340 generates a sense current I SEN_b according to the received sense current I SEN_c , and outputs the sense current I SEN_c from the mirror end of the current mirror 340 to the judgment node s. At the mirror end of the current mirror 340, since the sense current I SEN_c is greater than the judgment current I JUDGE , the voltage on the judgment node s will be pulled down to the ground voltage GND. That is to say, the judgment voltage V JUDGE is 0V. Therefore, during the sensing stage P3, the judgment element 360 can output the output data Dout of the first logic level (such as the logic low level "Lo"), indicating that the storage cell is in the off state.

[0071] When the storage cell connected to the data line DL is in the on state, the operation of the sensing element 300 is as Figure 4A , Figure 4C and Figure 4E shown. Basically, in Figure 4A and Figure 4E , the signals in the reset stage P1 are the same as Figure 4A and Figure 4D , which will not be elaborated here.

[0072] like Figure 4C and Figure 4E As shown, the period between time point tb and time point tc is the precharge period P2 of the sensing period. The signal of the reset pulse Rst falls, so that the switch SW2 becomes an opened state, and the switch SW1 becomes a closed state. Since the memory cell connected to the data line DL is in an on state, the memory cell current Icell is greater than the reference current I REF2 Therefore, the sensing current I SEN_a =0, transistor M1 is turned off, so that the data line DL is precharged to a voltage (V CLP -V T ). Wherein, voltage is the threshold voltage of transistor M1. For example, the threshold voltage of transistor M1 is V T is 0.7V.

[0073] like Figure 4C and Figure 4D As shown, the period between time point tc and time point td is the sensing phase P3 of the sensing cycle. Since the storage state of the memory cell is in the on state, the memory cell current Icell on the data line DL is greater than the reference current I REF2 Therefore, during the sensing phase P3 between the time point tc and the time point td, the voltage of the node b on the data line DL will be charged and increased from the voltage (V CLP -V T ) starts to rise. That is, the data line voltage V DL will be greater than the voltage (V CLP -V T ), that is, V DL >(V CLP -V T ). The transistor M1 is continuously turned off, so the sensing current I SEN_a , so that the sensing current I SEN_a Essentially zero.

[0074] In addition, since the sensing current I SEN_a = zero, the sensing current I generated by the mirror terminal of the current mirror 330 SEN_b is also 0. Similarly, the current mirror 340 receives the sensing current I SEN_b The generated sensing current I SEN_c is also 0. Therefore, the voltage on the determination node s is pulled up to the supply voltage Vdd, and the determination element 360 can output the output data Dout of the second logic level (eg, logic low level “Hi”), indicating that the memory cell is in the on state.

[0075] In the above description, it is assumed that transistors M2, M3, M4, M5, M6, and M7 have the same size. The reference current I REF1 is the same size as the reference current I REF2 . The sense current I SEN_a , the sense current I SEN_b is the same size as the sense current I SEN_c . The judgment current I JUDGE generated by the current source 350 is less than the reference current I REF1 generated by the current source 310.

[0076] Of course, in other embodiments, the transistors in the current mirrors 320, 330, and 340 can have different sizes arbitrarily. At this time, there will be other proportional relationships between the reference current I REF1 and the reference current I REF2 . There will be other proportional relationships between the sense current I SEN_a , the sense current I SEN_b and the sense current I SEN_c . And the magnitude relationship between the judgment current I JUDGE and the reference current I REF1 can also be corrected correspondingly.

[0077] From the above description, it can be seen that the sensing element 300 of the second embodiment of the present invention does not include an operational amplifier, so the sensing element 300 is less sensitive to noise. In addition, in the sensing element 300, the clamping voltage V CLP can be used to determine the initial data line voltage V DL on the data line DL, so the initial data line voltage V DL can be effectively reduced. Furthermore, since the storage cell current Icell only needs to be higher than the reference current I REF1 generated by the current source 310, the storage state of the storage cell will be determined as the on state. Therefore, the reference current I REF1 can be flexibly adjusted according to actual needs, and the sensing margin of the on state can be improved. Furthermore, in other embodiments, adjusting the sizes of the transistors in the current mirrors 330 and 340 can appropriately scale the sense current I SEN_b . In addition, adjusting the sizes of the transistors in the current mirror 320 can also improve the change of the sensing margin.

[0078] Please refer to Figure 5A , which shows the first example of the voltage clamping circuit applied to the sensing element of the second embodiment of the present invention. The voltage clamping circuit 410 provides the clamping voltage V CLPto the gate of transistor M1 in the sensing element 300. As Figure 5A shown, the voltage clamping circuit 410 includes a current source 412, a transistor Ma, and an operational amplifier 414.

[0079] The current source 412 is connected between the supply voltage Vdd and the node e. The current source 412 can generate a bias current I BIAS1 . The drain of the transistor Ma is connected to the node e. The gate of the transistor Ma is connected to the output terminal of the operational amplifier 414. The source of the transistor Ma receives the ground voltage GND. Furthermore, the first input terminal of the operational amplifier 414 receives a control voltage Vctrl, and the second input terminal of the operational amplifier 414 is connected to the node e. Therefore, when the voltage clamping circuit 410 operates normally, the voltage on the node e is equal to the control voltage Vcrtrl. That is to say, the clamped voltage V CLP output by the voltage clamping circuit 410 is equal to the control voltage Vctrl.

[0080] Since the voltage clamping circuit 410 is connected to the gate of transistor M1 in the sensing element 300, when the control voltage Vctrl is 1V, the clamped voltage V CLP is also 1V.

[0081] Please refer to Figure 5B , which is shown as the second example of the voltage clamping circuit applied to the sensing element in the second embodiment of the present invention. The voltage clamping circuit 420 provides a clamped voltage V CLP to the gate of transistor M1 in the sensing element 300. As shown in Figure 5B, the voltage clamping circuit 420 includes a current source 422, a transistor Mb, a transistor Mc, and an operational amplifier 424.

[0082] The current source 422 is connected between the supply voltage Vdd and the node f. The current source 422 can generate a bias current I BIAS2。The drain of transistor Mb is connected to node f, the gate of transistor Mb is connected to node f, the source of transistor Mb is connected to the gate of transistor M1 in the sensing element 300, and the source of transistor Mb is connected to node g. Therefore, transistor Mb is a diode connected transistor. The drain of transistor Mc is connected to node g, the gate of transistor Mc is connected to the output of the operational amplifier 424, and the source of transistor Mc receives the ground voltage GND. Furthermore, a control voltage Vctrl is received at the first input of the operational amplifier 424, and the second input of the operational amplifier 424 is connected to node g. Therefore, when the voltage clamping circuit 420 operates normally, the voltage on node g will be equal to the control voltage Vctrl. And the voltage on the gate of transistor Mb will be equal to the control voltage Vcrtrl plus the gate-source voltage V of transistor Mb gsb 。That is to say, the clamped voltage V output by the voltage clamping circuit 410 CLP is equal to the control voltage Vctrl plus the gate-source voltage V gsb , that is, V CLP =Vctrl + V gsb 。

[0083] For example, design transistors M1 and Mb in the sensing element 300 to have the same size, and set the reference current I REF2 to be the same as the bias current I BIAS2 , then the variation of the gate-source voltage can be eliminated. In the sensing element 300, the data line voltage V DL is equal to the clamped voltage V CLP minus the gate-source voltage V of transistor M1 gs1 . That is to say, V DL =(V CLP - V gs1 )=(Vctrl + V gsb ) - V gs1 =Vctrl, that is, the data line voltage V DL will be equal to the control voltage Vctrl. For example, assume that the control voltage Vctrl is 0.3V, the gate-source voltage V of transistor Mb gsb is 0.7V, and the gate-source voltage V of transistor M1 gs1 is 0.7V, then the clamped voltage V CLP is 1V, and the data line voltage V DL can be accurately pre-charged to 0.3V.

[0084] In addition, the sensing element 300 of the second embodiment of the present invention uses logic buffers 362 and 364 to form the determination element 360. Of course, the present invention is not limited thereto. The determination element 360 of the second embodiment can also be replaced by the determination element 230 of the first embodiment, that is, a comparator 232 is used to form the determination element.

[0085] Similarly, the present invention does not limit the architectures of the current mirrors 320, 330, and 340 in FIG. 3. Those skilled in the art can use other current mirrors with similar functions to implement the sensing element of the present invention.

[0086] Generally speaking, since the pulse width variation of the reset pulse will affect the sensing time and determination result of the sensing element 300. To improve the determination result of the sensing element 300, the present invention discloses a reset pulse generator. Of course, the present invention does not limit the circuit structure of the reset pulse generator, and those skilled in the art can use other circuits to implement the reset pulse generator.

[0087] As is well known, an SSD at least includes a memory cell array and a sensing module. The sensing module includes a plurality of sensing elements, and these sensing elements are connected to corresponding multiple data lines in the memory cell array to determine the storage state of the corresponding memory cell in a sensing cycle. For example, the sensing module includes 16 sensing elements, which are connected to 16 corresponding data lines in the memory cell array. Therefore, in a sensing cycle, the sensing module can generate 16 output data corresponding to the storage states of 16 memory cells.

[0088] Please refer to Figure 6A and Figure 6B , which shows a schematic diagram of a reset pulse generator and its related signals applied to the sensing element of the second embodiment. The reset pulse generator 600 includes a delay adjustment circuit 610, a wordline driver 612, a word line load 620, and a combinational logic circuit 630.

[0089] The delay adjustment circuit 610 receives a clock signal CK and an adjustment signal T. The wordline driver 612 is connected to the output end of the delay adjustment circuit 610, and the wordline driver 612 generates a delayed clock signal CK D to the word line load 620. The word line load 620 generates a plurality of loading signals D1 to D n。The combinational logic circuit 630 receives multiple load signals D1 to D n and the clock signal CK, and generates multiple pulse signals Φ1 to Φn. In the sensing element 300, the control terminal of the switch SW2 receives one of the multiple pulse signals Φ1 to Φn and serves as the reset pulse Rst.

[0090] The word line load 620 includes n serially connected loading devices 621 to 62n. For example, n is equal to 1024. The first loading device 621 receives the delayed clock CK D 。Each loading device 621 to 62n generates a corresponding load signal D1 to D n 。Among them, each loading device can delay the input signal by a fixed phase difference to become the output signal. For example, the loading device 622 receives the load signal D1 and generates the load signal D2, and the load signal D2 lags behind the load signal D1 by a fixed phase difference.

[0091] The combinational logic circuit 630 includes n combinational logic devices 631 to 63n. The first end of each combinational logic device 631 to 63n receives the clock signal CK, and the second end of each combinational logic device 631 to 63n receives the corresponding load signal D1 to D n ,and the output ends of each combinational logic device 631 to 63n generate the pulse signals Φ1 to Φn. Furthermore, the combinational logic devices 631 to 63n have the same structure. Taking the combinational logic device 631 as an example, it includes an AND gate and a NOT gate. The first input terminal of the AND gate receives the clock signal CK, the input terminal of the NOT gate receives the load signal D1, the output terminal of the NOT gate is connected to the second input terminal of the AND gate, and the output terminal of the AND gate generates the pulse signal Φ1.

[0092] According to an embodiment of the present invention, the sensing module receives a part of the pulse signals Φ1 to Φn generated by the reset pulse generator 600. For example, n and k are positive integers, and n is greater than or equal to k. The sensing module includes k sensing elements, and the structure of each sensing element is similar to Figure 3 。The k sensing elements receive k pulse signals Φ1 to Φk as the corresponding reset signals Rst.

[0093] That is to say, the first sensing element receives the pulse signal Φ1 as the reset signal Rst. The second sensing element receives the pulse signal Φ2 as the reset signal Rst. And so on, the kth sensing element receives the pulse signal Φk as the reset signal Rst.

[0094] Such as Figure 6BAs shown, one cycle of the clock signal CK is a sensing cycle. Furthermore, the adjustment signal T controls the delay adjustment circuit 610 so that there is a delay time of t1 between the clock signal CK and the delayed clock CK D and there is a delay time of t2 between the delayed clock CK D and the load signal D k . For example, in the sensing module, the k-th sensing element receives the pulse signal Φk as the reset signal Rst, then the pulse width W of the reset signal Rst is (t1 + t2). Therefore, the reset pulse Rst with the optimal pulse width can be applied to the k-th sensing element of the sensing module.

[0095] In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to that defined by the appended patent application scope.

Claims

1. A sensing element applied to a non-volatile memory, the non-volatile memory including memory cells, and during a sensing cycle, the memory cells are connected to a data line. The sensing element includes: A first current source connected between a supply voltage and a first node, the first current source generating a reference current; A first current mirror, an input terminal of the first current mirror being connected to the first node, a mirroring terminal of the current mirror being connected to a second node, and the second node being connected to the data line; A first switch, a first end of the first switch being connected to the second node, a control terminal of the first switch receiving an inverted reset pulse; A second switch, a first end of the second switch being connected to the second node, a second end of the second switch receiving a ground voltage, a control terminal of the second switch receiving a reset pulse; A first transistor, a drain of the first transistor being connected to a third node, a source of the first transistor being connected to a second end of the first switch, and a gate of the first transistor receiving a clamping voltage; A second current mirror, an input terminal of the second current mirror being connected to the third node, a mirroring terminal of the second current mirror being connected to a fourth node; A third current mirror, an input terminal of the third current mirror being connected to the fourth node, a mirroring terminal of the third current mirror being connected to a judgment node; A second current source connected between the supply voltage and the judgment node, the second current source generating a judgment current; And A judgment element, an input terminal of the judgment element being connected to the judgment node, and an output terminal of the judgment element generating output data.

2. The sensing element according to claim 1, wherein the first current mirror includes: A second transistor, a drain of the second transistor being connected to the first node, a gate of the second transistor being connected to the first node, and a source of the second transistor receiving the ground voltage; And A third transistor, a drain of the third transistor being connected to the second node, a gate of the third transistor being connected to the first node, and a source of the third transistor receiving the ground voltage.

3. The sensing element according to claim 1, wherein the second current mirror includes: A second transistor, a drain of the second transistor being connected to the third node, a gate of the second transistor being connected to the third node, and a source of the second transistor receiving the supply voltage; And A third transistor, a drain of the third transistor being connected to the fourth node, a gate of the third transistor being connected to the third node, and a source of the third transistor receiving the supply voltage.

4. The sensing element according to claim 1, wherein the third current mirror includes: A second transistor, a drain of the second transistor being connected to the fourth node, a gate of the second transistor being connected to the fourth node, and a source of the second transistor receiving the ground voltage; And A third transistor, a drain of the third transistor being connected to the judgment node, a gate of the third transistor being connected to the fourth node, and a source of the third transistor receiving the ground voltage.

5. The sensing element according to claim 1, wherein the judgment element includes: A comparator, wherein a first input terminal of the comparator is connected to the judgment node, a second input terminal of the comparator receives a comparison voltage, and an output terminal of the comparator generates the output data, wherein the comparison voltage is greater than the ground voltage and less than the supply voltage.

6. The sensing element according to claim 1, further comprising a voltage clamping circuit, comprising: A third current source connected between the supply voltage and a fifth node, the third current source generating a bias current, and the voltage of the fifth node being the clamping voltage; A second transistor, wherein a drain of the second transistor is connected to the fifth node, and a source of the second transistor receives the ground voltage; And An operational amplifier, wherein a first input terminal of the operational amplifier receives a control voltage, a second input terminal of the operational amplifier is connected to the fifth node, and an output terminal of the operational amplifier is connected to a gate of the second transistor.

7. The sensing element according to claim 1, further comprising a voltage clamping circuit, comprising: A third current source connected between the supply voltage and a fifth node, the third current source generating a bias current, and the voltage of the fifth node being the clamping voltage; A second transistor, wherein a drain of the second transistor is connected to the fifth node, a gate of the second transistor is connected to the fifth node, and a source of the second transistor receives a sixth node; A third transistor, wherein a drain of the third transistor is connected to the sixth node, and a source of the third transistor receives the ground voltage; And An operational amplifier, wherein a first input terminal of the operational amplifier receives a control voltage, a second input terminal of the operational amplifier is connected to the sixth node, and an output terminal of the operational amplifier is connected to a gate of the third transistor.

8. The sensing element according to claim 1, further comprising a reset pulse generator, and the reset pulse generator comprises: A delay adjustment circuit that receives a clock signal and an adjustment signal; A word line driver connected to an output terminal of the delay adjustment circuit, and the word line driver generates a delayed clock signal; A word line load that receives the delayed clock signal and generates a plurality of load signals; And A combinational logic circuit that receives the clock signal and the load signals and generates a plurality of pulse signals; Wherein, a control terminal of the second switch receives one of the pulse signals and serves as the reset pulse.

9. The sensing element according to claim 1, wherein when the memory cell current of the memory cell is less than the reference current, the first transistor is turned on, and the judgment voltage of the judgment node is pulled down, and the judgment element generates the output data of the first logic level, representing that the memory cell is in the off state.

10. The sensing element according to claim 9, wherein when the memory cell current of the memory cell is greater than the reference current, the first transistor is turned off, so that the judgment voltage of the judgment node is pulled up, and the judgment element generates the output data of the second logic level, representing that the memory cell is in the on state.

11. A sensing element applied to a non-volatile memory, the non-volatile memory including memory cells, during a sensing cycle, the memory cells being connected to a data line and generating a memory cell current to a first node, the sensing element including: A reference circuit connected to the first node, and the reference circuit providing a reference current; A first switch, a first end of the first switch being connected to the first node, a control end of the first switch receiving an inverted reset pulse; A second switch, a first end of the second switch being connected to the first node, a second end of the second switch receiving a ground voltage, a control end of the second switch receiving a reset pulse, wherein the reset pulse and the inverted reset pulse are in a complementary relationship; A sensing circuit connected between a second end of the first switch and a second node, the sensing circuit generating a first sensing current according to a difference between the memory cell current and the reference current; And A judging circuit connected to the second node, the judging circuit receiving the first sensing current and generating output data according to the first sensing current; Wherein, when the memory cell current of the memory cell is greater than the reference current, the first sensing current is substantially equal to zero, and the output data is a first logic level; Wherein, when the memory cell current of the memory cell is less than the reference current, the first sensing current is greater than zero, and the output data is a second logic level.

12. The sensing element according to claim 11, wherein during a reset phase of the sensing cycle, the first switch is in an open state, the second switch is in a closed state, and a voltage of the first node is set to be equal to the ground voltage.

13. The sensing element as claimed in claim 11, wherein the sensing circuit includes a clamping transistor connected to the second end of the first switch, and the gate of the clamping transistor receives a clamping voltage; wherein, During a pre-charge phase of the sensing cycle, the first switch is in a closed state, the second switch is in an open state, the first node is pre-charged to an initial voltage, and the initial voltage is less than a clamping voltage.

14. The sensing element according to claim 13, wherein during a sensing phase after the pre-charge phase in the sensing cycle, when the memory cell current is greater than the reference current, the clamping transistor is turned off, the voltage of the first node is greater than the initial voltage, and the output data indicates that the memory cell is in an on state.

15. The sensing element according to claim 13, wherein during a sensing phase after the pre-charge phase in the sensing cycle, when the memory cell current is less than the reference current, the clamping transistor is turned on, and the output data indicates that the memory cell is in an off state.

16. The sensing element according to claim 11, wherein during a sensing phase of the sensing cycle, when the memory cell current is less than the reference current, the output data indicates that the memory cell is in an off state.

17. The sensing element according to claim 16, wherein during the sensing phase of the sensing cycle, when the memory cell current is greater than the reference current, the output data indicates that the memory cell is in an on state.

18. The sensing element according to claim 11, wherein the judging circuit receives a judging current, and the judging circuit generates a second sensing current according to the first sensing current; wherein, When the second sensing current is greater than the judging current, the output data is the second logic level; And when the second sensing current is less than the judging current, the output data is the first logic level.

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