Array substrate, display panel

Abstract

The present application provides an array substrate and a display panel, relating to the field of display technologies. The display panel can ensure that, while meeting the requirements for the resistance of the wiring, the line width is minimized as much as possible to improve the aperture ratio of the product. The array substrate includes: a plurality of touch control units, each touch control unit including a plurality of sub-pixels arranged in an array; the sub-pixels include a first electrode; a plurality of wiring units; the wiring units include a first electrode line and a second electrode line that at least partially overlap in a direction perpendicular to the substrate; the first electrode line includes at least one first parallel portion, and the second electrode line includes at least one second parallel portion; in the wiring unit, the first parallel portion of the first electrode line and the second parallel portion of the second electrode line are arranged in parallel; in the wiring unit, at least one of the first electrode line and the second electrode line is electrically connected to the first electrode included in one of the plurality of touch control units arranged in the first direction.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to an array substrate and a display panel. Background Art

[0002] With the rapid development of touch display screen technologies and the increasing market demand for touch display screens, touch display technologies have become an indispensable part of human-computer interaction and are widely used in industries such as education, commerce, finance, and services.

[0003] Currently, capacitive touch screens designed based on In Cell Touch technology have characteristics such as low production cost, high stability, and relatively good touch technology effects, occupying the mainstream market. In Cell Touch technology is to set touch electrodes inside the display panel, which will have a greater impact on the product aperture ratio, thereby reducing the product transmittance and display effect. Summary of the Invention

[0004] Embodiments of the present application provide an array substrate and a display panel. The embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, an array substrate is provided, including:

[0006] A substrate;

[0007] A plurality of touch units arranged in an array on the substrate, the touch units including a plurality of sub-pixels arranged in an array; the sub-pixels include a first electrode;

[0008] A plurality of wiring units, the wiring units including a first electrode line and a second electrode line that at least partially overlap in a direction perpendicular to the substrate; both the first electrode line and the second electrode line are arranged in a first direction, and the line width of the first electrode line is smaller than the line width of the second electrode line; the first electrode line at least includes a first parallel portion, and the second electrode line at least includes a second parallel portion; in the wiring unit, the first parallel portion of the first electrode line and the second parallel portion of the second electrode line are arranged in parallel, and at least one of the first electrode line and the second electrode line is electrically connected to the first electrode included in one of the plurality of touch units arranged in the first direction.

[0009] Optionally, the first electrode line includes a plurality of continuously arranged first parallel portions, and the second electrode line includes a plurality of intermittently arranged second parallel portions;

[0010] The first parallel portion and the second parallel portion are both arranged between at least two of the sub-pixels arranged in the second direction.

[0011] Optionally, the touch unit further includes a plurality of connection electrodes;

[0012] The plurality of connection electrodes arranged along the first direction include a first connection electrode and a second connection electrode. The first electrode line is electrically connected to the first connection electrode and the second connection electrode respectively, and at least one of the first connection electrodes is electrically connected to the corresponding first electrode, and the second connection electrode is not electrically connected to the first electrode.

[0013] Optionally, in the routing unit, the first end of the second parallel portion of the second electrode line is electrically connected to the corresponding connection electrode and the first parallel portion of the first electrode line respectively, and the second end is electrically connected to another connection electrode;

[0014] In the routing unit, two adjacent second parallel portions arranged along the first direction are electrically connected through the connection electrode.

[0015] Optionally, the connection electrode and the first electrode are arranged on the same layer;

[0016] The first connection electrode is connected to the corresponding first electrode, and the second connection electrode is disconnected from the corresponding first electrode.

[0017] Optionally, the array substrate further includes a plurality of gate lines arranged along the first direction; the orthographic projection of the gate lines on the substrate is arranged between the orthographic projections of two adjacent rows of the first electrodes arranged along the first direction on the substrate;

[0018] Wherein, the second parallel portion of the second electrode line is arranged between two adjacent gate lines arranged along the first direction; the second electrode line and the gate lines are arranged on the same layer and do not overlap each other.

[0019] Optionally, the part of the gate line located in the first region includes a continuously arranged first part, an intermediate part and a second part; the first region is the region where the sub-pixels are located, and the connection electrodes in the first region are disconnected from the first electrodes in the first region;

[0020] Wherein, the connection electrodes in the first region cover the first part, the first electrodes in the first region cover the second part, and the intermediate part is not covered by the connection electrodes or the first electrodes located in the first region;

[0021] The first region further includes a shielding electrode, the shielding electrode and the gate lines are arranged on the same layer and do not overlap each other; the shielding electrode overlaps at least the disconnected part between the connection electrodes and the first electrodes in the first region in the direction perpendicular to the substrate.

[0022] Optionally, the shielding electrode also partially overlaps with the first electrode in the first region in a direction perpendicular to the substrate.

[0023] Optionally, the shielding electrode includes a strip-shaped electrode and is arranged parallel to the gate line.

[0024] Optionally, the array substrate further includes a plurality of data lines arranged along the second direction; a positive projection of the data line on the substrate is disposed between positive projections of two adjacent rows of the first electrodes arranged along the second direction on the substrate;

[0025] Wherein, the first electrode line and the data line are arranged in the same layer and do not overlap with each other.

[0026] Optionally, the sub-pixel further includes a transistor, and the transistor includes a control electrode, a first electrode, and a second electrode; the control electrode is connected to the gate line, and the first electrode is connected to the data line;

[0027] The control electrode, the second electrode line, the gate line, and the shielding electrode are arranged in the same layer; the first electrode, the second electrode, the data line, and the first electrode line are arranged in the same layer.

[0028] Optionally, the transistor includes a bottom-gate transistor; the transistor further includes an active layer; the sub-pixel further includes a gate insulating layer, an interlayer dielectric layer, and a planarization layer;

[0029] The gate insulating layer covers the control electrode, the second electrode line, the gate line, and the shielding electrode; the active layer is disposed on a side of the gate insulating layer away from the substrate and overlaps with the control electrode in a direction perpendicular to the substrate; the interlayer dielectric layer covers the active layer; the first electrode and the second electrode are disposed on a side of the interlayer dielectric layer away from the substrate and are respectively electrically connected to the active layer; the planarization layer at least covers the first electrode, the second electrode, the data line, and the first electrode line; the connection electrode and the first electrode are disposed on a side of the planarization layer away from the substrate.

[0030] Optionally, the sub-pixel further includes a first via hole;

[0031] The first via hole is configured to penetrate through the gate insulating layer and the planarization layer to expose a second end of the second parallel portion of the second electrode line; the connection electrode is overlapped with the second end of the second parallel portion through the first via hole.

[0032] Optionally, an opening distance of the first via hole along the first direction is greater than a line width of an exposed portion of the second end of the second parallel portion, and the connection electrode covers a top surface and a side surface of the exposed portion of the second end of the second parallel portion.

[0033] Optionally, the sub-pixel further includes a second via hole;

[0034] The second via hole includes a first sub-hole and a second sub-hole connected to each other. The first sub-hole is configured to penetrate through the gate insulating layer and the planarization layer to expose a part of the first end of the second parallel portion of the second electrode line; the second sub-hole is configured to penetrate through the planarization layer to expose a part of the first parallel portion of the first electrode line;

[0035] The connecting electrode overlaps with the first end of the second parallel portion through the first sub-hole and overlaps with the first parallel portion through the second sub-hole.

[0036] Optionally, the orthographic projection of the second via hole on the substrate respectively overlaps with the orthographic projection of the exposed part of the first end of the second parallel portion on the substrate and the orthographic projection of the exposed part of the first parallel portion on the substrate;

[0037] The connecting electrode covers the top surface and the side surface of the exposed part of the first end of the second parallel portion, and the top surface and the side surface of the exposed part of the first parallel portion.

[0038] On the other hand, a display panel is provided, including the above-mentioned array substrate.

[0039] Optionally, the display panel further includes a color filter substrate, and the color filter substrate is disposed opposite to the array substrate;

[0040] Wherein, the color filter substrate includes a black matrix; the array substrate includes a substrate and a shielding electrode; the first orthographic projection of the shielding electrode on the substrate is located inside the second orthographic projection of the black matrix on the substrate, and a partial boundary of the first orthographic projection coincides with a partial boundary of the second orthographic projection.

[0041] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically exemplified below. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0043] Figure 1 Schematically shows a structural diagram of an array substrate;

[0044] Figure 2 Schematically shows a structural diagram of a touch control unit;

[0045] Figure 3 In figure a is Figure 2 An enlarged view of area S1 in, figure b is Figure 2 An enlarged view of area S2 in;

[0046] Figure 4a Schematically shows a structural diagram of another array substrate;

[0047] Figure 4b In, figures A - C schematically show Figure 4a A manufacturing process structural diagram of data lines, a first parallel part and a second parallel part in;

[0048] Figure 5 Is Figure 4a An enlarged view of area L in;

[0049] Figure 6 Is along Figure 5 A cross - sectional view in the CC direction in;

[0050] Figure 7 Is along Figure 5 A cross - sectional view in the DD direction in;

[0051] Figure 8 Is along Figure 5 A cross - sectional view in the EE direction in;

[0052] Figure 9 Is along Figure 5 A cross - sectional view in the FF direction in;

[0053] Figures 10 - 15 Schematically shows a manufacturing process structural diagram of an array substrate;

[0054] Figure 16 Schematically shows a structural diagram in which a connection electrode and a first electrode are independently arranged;

[0055] Figure 17 Schematically shows a structural diagram in which a connection electrode and a first electrode are connected;

[0056] Figure 18 Schematically shows a structural diagram of a connection electrode and a first electrode in different sub - pixels within a single touch control unit;

[0057] Figure 19 Schematically shows a structural diagram without a shielding electrode provided;

[0058] Figure 20 Schematically shows a structural schematic diagram of a shielding electrode arrangement;

[0059] Figure 21 Schematically shows a comparison diagram of the opening areas of two structures;

[0060] Figure 22 Schematically shows a structural schematic diagram of a transistor;

[0061] Figure 23 Schematically shows a structural schematic diagram of a display panel. Detailed implementation manners

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0063] In the embodiments of the present application, terms such as "first" and "second" are used to distinguish identical or similar items with basically the same functions and effects, only for clearly describing the technical solutions of the embodiments of the present application, and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. In addition, the meaning of "a plurality of" is two or more, and the meaning of "at least one" is one or more, unless otherwise clearly and specifically defined.

[0064] The embodiments of the present application provide an array substrate, in combination with Figures 1 - 4a as shown, including:

[0065] A substrate ( Figure 1 not shown); the material of the substrate is not limited. By way of example, it may be a rigid material, such as: glass.

[0066] A plurality of touch units 1 arranged in an array on the substrate, and the touch unit includes a plurality of sub-pixels arranged in an array ( Figure 4a labeled as 4 in the figure); the sub-pixel includes a first electrode 11.

[0067] A plurality of wiring units 2, referring to Figure 4a as shown, the wiring unit includes a first electrode line 21 and a second electrode line 22 that overlap at least partially in a direction perpendicular to the substrate; both the first electrode line 21 and the second electrode line 22 extend along a first direction ( Figure 4aIt is arranged in the OA direction in [description], and the line width of the first electrode line is smaller than that of the second electrode line; the first electrode line 21 includes at least one first parallel part 210, and the second electrode line 22 includes at least one second parallel part 220; in the routing unit, the first parallel part of the first electrode line and the second parallel part of the second electrode line are arranged in parallel, and at least one of the first electrode line and the second electrode line is electrically connected to a first electrode included in one of the plurality of touch units arranged along the first direction.

[0068] In this array substrate, in order to reduce the implementation difficulty of In Cell Touch, the first electrode can be time-division multiplexed. That is, the first electrode is used as a driving electrode during the display stage to drive the liquid crystal to deflect; while during the touch stage, it is used as a touch sensing electrode to form a touch capacitance with the finger to achieve the touch effect.

[0069] When this array substrate is applied to a liquid crystal touch display screen, the plurality of touch units are equivalent to a plurality of touch sensing electrode blocks (Touch Sensor). It should be noted that the sizes of the plurality of touch units 1 arranged along the first direction (such as Figure 1 the OA direction shown) can be the same, or they can also be different, which is not limited here. Figure 1 In [description], taking the sizes of the touch units arranged along the first direction as the same as an example for illustration. For the convenience of wiring, the sizes of the plurality of touch units arranged along the second direction (such as Figure 1 the OB direction shown) are the same. The specific number of sub-pixels included in the above touch units is not limited and can be selected according to the actual situation. Figure 1 Taking the touch units of N rows and M columns as an example for illustration, the values of N and M can be selected according to the actual panel size.

[0070] Refer to Figure 3 As shown in Figure b in [reference], the first electrodes 11 of all sub-pixels in the same touch unit are electrically connected. For example, they can be electrically connected through the trace 5, and between adjacent two rows, they can be electrically connected through the electrode 6. Refer to Figure 3 As shown in Figure a in [reference], the first electrodes 11 between adjacent touch units are independent of each other and there is no electrical connection relationship, and the trace 5 is disconnected between adjacent touch units.

[0071] Refer to Figure 4bAs shown, the line width W1 of the first electrode line is less than the line width W2 of the second electrode line. The difference between the two is not limited here. For example, the absolute value of the difference between the line width of the first electrode line and the line width of the second electrode line is greater than or equal to a positive preset value, and this positive preset value can be selected according to actual impedance requirements. For example, this positive preset value can be 0.8μm, 0.9μm, 1μm, 1.1μm, 1.2μm, etc. The line width is one of the important factors affecting the trace impedance. When other factors (such as trace material and length) remain unchanged, the wider the line width, the smaller the impedance; the narrower the line width, the greater the impedance. By controlling the line width of the first electrode line and the line width of the second electrode line, the total impedance of the trace unit formed by the two can be controlled. Of course, the total impedance of the trace unit formed by the two can also be controlled by controlling parameters such as the materials and line lengths of the first electrode line and the second electrode line.

[0072] Since the first electrode line is generally arranged on the same layer as traces such as data lines, if the line width of the first electrode line is increased, it will affect the traces such as data lines on the same layer; while the second electrode line is arranged on a different layer from the traces such as data lines, increasing the line width of the second electrode line will not affect the traces such as data lines. Therefore, a structure in which the line width of the first electrode line is less than the line width of the second electrode line is generally selected. For example, the line width of the first electrode line can be 3.1μm, and the line width of the second electrode line can be 4.1μm. Of course, it should be noted that the line width of the first electrode line and the line width of the second electrode line can also be the same; or, the line width of the first electrode line is greater than the line width of the second electrode line, which can be selected according to the actual situation.

[0073] The overlapping area of the second electrode line and the first electrode line in the direction perpendicular to the substrate is not limited. The larger the overlapping area of the two, the more the aperture ratio can be further improved. In the overlapping area of the first electrode line and the second electrode line in the direction perpendicular to the substrate, the boundary of the positive projection of the first electrode line on the substrate can be located within the boundary of the positive projection of the second electrode line on the substrate; or, in the overlapping area of the first electrode line and the second electrode line in the direction perpendicular to the substrate, the boundary of the positive projection of the second electrode line on the substrate can be located within the boundary of the positive projection of the first electrode line on the substrate; or, in the overlapping area of the first electrode line and the second electrode line in the direction perpendicular to the substrate, the boundary of the positive projection of the first electrode line on the substrate coincides with the boundary of the positive projection of the second electrode line on the substrate; or, in the overlapping area of the first electrode line and the second electrode line in the direction perpendicular to the substrate, the boundary of the positive projection of the second electrode line on the substrate is tangent to the boundary of the positive projection of the first electrode line on the substrate, which is not limited here. Of course, it should be noted that the first electrode line and the second electrode line may not overlap at all in the direction perpendicular to the substrate.

[0074] The relative positional relationships between the above-mentioned first electrode line and the second electrode line and the first electrode are not limited. By way of example, refer to Figure 4a As shown, the orthographic projections of the first electrode line 21 and the second electrode line 22 on the substrate are respectively arranged between the orthographic projections of two adjacent rows of first electrodes 11 arranged along the second direction ( Figure 4a the OB direction in Figure 4a ) on the substrate, and the first direction and the second direction intersect; the first direction can be, for example, Figure 4a the OA direction as shown, and at this time, the second direction can be, for example, Figure 4a the OB direction as shown. Or, the first direction can also be, for example, Figure 4a the OB direction as shown, and at this time, the second direction can be, for example, Figures 1 - 4a the OA direction as shown. Here, there is no limitation.

[0075] For a clearer illustration of Figure 4a the structures of the first parallel portion and the second parallel portion in Figure 4b , refer to Figure 4b . The second parallel portion 220 shown in FIG. A in Figure 4b can be formed first, and then the data line 32 and the first parallel portion 210 shown in FIG. B in Figure 4b are formed. Finally, the structure shown in FIG. C in

[0076] is formed, and the second parallel portion 220 and the first parallel portion 210 partially overlap in a direction perpendicular to the substrate.

[0077] The specific number of the above-mentioned wiring units is not limited. By way of example, the number of the wiring units can be the same as the number of sub-pixels arranged along the second direction, so as to form a 1P3T structure; or, the number of the wiring units can be two-thirds of the total number of sub-pixels arranged along the second direction, so as to form a 1P2T structure; or, the number of the wiring units can be one-third of the total number of sub-pixels arranged along the second direction, so as to form a 1P1T structure. The 1P3T structure means that three electrode lines are provided for one pixel unit; similarly, the 1P1T structure means that one electrode line is provided for one pixel unit, and the 1P2T structure means that two electrode lines are provided for one pixel unit. Generally, one pixel unit includes three sub-pixels (R sub-pixel, G sub-pixel, and B sub-pixel).

[0078] In the above-mentioned wiring unit, at least one of the first electrode line and the second electrode line is electrically connected to a first electrode included in one of the plurality of touch units arranged in the first direction, which includes: in the wiring unit, the first electrode line is electrically connected to the first electrode included in one of the plurality of touch units arranged in the first direction; or, in the wiring unit, the second electrode line is electrically connected to the first electrode included in one of the plurality of touch units arranged in the first direction; or, both the first electrode line and the second electrode line are electrically connected to the first electrode included in one of the plurality of touch units arranged in the first direction.

[0079] The above-mentioned array substrate can be applied to liquid crystal touch display panels such as TN (Twisted Nematic) type, VA (Vertical Alignment) type, IPS (In-Plane Switching) type, ADS (Advanced Super Dimension Switch) type or HADS type, etc., which are not limited here.

[0080] Compared with the ADS type liquid crystal touch display screen, in order to further improve the aperture ratio, the HADS type liquid crystal touch display screen came into being. The biggest difference between the ADS type and the HADS type lies in the different electrode positions of the common electrode (Com electrode) and the pixel electrode (Pixel electrode). If the array substrate is applied to the ADS type touch display screen, then the first electrode can be called the common electrode; if the array substrate is applied to the HADS type liquid crystal touch display screen, then the first electrode can be called the pixel electrode.

[0081] The size of the above-mentioned array substrate is not limited, and it can be applied to large-sized display devices such as computers and televisions, or it can also be applied to small-sized display devices such as mobile phones and tablet computers.

[0082] The following takes Figure 1 the shown structure as an example to illustrate the touch principle. Referring to Figure 1 as shown, each touch unit 1 can be electrically connected to the driving chip 7 through the wiring unit 2. The driving chip may include a TDDI-IC (Touch and Display Driver Integrated Circuit). The TDDI-IC can provide a data signal to the wiring unit during the display stage and receive the touch signal transmitted by the wiring unit during the touch stage, and then locate the coordinates where the touch occurs through the Touch MCU (Touch Microprocessor) and perform corresponding processing actions according to the touch instructions issued by the user. Among them, the TDDI-IC (Touch and Display Driver Integrated Circuit) can be arranged on the FPC (Flexible Printed Circuit) 8.

[0083] In the related art, the touch unit can be electrically connected to the driving chip through TX lines. To ensure touch performance, the line width of the TX lines needs to be greater than or equal to 5.5 μm to meet the resistance requirements of the TX lines. To reduce costs, the TX lines are generally arranged on the same layer as the data lines, which will inevitably reduce the aperture ratio of the pixels, thereby affecting the transmittance of the product and reducing the display effect. At the same time, the more the number of TX lines is set, the greater the impact on the aperture ratio. Therefore, in products using a 1P3T structure, it is very important to improve the aperture ratio.

[0084] In this application, along the direction perpendicular to the substrate, at least partially overlapping first electrode lines and second electrode lines form a wiring unit; the wiring unit is electrically connected to a first electrode included in one of a plurality of touch units arranged in a first direction. In the wiring unit, a first parallel portion of the first electrode line and a second parallel portion of the second electrode line are arranged in parallel, so that the resistance becomes smaller after the first electrode line and the second electrode line are connected in parallel; then, compared with the TX lines in the related art, in this application, the line width of the first electrode line can be reduced as much as possible (for example, reduced to less than 3 μm) while meeting the wiring resistance requirements, and at the same time, the line width of the second electrode line can also be reduced to less than 5.5 μm, thereby reducing the impact on the corresponding aperture ratio, and further improving the transmittance of the product and enhancing the display effect.

[0085] Optionally, to improve touch performance, in combination with Figure 4a , Figures 10 - 12 as shown, the first electrode line 21 includes a plurality of continuously arranged first parallel portions 210, and the second electrode line 22 includes a plurality of intermittently arranged second parallel portions 220; referring to Figure 4a as shown, the first parallel portion 210 and the second parallel portion 220 are arranged between at least two sub-pixels 4 arranged in a second direction (OB direction).

[0086] In the above array substrate, the number of the first parallel portion and the second parallel portion provided is not limited and can be determined according to the specific structure. By way of example, if an array substrate for forming 1P3T is used, then referring to Figure 4a as shown, each sub-pixel 4 in each pixel unit corresponds to the first parallel portion 210 and the second parallel portion 220 being provided; if an array substrate for forming 1P2T is used, any two sub-pixels in each pixel unit correspond to the first parallel portion and the second parallel portion being provided; if an array substrate for forming 1P1T is used, any one sub-pixel in each pixel unit corresponds to the first parallel portion and the second parallel portion being provided.

[0087] Optionally, to facilitate the electrical connection between the wiring unit and the touch unit, referring to Figure 4a as shown, the touch unit further includes a plurality of connection electrodes 14.

[0088] A plurality of connection electrodes arranged in a first direction include a first connection electrode and a second connection electrode. The first electrode lines are electrically connected to the first connection electrode and the second connection electrode respectively, and referring to Figure 17 as shown, at least one of the first connection electrodes 141 is electrically connected to the corresponding first electrode 11; referring to Figure 16 as shown, the second connection electrode 142 is not electrically connected to the corresponding first electrode 11.

[0089] In the present application, one first electrode line is only electrically connected to the first electrode of one touch unit to prevent short circuits between different touch units; the above-mentioned first connection electrode is used to electrically connect the first electrode line and the corresponding first electrode. Therefore, at least one of the first connection electrodes is electrically connected to the corresponding first electrode; the above-mentioned second connection electrode is not used to electrically connect the first electrode line and the first electrode. Therefore, the second connection electrode is not electrically connected to the first electrode. Referring to Figure 18 as shown, in the same touch unit, Figure 18 the connection electrode 14 in the middle is connected to the first electrode 11, so that the first electrode line 21 in the middle is electrically connected to the first electrode 11 through the middle connection electrode 14; Figure 18 the two connection electrodes 14 on the left and right are respectively disconnected from the corresponding first electrodes 11, so as to ensure that the two first electrode lines 21 on the left and right cannot be electrically connected to the first electrode 11 through the middle connection electrode 14.

[0090] Optionally, referring to Figure 5 and Figures 12 - 15 as shown, in the wiring unit, the first end 221 of the second parallel portion 220 of the second electrode line is electrically connected to the corresponding connection electrode 14 and the first parallel portion 210 of the first electrode line respectively, and the second end 222 is electrically connected to another connection electrode 14.

[0091] In the wiring unit, two adjacent second parallel portions 220 arranged in the first direction (OA direction) are electrically connected through the connection electrode 14.

[0092] In the present application, by providing the connection electrode, the parallel connection of the first electrode line and the second electrode line in the wiring unit is realized, and the design is simple and the cost is low.

[0093] Optionally, in order to reduce the number of patterning times and thus reduce the cost, the connection electrode and the first electrode are arranged on the same layer; referring to Figure 17 as shown, the first connection electrode 141 is connected to the corresponding first electrode 11, referring to Figure 16 as shown, the second connection electrode 142 is disconnected from the corresponding first electrode 11.

[0094] The above same-layer setting means it is fabricated by a single lithography process. The single lithography process refers to the process of forming the required layer structure through one exposure. The single lithography process includes processes such as masking, exposure, development, etching, and stripping.

[0095] Optionally, as shown in Figure 4a 、 Figures 10 - 15 , the array substrate further includes a plurality of gate lines 31 arranged along the first direction (OA direction); the orthographic projection of the gate lines 31 on the substrate is disposed between the orthographic projections of two adjacent rows of first electrodes 11 arranged along the first direction (OA direction) on the substrate.

[0096] Among them, the second parallel portion 220 of the second electrode line is disposed between two adjacent gate lines 31 arranged along the first direction (OA direction); the second electrode line is provided on the same layer as the gate line and does not overlap with each other.

[0097] The above second electrode line and the gate line are provided on the same layer, which can reduce the number of lithography times, thereby reducing costs.

[0098] Optionally, as shown in reference to Figure 20 , the part of the gate line 31 located in the first region includes a continuously provided first part 311, an intermediate part 310, and a second part 312; the first region is the region where the sub-pixels are located, and the connection electrode 14 in the first region is disconnected from the first electrode 11 in the first region.

[0099] Among them, the connection electrode 14 in the first region covers the first part 311, the first electrode 11 in the first region covers the second part 312, and the intermediate part 310 is not covered by the connection electrode or the first electrode located in the first region.

[0100] As shown in reference to Figure 20 , the first region further includes a shielding electrode 15, the shielding electrode is provided on the same layer as the gate line and does not overlap with each other; the shielding electrode overlaps at least the disconnected part between the connection electrode and the first electrode in the first region in the direction perpendicular to the substrate.

[0101] Since the intermediate part of the above gate line is not covered by the connection electrode or the first electrode located in the first region, when the gate line is in the working state, as shown in reference to Figure 19 , an electric field will be generated between the intermediate part 310 of the gate line 31 and the surrounding first electrodes 11. When this substrate is applied to a liquid crystal touch panel, this electric field will cause the nearby liquid crystal to rotate, resulting in a light leakage phenomenon and reducing the display effect. In this application, as shown in reference to Figure 20 , by providing the shielding electrode 15, the electric field generated by the intermediate part 310 of the shielding gate line is shielded, thereby greatly reducing the light leakage range and further improving the transmittance of the product.

[0102] Optionally, in order to increase the area of the shielding electrode to enhance the shielding effect, refer to Figure 20 As shown, the shielding electrode 15 also partially overlaps with the first electrode 11 in the first region in a direction perpendicular to the substrate.

[0103] Optionally, in order to simplify the structure and facilitate implementation, refer to Figure 20 As shown, the shielding electrode 15 includes a strip-shaped electrode and is arranged parallel to the gate line 31.

[0104] In order to reduce the number of patterning steps and thus reduce costs, the shielding electrode and the gate line can be provided on the same layer.

[0105] In one or more embodiments, referring to Figure 4a 、 Figures 10 - 15 As shown, the array substrate further includes a plurality of data lines 32 arranged along the second direction (OB direction); the orthographic projection of the data line 32 on the substrate is provided between the orthographic projections of two adjacent rows of the first electrodes 11 arranged along the second direction (OB direction) on the substrate; wherein, the first electrode line and the data line are provided on the same layer and do not overlap with each other.

[0106] The above-mentioned first electrode line and the data line being provided on the same layer can reduce the number of patterning steps and further reduce costs.

[0107] Optionally, referring to Figure 4a 、 Figures 10 - 15 and Figure 22 , the sub-pixel further includes a transistor 16, and the transistor 16 includes a control electrode 160, a first electrode 161, and a second electrode 162; the control electrode 160 is connected to the gate line 31, and the first electrode 161 is connected to the data line 32.

[0108] The control electrode, the second electrode line, the gate line, and the shielding electrode are provided on the same layer; the first electrode, the second electrode, the data line, and the first electrode line are provided on the same layer, so as to minimize the number of patterning steps and further reduce costs.

[0109] The above-mentioned transistor includes a gate, a source, and a drain. One of the source and the drain is referred to as the first electrode, and the other is referred to as the second electrode. The gate is the control electrode. The transistor can be a P-type thin film transistor or an N-type thin film transistor, which is not limited here. Of course, the transistor can also include an active layer.

[0110] According to the positional relationship of the electrodes, transistors can be divided into two categories: one is that the gate is located below the source and the drain, and this type is called a bottom-gate transistor; the other is that the gate is located above the source and the drain, and this type is called a top-gate transistor. The transistors in this application can be bottom-gate type or top-gate type. When applying this array substrate to a liquid crystal touch screen, since liquid crystals do not emit light by themselves, the liquid crystal touch screen also includes a backlight module. The light emitted by the backlight module passes through the array substrate and shines on the liquid crystal. By adjusting the deflection angle of the liquid crystal, the amount of light emitted is controlled, and finally the display of different images is achieved. Since the active layer of the transistor is easily affected by light, if a bottom-gate transistor is used, the gate can block the light shining on the active layer, thus playing a certain protective role for the active layer and improving the performance of the transistor.

[0111] Optionally, in order to prevent light from affecting the performance of the transistor, the transistor includes a bottom-gate transistor; combined Figure 4a 、 Figures 10 - 15 and Figure 22 , the transistor further includes an active layer 163; referring to Figure 22 as shown, the sub-pixel further includes a gate insulating layer 17, an interlayer dielectric layer 19, and a planarization layer 18.

[0112] The gate insulating layer covers the control electrode, the second electrode line, the gate line, and the shielding electrode; referring to Figure 22 as shown, the active layer 163 is disposed on a side of the gate insulating layer 17 away from the substrate 100 and overlaps with the control electrode 160 in a direction perpendicular to the substrate; the interlayer dielectric layer 19 covers the active layer 163; the first electrode 161 and the second electrode 162 are disposed on a side of the interlayer dielectric layer 19 away from the substrate 100 and are electrically connected to the active layer 163 respectively; the planarization layer 18 covers at least the first electrode 161, the second electrode 162, the data line ( Figure 22 not shown) and the first electrode line ( Figure 22 not shown); the connection electrode and the first electrode are disposed on a side of the planarization layer away from the substrate.

[0113] The material of the above-mentioned active layer can be single-crystalline silicon; or amorphous silicon; or polycrystalline silicon, for example: LTPS (Low Temperature Poly-silicon); or an oxide semiconductor material, for example: IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), etc.

[0114] Optionally, in order to simplify the structure and facilitate implementation, combined Figure 5 and Figure 6As shown, the sub-pixel further includes a first via 41; the first via is configured to penetrate through the gate insulating layer and the planarization layer to expose the second end of the second parallel portion of the second electrode line; the connection electrode is overlapped with the second end of the second parallel portion through the first via.

[0115] Further optionally, in combination with Figure 5 and 6 As shown, the opening distance L of the first via 41 in the first direction (OA direction) is greater than the line width W of the exposed portion 223 of the second end 222 of the second parallel portion, and the connection electrode 14 covers the top surface a1 and the side surface a3 of the exposed portion 223 of the second end of the second parallel portion.

[0116] Referring to Figure 6 As shown, the exposed portion 223 of the second end of the second parallel portion described above includes an opposite top surface a1 and a bottom surface a2, and the top surface a1 is farther from the substrate 100 than the bottom surface a2.

[0117] The overlapping manner of the connection electrode and the second end of the second parallel portion belongs to a semi-overlapping manner. The connection electrode is in direct contact with both the top surface and the side surface of the exposed portion of the second end of the second parallel portion. Then, while ensuring a good electrical connection effect, the line width of the second end of the second parallel portion and the area of the connection electrode can be reduced, thereby further improving the aperture ratio.

[0118] Optionally, in order to simplify the structure and facilitate implementation, in combination with Figure 5 and Figure 7 As shown, the sub-pixel further includes a second via 42; the second via 42 includes a connected first sub-via 421 and a second sub-via 422. The first sub-via is configured to penetrate through the gate insulating layer and the planarization layer to expose a part of the first end of the second parallel portion of the second electrode line; the second sub-via is configured to penetrate through the planarization layer to expose a part of the first parallel portion of the first electrode line; the connection electrode 14 is overlapped with the first end 221 of the second parallel portion through the first sub-via 421 and overlapped with the first parallel portion 210 through the second sub-via 422.

[0119] Further optionally, in combination with Figure 5 and Figures 7 - 9 , the orthographic projection of the second via 42 on the substrate overlaps with the orthographic projection of the exposed portion 224 of the first end 221 of the second parallel portion on the substrate and the orthographic projection of the exposed portion 211 of the first parallel portion on the substrate respectively; referring to Figure 8 and Figure 9 As shown, the connection electrode 14 covers the top surface c1 and the side surface c3 of the exposed portion 224 of the first end 221 of the second parallel portion, and the top surface b1 and the side surface b3 of the exposed portion 211 of the first parallel portion 210.

[0120] Referring to Figure 9As shown, the exposed portion 224 of the first end 221 of the second parallel portion includes opposite top surface c1 and bottom surface c2, and the top surface c1 is farther from the substrate 100 than the bottom surface c2. Similarly, referring to Figure 8 As shown, the exposed portion 211 of the first parallel portion 210 includes opposite top surface b1 and bottom surface b2, and the top surface b1 is farther from the substrate than the bottom surface b2.

[0121] The overlapping manner of the connection electrode and the first end of the second parallel portion belongs to a semi-overlapping manner. The connection electrode is in direct contact with both the top surface and the side surface of the exposed portion of the first end of the second parallel portion. Thus, while ensuring a good electrical connection effect, the line width of the first end of the second parallel portion and the area of the connection electrode can be reduced, thereby further improving the aperture ratio.

[0122] Similarly, the overlapping manner of the connection electrode and the first parallel portion belongs to a semi-overlapping manner. The connection electrode is in direct contact with both the top surface and the side surface of the exposed portion of the first parallel portion. Thus, while ensuring a good electrical connection effect, the line width of the first end of the second parallel portion and the area of the connection electrode can be reduced, thereby further improving the aperture ratio.

[0123] In one or more embodiments, in combination with Figures 12 - 15 , the sub-pixel further includes a second electrode 12; the second electrode 12 is electrically connected to the corresponding second pole 162. The second electrode is disposed between the gate insulating layer and the planarization layer, and the orthographic projection of the second electrode 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode 11 on the substrate; the second electrode is configured to form an electric field with the first electrode during the display stage.

[0124] If the above array substrate is applied to an ADS type touch display screen, the first electrode can be referred to as a common electrode, and the second electrode can be referred to as a pixel electrode; if the array substrate is applied to an HADS type liquid crystal touch display screen, the first electrode can be referred to as a pixel electrode, and the second electrode can be referred to as a common electrode.

[0125] During the display stage of the above array substrate, the voltage of the first electrode can be controlled by a transistor, and further the magnitude of the electric field between the first electrode and the second electrode can be controlled. When the above array substrate is applied to a liquid crystal touch display screen, the electric field generated by the first electrode and the second electrode can cause the liquid crystal to deflect. By changing the magnitude of the electric field, the deflection angle of the liquid crystal is further changed, thereby controlling the amount of light emitted, and finally realizing the display of different pictures.

[0126] Optionally, referring to Figure 12 As shown, the second electrode 12 includes a plate-shaped electrode. Referring to Figure 15 As shown, the first electrode 11 includes a plurality of strip-shaped electrodes. In this way, a multi-dimensional electric field can be formed between the first electrode and the second electrode, which is more conducive to controlling the deflection of the liquid crystal.

[0127] Reference Figure 15 As shown, the first electrode 11 may include a plurality of parallel strip electrodes with slits between adjacent strip electrodes, and the same ends of all strip electrodes are connected together.

[0128] Of course, the above array substrate may further include other structures; only the structures related to the inventive points are introduced here, and the remaining structures can be obtained with reference to the related art and will not be elaborated here.

[0129] An embodiment of the present application further provides a display panel including the above array substrate.

[0130] The display panel may be a liquid crystal touch display panel such as TN (Twisted Nematic), VA (Vertical Alignment), IPS (In-Plane Switching), ADS (Advanced Super Dimension Switch), or HADS type, or may be any product or component with display and touch functions such as a TV, digital camera, mobile phone, tablet computer, etc. including these display panels.

[0131] Optionally, as shown in the reference Figure 22 the display panel further includes a color filter substrate 102, and the color filter substrate 102 is disposed opposite to the array substrate 101; wherein, the color filter substrate 102 includes a black matrix 104; and the array substrate 101 includes a substrate 100 and a shielding electrode 15.

[0132] Combined with Figure 20 and Figure 23 as shown, the first orthographic projection N of the shielding electrode 15 on the substrate 100 is located within the second orthographic projection T of the black matrix 104 on the substrate 100, and a partial boundary of the first orthographic projection N coincides with a partial boundary of the second orthographic projection T.

[0133] Figure 20 In, the black dotted lines BM1 and BM2 are the shielding boundaries corresponding to the black matrix, and the part between the black dotted lines BM1 and BM2 is shielded by the black matrix.

[0134] Since the shielding electrode can shield the electric field generated when the gate line transmits signals (for example: gate signals), thereby greatly reducing the light leakage range, therefore, the black matrix does not need to be set with an additional larger area to avoid light leakage, thereby further improving the transmittance and enhancing the display effect. A partial boundary of the first orthographic projection of the above shielding electrode on the substrate coincides with a partial boundary of the second orthographic projection of the black matrix on the substrate, that is, along the direction perpendicular to the substrate of the array substrate, a part of the black matrix is set flush with the shielding electrode.

[0135] Of course, the above display panel may further include, for example, Figure 23 a liquid crystal 103 located between the color filter substrate 102 and the array substrate 101, a backlight module ( Figure 23 not shown) located on the side of the array substrate away from the color filter substrate, etc.; the color filter substrate may further include a color filter layer, a polarizing layer, etc. Here, only the structures related to the inventive points are introduced, and the remaining structures can be obtained by referring to the related art and will not be elaborated here.

[0136] An embodiment of the present application further provides a method for manufacturing an array substrate. The structure of the array substrate can be referred to Figure 15 as shown, and the method includes:

[0137] S01. Form a gate line 31, a second electrode line (including a second parallel portion 220), a control electrode 160, and a shielding electrode 15 as Figure 10 shown on a substrate.

[0138] The material of the substrate is not limited. Exemplarily, it can be a rigid material, such as: glass.

[0139] Exemplarily, a single patterning process can be used to form the gate line, the second electrode line, the control electrode, and the shielding electrode, thereby reducing the number of patterning processes and lowering the production cost.

[0140] S02. Form a gate insulating layer and an active layer 163 as Figure 11 shown; wherein, the gate insulating layer covers the control electrode, the second electrode line, the gate line, and the shielding electrode; the active layer is disposed on the side of the gate insulating layer away from the substrate.

[0141] The material of the gate insulating layer can be silicon nitride or silicon oxide; the material of the active layer can be single-crystalline silicon; or amorphous silicon; or polycrystalline silicon, such as: LTPS (Low Temperature Poly-silicon); or an oxide semiconductor material, such as: IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), IZO (Indium Zinc Oxide), etc.

[0142] S03. Sequentially form an interlayer dielectric layer covering the active layer and a second electrode 12 as Figure 12 shown; the second electrode 12 covers a part of the shielding electrode 15.

[0143] The material of the second electrode may include a transparent metal oxide, such as: ITO (Indium Tin Oxide).

[0144] S04. Form asFigure 13 The first pole 161, the second pole 162, the data line 32, and the first electrode line (including the first parallel portion 210) as shown.

[0145] Exemplarily, the first pole, the second pole, the data line, and the first electrode line can be formed by a single patterning process, thereby reducing the number of patterning processes and lowering the production cost.

[0146] S05. Form a planarization layer; wherein, the planarization layer covers at least the first pole, the second pole, the data line, and the first electrode line.

[0147] The material of the planarization layer can be an organic material such as resin.

[0148] S06. Form a first via hole 41 and a second via hole 42 as shown in Figure 14 the figure.

[0149] S07. Form a first electrode 11 and a connection electrode 14 as shown in Figure 15 the figure; wherein, the connection electrode is overlapped with the second end of the second parallel portion through the first via hole, and at the same time, the connection electrode is overlapped with the first end of the second parallel portion through the first sub-via hole of the second via hole and overlapped with the first parallel portion through the second sub-via hole of the second via hole.

[0150] The materials of the above-mentioned first electrode and connection electrode can include a transparent metal oxide, for example: ITO (Indium Tin Oxide).

[0151] Exemplarily, the first electrode and the connection electrode can be formed by a single patterning process, thereby reducing the number of patterning processes and lowering the production cost.

[0152] In the array substrate formed by the above method, referring to Figure 21 Figure b in, the effective area of the sub-pixel is 6855 μm2; while for the sub-pixel with the original design as shown in Figure 21 Figure a in, its effective area is 6562.5 μm2; without increasing the processes and cost, the transmittance is increased by 4%.

[0153] In the above preparation method, the relevant descriptions of the structures involved can refer to the foregoing embodiments and will not be elaborated here.

[0154] As used herein, "one embodiment", "an embodiment", or "one or more embodiments" means that the specific features, structures, or characteristics described in connection with the embodiments are included in at least one embodiment of the present application. In addition, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0155] In the specification provided herein, a large number of specific details are set forth. However, it will be understood that embodiments of the present application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, wherein, comprising: a substrate; a plurality of touch units arranged in an array on the substrate, the touch units comprising a plurality of sub-pixels arranged in an array; the sub-pixels comprising a first electrode; a plurality of trace units, the trace units comprising a first electrode line and a second electrode line that overlap at least partially in a direction perpendicular to the substrate; the first electrode line and the second electrode line are both arranged in a first direction, and the line width of the first electrode line is less than the line width of the second electrode line; the first electrode line includes at least one first parallel portion, and the second electrode line includes at least one second parallel portion; in the trace unit, the first parallel portion of the first electrode line and the second parallel portion of the second electrode line are arranged in parallel, and at least one of the first electrode line and the second electrode line is electrically connected to the first electrode included in one of the plurality of touch units arranged in the first direction; the touch unit further comprises a plurality of connection electrodes; the plurality of connection electrodes arranged in the first direction include a first connection electrode and a second connection electrode, the first electrode line is electrically connected to the first connection electrode and the second connection electrode respectively, and at least one of the first connection electrodes is electrically connected to the corresponding first electrode, and the second connection electrode is not electrically connected to the first electrode; the connection electrodes and the first electrodes are arranged in the same layer; the array substrate further comprises a plurality of gate lines arranged in the first direction; the orthographic projection of the gate lines on the substrate is arranged between the orthographic projections of two adjacent rows of the first electrodes arranged in the first direction on the substrate; wherein, the second parallel portion of the second electrode line is arranged between two adjacent gate lines arranged in the first direction; the second electrode line and the gate lines are arranged in the same layer and do not overlap with each other; the portion of the gate line located in the first region includes a continuously arranged first portion, an intermediate portion, and a second portion; the first region is the region where the sub-pixels are located, and the connection electrodes in the first region are disconnected from the first electrodes in the first region; wherein, the connection electrodes in the first region cover the first portion, the first electrodes in the first region cover the second portion, and the intermediate portion is not covered by the connection electrodes or the first electrodes located in the first region; the first region further comprises a shielding electrode, the shielding electrode and the gate lines are arranged in the same layer and do not overlap with each other; the shielding electrode overlaps at least with the disconnected portion between the connection electrodes and the first electrodes in the first region in a direction perpendicular to the substrate.

2. The array substrate according to claim 1, wherein, the first electrode line includes a plurality of continuously arranged first parallel portions, and the second electrode line includes a plurality of intermittently arranged second parallel portions; the first parallel portion and the second parallel portion are arranged between at least two of the sub-pixels arranged in a second direction.

3. The array substrate according to claim 1, wherein, In the wiring unit, the first ends of the second parallel portions of the second electrode lines are respectively electrically connected to the corresponding connection electrodes and the first parallel portions of the first electrode lines, and the second ends are electrically connected to the other connection electrodes; In the wiring unit, two adjacent second parallel portions arranged along the first direction are electrically connected through the connection electrode.

4. The array substrate according to claim 1, wherein, The shielding electrode also partially overlaps with the first electrode in the first region in a direction perpendicular to the substrate.

5. The array substrate according to claim 4, wherein, The shielding electrode includes a strip-shaped electrode and is arranged parallel to the gate line.

6. The array substrate according to claim 2, wherein, The array substrate further includes a plurality of data lines arranged along the second direction; the orthographic projection of the data lines on the substrate is disposed between the orthographic projections of two adjacent rows of the first electrodes arranged along the second direction on the substrate; wherein the first electrode line and the data line are disposed in the same layer and do not overlap each other.

7. The array substrate according to claim 6, wherein, The sub-pixel further includes a transistor, and the transistor includes a control electrode, a first electrode, and a second electrode; the control electrode is connected to the gate line, and the first electrode is connected to the data line; The control electrode, the second electrode line, the gate line, and the shielding electrode are disposed in the same layer; The first electrode, the second electrode, the data line, and the first electrode line are disposed in the same layer.

8. The array substrate according to claim 7, wherein, The transistor includes a bottom-gate transistor; the transistor further includes an active layer; the sub-pixel further includes a gate insulating layer, an interlayer dielectric layer, and a planarization layer; The gate insulating layer covers the control electrode, the second electrode line, the gate line, and the shielding electrode; the active layer is disposed on a side of the gate insulating layer away from the substrate and overlaps with the control electrode in a direction perpendicular to the substrate; the interlayer dielectric layer covers the active layer; the first electrode and the second electrode are disposed on a side of the interlayer dielectric layer away from the substrate and are respectively electrically connected to the active layer; The planarization layer covers at least the first electrode, the second electrode, the data line, and the first electrode line; the connection electrode and the first electrode are disposed on a side of the planarization layer away from the substrate.

9. The array substrate according to claim 8, wherein, The sub-pixel further includes a first via hole; The first via hole is configured to penetrate through the gate insulating layer and the planarization layer to expose the second end of the second parallel portion of the second electrode line; the connection electrode is overlapped with the second end of the second parallel portion through the first via hole.

10. The array substrate according to claim 9, wherein, The opening distance of the first via hole along the first direction is greater than the line width of the exposed portion of the second end of the second parallel portion, and the connection electrode covers the top surface and the side surface of the exposed portion of the second end of the second parallel portion.

11. The array substrate according to claim 8, wherein, The sub-pixel further includes a second via hole; The second via hole includes a first sub-hole and a second sub-hole connected to each other. The first sub-hole is configured to penetrate through the gate insulating layer and the planarization layer to expose a part of the first end of the second parallel portion of the second electrode line; the second sub-hole is configured to penetrate through the planarization layer to expose a part of the first parallel portion of the first electrode line. The connecting electrode is overlapped with the first end of the second parallel portion through the first sub-hole and overlapped with the first parallel portion through the second sub-hole.

12. The array substrate according to claim 11, wherein, The orthographic projection of the second via hole on the substrate overlaps with the orthographic projection of the exposed portion of the first end of the second parallel portion on the substrate and the orthographic projection of the exposed portion of the first parallel portion on the substrate respectively; The connecting electrode covers the top surface and the side surface of the exposed portion of the first end of the second parallel portion and the top surface and the side surface of the exposed portion of the first parallel portion.

13. A display panel, wherein, It includes the array substrate according to any one of claims 1-12.

14. The display panel according to claim 13, wherein, The display panel further includes a color filter substrate, and the color filter substrate is disposed opposite to the array substrate; wherein, the color filter substrate includes a black matrix; the array substrate includes a substrate and a shielding electrode; the first orthographic projection of the shielding electrode on the substrate is located inside the second orthographic projection of the black matrix on the substrate, and a part of the boundary of the first orthographic projection coincides with a part of the boundary of the second orthographic projection.

Images