A method for improving the crystal quality of large-size thick-film silicon epitaxial wafer

Abstract

This invention relates to a method for improving the crystal quality of large-size thick-film silicon epitaxial wafers. By comprehensively designing parameters such as the radial temperature gradient difference of the silicon substrate placement area, the silicon epitaxial layer growth temperature, the evacuation time before silicon epitaxial layer growth, the silicon epitaxial layer growth rate, the flatness of the graphite substrate, and the rotation speed of the graphite substrate during silicon epitaxial layer growth, the crystal quality of large-size thick-film silicon epitaxial wafers is improved with simple process and batch reproducibility. It avoids problems such as edge chipping, cracking, and fragmentation of silicon epitaxial wafers. It can be applied to the industrial mass production of large-size thick-film silicon epitaxial wafers with diameters of 150~200mm and silicon epitaxial layer thicknesses greater than 100μm.

Description

Technical Field

[0001] This invention relates to the field of semiconductor silicon epitaxial wafer fabrication technology, and more particularly to a method for improving the crystal quality of large-size thick-film silicon epitaxial wafers. Background Technology

[0002] Silicon epitaxial wafers are formed by using CVD (CVD) to create a silicon epitaxial layer on the polished surface of a silicon substrate. The process temperature during silicon epitaxial layer growth is typically above 1050°C. The final doping type, resistivity, thickness, uniformity, and other parameters must meet design and usage requirements. As a key basic material used in the manufacture of various semiconductor discrete devices, photodetectors, and integrated circuits, it directly determines the performance of these devices. With the emergence of new technologies such as artificial intelligence, the Internet of Things, and electric vehicles in recent years, the end applications of silicon epitaxial wafers have been continuously expanding, leading to a rapid increase in demand and necessitating large-scale production capabilities. Today, widely used power electronic high-voltage devices, such as fast recovery diodes, require operating voltages exceeding 1000V, correspondingly requiring silicon epitaxial layer thicknesses of over 100μm, known as thick-film silicon epitaxial wafers. Since silicon epitaxial layers can be considered as a series of extremely thin films stacked together, the continuous growth time for silicon epitaxial layers at temperatures above 1050°C generally exceeds 40 minutes. Including heating, cooling, and pretreatment processes, the total thermal processing time exceeds 1.5 hours, which is 2-3 times longer than the thermal processing time for thin-film silicon epitaxial layers. This significantly increases the difficulty of controlling key performance parameters such as thickness uniformity and resistivity uniformity. Furthermore, to meet industrial production efficiency requirements, thick-film silicon epitaxial wafers (greater than 50 μm) need to have faster growth rates than medium-thickness silicon epitaxial wafers (20-50 μm) and thin-film silicon epitaxial wafers (less than 20 μm). Typically, the industry uses a growth rate of 1.0-1.5 μm / min for thin-film silicon epitaxial wafers and 1.5-1.8 μm / min for medium-thickness silicon epitaxial wafers. While the growth rate of thick-film silicon epitaxial wafers needs to exceed 1.8 μm / min to ensure sufficient production efficiency, this also exposes them to greater mechanical and thermal stress, making them prone to warping and bending deformation. This is especially true for growing 100 μm thick silicon epitaxial wafers, where the growth process is longer and the risk of warping and bending deformation is greater. Once warping and bending reach a certain threshold, it can easily lead to edge chipping, cracking, or even fragmentation of the thick-film silicon epitaxial wafer after growth and during device fabrication, resulting in losses in silicon epitaxial wafer production. Statistics show that crystal quality issues can cause product qualification rate losses of up to 7%, resulting in a product qualification rate that has long hovered below 92%. Moreover, the long-term low growth efficiency of the production line due to equipment cleaning of fragments seriously affects production capacity and delays product order delivery. In addition, cracking problems during cleaning and primary oxidation processes at the user end of power electronic devices will cause even greater losses such as production line shutdowns and equipment cleaning and maintenance to remove fragments, leading to order cancellations and huge claims.

[0003] Growing thick silicon epitaxial wafers with a thickness of 100μm requires the use of a flat-panel multi-wafer silicon epitaxial furnace. Each furnace can grow 8 150mm silicon epitaxial wafers and 5 200mm silicon epitaxial wafers simultaneously, achieving good crystal quality for large-size thick silicon epitaxial wafers with diameters of 150~200mm and silicon epitaxial layer thicknesses of over 100μm. Controlling key performance parameters of silicon epitaxial layers, such as edge chipping, fragmentation, and cracking, while simultaneously ensuring thickness uniformity, has become a technical challenge in the industry.

[0004] Traditional processing methods include those disclosed in Chinese patents ZL 201410002107.X and ZL 201310240216.0. ZL 201410002107.X reduces warpage by adding a buffer layer during the early stages of silicon epitaxial growth, thereby reducing stress during the growth process and preventing excessive warpage of large-size silicon epitaxial wafers that could lead to fragmentation or cracking. However, the introduction of the buffer layer makes the overall growth process of the silicon epitaxial layer more complex. Chinese patent ZL 201310240216.0 employs a two-step substrate heating method. In the first step, the temperature is raised from room temperature to 950-1000°C at a rate of 80°C / min to 120°C / min. In the second step, the temperature is raised to the silicon epitaxial layer growth temperature at a rate of 10°C / min to 20°C / min. This method reduces the deformation of the silicon epitaxial wafer caused by thermal stress by significantly extending the heating time. However, because the two-step heating significantly extends the total thermal process time, it will not only affect the growth efficiency, but also cause the substrate to be heated for a longer time. Impurities contained in the heavily doped substrate will continue to volatilize, which is not conducive to the control of the resistivity uniformity of the silicon epitaxial layer.

[0005] Therefore, there is an urgent need to design a new preparation method for thick silicon epitaxial wafers with a diameter of 150~200 mm and a silicon epitaxial layer thickness of more than 100 μm, to avoid problems such as edge chipping, fragmentation, and cracking during the growth of silicon epitaxial wafers, and to ensure good parameters such as thickness uniformity and resistivity uniformity. The process should be simple, stable, and suitable for the requirements of continuous industrial production. Summary of the Invention

[0006] Given the shortcomings of existing growth techniques for large-size thick-film silicon epitaxial wafers with diameters of 150-200 mm and epitaxial layer thicknesses exceeding 100 μm, which are prone to edge chipping, fragmentation, and cracking during growth, the present invention aims to provide a method for improving the crystal quality of large-size thick-film silicon epitaxial wafers. This method primarily employs a comprehensive design of the radial temperature gradient in the silicon substrate area, the silicon epitaxial layer growth temperature, and the growth rate. Combined with sufficient thermal stabilization time and venting time of the growth gas source before silicon epitaxial layer growth, it provides steady-state reaction conditions for silicon epitaxial layer growth. By optimizing the flatness and rotation speed of the graphite substrate, the method improves the positional consistency of the silicon epitaxial wafer within the graphite substrate pits, reducing the thickness of wafers with diameters of 150-200 mm. Large-size silicon epitaxial wafers (mm in diameter) face the risk of severe warping and bending deformation due to excessive mechanical and thermal stress during growth. This method effectively avoids edge chipping, fragmentation, and cracking problems after silicon epitaxial layer growth. Under the premise of simple process, good stability, strong operability, and good growth efficiency, it effectively improves the crystal quality of large-size thick-film silicon epitaxial wafers.

[0007] The technical problem to be solved by the present invention is achieved through the following steps: A method for preparing large-size thick-film silicon epitaxial wafers with improved crystal quality, comprising the following steps:

[0008] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it, and adjust the radial temperature field of the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is 2~5℃.

[0009] Step 2: Heat the reaction chamber to 1110~1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and the graphite substrate inside to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 34~36 L / min, and the etching time is set to 10~12 min.

[0010] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 140~160 L / min and the trichlorosilane flow rate is set to 10~16 L / min. A polycrystalline silicon coating layer with a thickness of 1~2 μm is deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60~120 sec.

[0011] Step 4: Cool the reaction chamber to 300~350℃, keep the flatness of the graphite base at 0.3~0.5mm, and place the silicon substrate in the center of the pit in the graphite base;

[0012] Step 5: The reaction chamber is heated to 1050~1060℃ for 12~16 min, and then held at this temperature for 1~2 min. Hydrogen carries gaseous trichlorosilane into the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 140~160 L / min, the trichlorosilane flow rate is set to 10~13 L / min, the ramp-up time is set to 30~60 sec, and the venting time in the venting pipe is set to 30~60 sec. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 3~4 r / min, and the growth rate of the silicon epitaxial layer is set to 1.8~2.0 μm / min.

[0013] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 300~350℃ for 15~20 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 50~60℃, it is removed from the wafer carrier basket.

[0014] In step 1, the distance between the induction heating coil and the horizontal disc-shaped graphite base above it is set to 15~30 mm.

[0015] In step 1, the silicon substrate is placed centered in the pit of the graphite base. The edge chamfer type of the silicon substrate is set to R-type, the chamfer angle is set to 22°, and the chamfer width is set to 300~400 μm.

[0016] The silicon substrate has a crystal orientation of <100> ±0.5°, diameter 150~200mm, resistivity 0.002~0.005Ω·cm, oxygen content 14~18ppma, front surface polished, back surface successively coated with a polycrystalline silicon layer with a thickness of 800~1000nm and a silicon dioxide layer with a thickness of 450~550nm.

[0017] The target growth thickness of the silicon epitaxial layer is greater than 100 μm.

[0018] The heating power of the reaction chamber of the silicon epitaxial furnace during the silicon epitaxial layer growth process is set to 80~84KW, and the pressure of the reaction chamber is maintained at -1.3~-1.7 mbar.

[0019] The advantages of this invention compared to existing technologies are as follows: By comprehensively designing parameters such as the radial temperature gradient difference of the silicon substrate placement area used for silicon epitaxial wafers, the silicon epitaxial layer growth temperature, the evacuation time before silicon epitaxial layer growth, the silicon epitaxial layer growth rate, the flatness of the graphite substrate, and the rotation speed of the graphite substrate during silicon epitaxial layer growth, this invention first avoids common crystal quality problems such as edge chipping, cracking, and fragmentation of silicon epitaxial wafers, as well as the resulting production line downtime maintenance such as fragment cleaning and machine debugging. With a simple process and the ability to be repeated in batches, this invention significantly improves the production capacity of wafers with diameters of 150-200 mm. The crystal quality of large-size thick-film silicon epitaxial wafers with a silicon epitaxial layer thickness greater than 100μm was significantly improved, with a product qualification rate increased by 7%, meeting the batch production requirements of power electronic high-voltage devices. Secondly, it overcomes the problems of complex processes and low production capacity caused by traditional thick-film silicon epitaxial wafer preparation methods, such as the need to first grow a silicon epitaxial buffer layer or significantly extend the heating time. It achieves a significant increase of 10% in the daily output of large-size thick-film silicon epitaxial wafers without adding additional processes, and is suitable for the industrial mass production requirements of large-size thick-film silicon epitaxial wafers with a silicon epitaxial layer thickness greater than 100μm. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments, comparative embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 Schematic diagrams of silicon epitaxial wafers produced in Embodiments 1 to 4 of the present invention;

[0022] Figure 2 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 1;

[0023] Figure 3 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 2;

[0024] Figure 4 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 3;

[0025] Figure 5 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 4;

[0026] Figure 6 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 5;

[0027] Figure 7 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 6;

[0028] Figure 8 This is a schematic diagram of the silicon epitaxial wafer produced in Example 7;

[0029] Figure 9 A schematic diagram of the silicon epitaxial wafer produced in Comparative Example 8;

[0030] Figure 10 This is a schematic diagram of the silicon epitaxial wafer produced in Comparative Example 9. Detailed Implementation

[0031] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the embodiments of the invention are not limited thereto.

[0032] A method for improving the crystal quality of large-size thick-film silicon epitaxial wafers is disclosed. The target growth thickness of the silicon epitaxial layer is greater than 100 μm. The heating power of the reaction chamber in the silicon epitaxial furnace is set to 80-84 kW. The chamber pressure is maintained at -1.3 to -1.7 mbar during the silicon epitaxial layer growth process. The crystal orientation of the silicon substrate is... <100> ±0.5°, diameter 150mm, resistivity 0.002~0.005Ω·cm, front surface polished, back surface successively coated with 800nm ​​thick polycrystalline silicon layer and 500nm thick silicon dioxide layer, silicon substrate edge chamfer type set to R type, chamfer angle set to 22°, chamfer width set to 380μm. Example 1;

[0033] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 30mm, and adjust the radial temperature field of the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0034] Step 2: Heat the reaction chamber to 1125℃, and introduce hydrogen chloride gas to etch the reaction chamber and the graphite substrate inside to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0035] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 90 sec.

[0036] Step 4: Cool the reaction chamber to 345℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0037] Step 5: The reaction chamber is heated to 1055℃ for 15 minutes, and then the temperature is maintained for 2 minutes. Hydrogen carrying gaseous trichlorosilane is introduced into the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 150 L / min, the trichlorosilane flow rate is set to 13 L / min, the ramp-up time is set to 60 seconds, and the venting time in the venting pipe is set to 60 seconds. The trichlorosilane and hydrogen flow rates then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0038] Step 6: After the silicon epitaxial layer growth is completed, the reaction chamber is cooled to 335°C and the cooling time is set to 19 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 55°C naturally, it is removed from the wafer carrier basket.

[0039] Example 2;

[0040] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 18mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 3℃.

[0041] Step 2: Heat the reaction chamber to 1118℃, and introduce hydrogen chloride gas to etch the reaction chamber and the graphite substrate inside to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 36L / min, and the etching time is set to 11min.

[0042] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 155 L / min and the trichlorosilane flow rate is set to 14 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0043] Step 4: Cool the reaction chamber to 320℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0044] Step 5: The reaction chamber is heated to 1055℃ for 13 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 155 L / min, the trichlorosilane flow rate is set to 12 L / min, the ramp-up time is set to 35 seconds, and the venting time in the venting pipe is set to 55 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 1.9 μm / min.

[0045] Step 6: After the silicon epitaxial layer growth is completed, the reaction chamber is cooled to 335°C and the cooling time is set to 16 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 55°C naturally, it is removed from the wafer carrier basket.

[0046] Example 3;

[0047] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 24mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 4℃.

[0048] Step 2: Heat the reaction chamber to 1110℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 34L / min, and the etching time is set to 12min.

[0049] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 140 L / min and the trichlorosilane flow rate is set to 11 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 110 sec.

[0050] Step 4: Cool the reaction chamber to 325℃, maintain the flatness of the graphite base at 0.3mm, and place the silicon substrate in the center of the graphite base pit.

[0051] Step 5: The reaction chamber is heated to 1050℃ for 14 minutes, and then the temperature is maintained for 2 minutes. Hydrogen carrying gaseous trichlorosilane is introduced into the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 140 L / min, the trichlorosilane flow rate is set to 11 L / min, the ramp-up time is set to 40 seconds, and the venting time in the venting pipe is set to 35 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 3 r / min, and the growth rate of the silicon epitaxial layer is set to 1.8 μm / min.

[0052] Step 6: After the silicon epitaxial layer growth is completed, the reaction chamber is cooled to 330°C and the cooling time is set to 20 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 50°C naturally, it is removed from the wafer carrier basket.

[0053] Example 4;

[0054] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0055] Step 2: Heat the reaction chamber to 1120℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 36L / min, and the etching time is set to 11min.

[0056] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 160 L / min and the trichlorosilane flow rate is set to 14 L / min. A 1 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0057] Step 4: Cool the reaction chamber to 348℃, keep the flatness of the graphite base at 0.5mm, and place the silicon substrate in the center of the graphite base pit.

[0058] Step 5: The reaction chamber is heated to 1058℃ for 14 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 157 L / min, the trichlorosilane flow rate is set to 11 L / min, the ramp-up time is set to 45 seconds, and the venting time in the venting pipe is set to 33 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0059] Step 6: After the silicon epitaxial layer growth is completed, the reaction chamber is cooled to 310°C and the cooling time is set to 18 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 54°C naturally, it is removed from the wafer carrier basket.

[0060] The silicon epitaxial wafers obtained in Examples 1-4 are of good quality, without edge chipping, breakage, or cracking, thus meeting the objectives of this invention. Schematic diagrams are shown below. Figure 1 As shown.

[0061] Comparative Example 1;

[0062] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base, so that the temperature gradient difference is set to 5℃.

[0063] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0064] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0065] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0066] Step 5: The reaction chamber is heated to 1080℃ for 16 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane is introduced into the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 150 L / min, the trichlorosilane flow rate is set to 12 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0067] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0068] The silicon epitaxial wafer 1 prepared in Comparative Example 1 exhibits irregularly shaped cracks 2 that extend inward, causing the silicon epitaxial wafer to break, as shown in the schematic diagram. Figure 2 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality of the silicon epitaxial wafer is poor. This indicates that the growth temperature of the silicon epitaxial layer was set too high, and the excessive thermal stress caused severe deformation of the silicon epitaxial layer, which affected the crystal quality of the thick silicon epitaxial wafer.

[0069] Comparative Example 2;

[0070] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0071] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0072] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0073] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0074] Step 5: The reaction chamber is heated to 1040℃ for 12 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 150 L / min, the trichlorosilane flow rate is set to 12 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.5 μm / min.

[0075] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0076] In contrast to Example 2, the silicon epitaxial wafer 1 exhibits a transverse and longitudinal intersecting straight crack 3 at the arc surface, which extends inward, causing the silicon epitaxial wafer to break. A schematic diagram is shown below. Figure 3 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality is poor. This indicates that the growth rate of the silicon epitaxial layer is too fast, resulting in uneven thickness distribution of the silicon epitaxial layer, causing excessive mechanical stress, and affecting the crystal quality of the silicon epitaxial wafer.

[0077] Comparative Example 3;

[0078] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0079] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0080] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0081] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.8mm, and place the silicon substrate in the center of the graphite base pit.

[0082] Step 5: The reaction chamber is heated to 1060℃ for 12 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 160 L / min, the trichlorosilane flow rate is set to 13 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0083] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0084] In Comparative Example 3, the silicon epitaxial wafer 1 prepared in the same furnace exhibits a longitudinal through-crack 4 at the junction of the reference plane and the arc surface, resulting in wafer breakage. A schematic diagram is shown below. Figure 4 As shown, the silicon epitaxial wafer growth quality is poor, which does not meet the requirements of the invention. This indicates that the graphite substrate inside the silicon epitaxial furnace is not level enough, resulting in uneven heating of each silicon epitaxial wafer. The accumulated thermal stress causes severe deformation of the silicon epitaxial wafer, affecting the crystal quality of the silicon epitaxial wafer.

[0085] Comparative Example 4;

[0086] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0087] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0088] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0089] Step 4: Cool the reaction chamber to 350℃, keep the flatness of the graphite base at 0.4mm, and place the silicon substrate in the pit of the graphite base and attach it to the left edge.

[0090] Step 5: The reaction chamber is heated to 1060℃ for 16 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 160 L / min, the trichlorosilane flow rate is set to 13 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0091] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0092] In contrast, the silicon epitaxial wafer 1 prepared in Example 4 simultaneously exhibits a triangular chipping edge 5 at the arc-shaped surface and a short straight crack 6 at the arc-shaped surface, as shown in the schematic diagram. Figure 5 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality of the silicon epitaxial wafer is poor. This indicates that the silicon substrate is attached to the left edge of the graphite base, resulting in an excessive temperature gradient at the edge of the silicon epitaxial wafer, which causes a large number of lattice defects and affects the crystal quality of the silicon epitaxial wafer.

[0093] Comparative Example 5;

[0094] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0095] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0096] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0097] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0098] Step 5: The reaction chamber is heated to 1060℃, and the heating time is set to 12min. Hydrogen carries gaseous trichlorosilane into the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 160L / min, the trichlorosilane flow rate is set to 13L / min, the ramp-up time is set to 30sec, and the venting time in the venting pipe is set to 30sec. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4r / min, and the growth rate of the silicon epitaxial layer is set to 2.0μm / min.

[0099] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 8 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0100] In contrast, the silicon epitaxial wafer 1 prepared in Example 5 exhibited a transverse through-crack 7 at the arc-shaped surface, which caused the silicon epitaxial wafer to break, as shown in the schematic diagram. Figure 6 As shown, the growth quality of the silicon epitaxial wafer is poor, which does not meet the requirements of the invention. This indicates that hydrogen and trichlorosilane were introduced into the reaction chamber before the process temperature reached thermal stability for the growth of the silicon epitaxial layer. This caused uneven heating of the silicon epitaxial layer growth material inside the chamber, which directly resulted in poor uniformity of the thickness distribution of the thick silicon epitaxial layer, leading to severe mechanical stress within the wafer and affecting the crystal quality of the thick silicon epitaxial wafer.

[0101] Comparative Example 6;

[0102] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0103] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0104] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0105] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0106] Step 5: The reaction chamber is heated to 1060℃ for 16 minutes. Hydrogen carries gaseous trichlorosilane into the reaction chamber of the silicon epitaxial furnace. The hydrogen flow rate is set to 160 L / min and the trichlorosilane flow rate is set to 13 L / min. Silicon epitaxial layer is grown on the polished surface of the silicon substrate. The rotation speed of the graphite substrate is set to 4 r / min and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0107] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0108] In contrast, the silicon epitaxial wafer prepared in Example 6 exhibited a longitudinal through-crack 8 at the reference plane position, which extended inward and caused the silicon epitaxial wafer to break, as shown in the schematic diagram. Figure 7 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality of the silicon epitaxial wafer is poor. This indicates that hydrogen and trichlorosilane entered the reaction chamber of the silicon epitaxial furnace before reaching a steady state, causing original lattice defects in the initial growth stage of the silicon epitaxial layer, which leads to serious crystal quality problems in the thick silicon epitaxial wafer.

[0109] Comparative Example 7;

[0110] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0111] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0112] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0113] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0114] Step 5: The reaction chamber is heated to 1060℃ for 10 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 160 L / min, the trichlorosilane flow rate is set to 15 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0115] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0116] In contrast, the silicon epitaxial wafer 1 prepared in Example 7 exhibits dense, long, straight cracks 9 at the arc-shaped surface, which extend laterally inward, causing the silicon epitaxial wafer to break. A schematic diagram is shown below. Figure 8 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality is poor. This indicates that the heating rate is too fast, resulting in a large accumulation of thermal stress within the wafer during the initial growth stage of the silicon epitaxial layer, which leads to serious crystal quality problems in the thick silicon epitaxial wafer.

[0117] Comparative Example 8;

[0118] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 28mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 5℃.

[0119] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0120] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0121] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0122] Step 5: The reaction chamber is heated to 1060℃ for 16 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane is introduced into the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 160 L / min, the trichlorosilane flow rate is set to 13 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 6 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0123] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0124] The silicon epitaxial wafer 1 prepared in Comparative Example 8 exhibits an arc-shaped chipping edge 10 at the arc-shaped surface position, as shown in the schematic diagram. Figure 9 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality is poor. This indicates that the rotation speed of the graphite substrate is too fast, which increases the risk of collision between the silicon substrate and the edge of the pit of the graphite substrate, causing serious crystal quality problems such as edge chipping of the thick silicon epitaxial wafer.

[0125] Comparative Example 9;

[0126] Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it to 40mm, and adjust the radial temperature field in the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is set to 8℃.

[0127] Step 2: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 35L / min, and the etching time is set to 10min.

[0128] Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 150 L / min and the trichlorosilane flow rate is set to 13 L / min. A 2 μm thick polycrystalline silicon coating layer is uniformly deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60 sec.

[0129] Step 4: Cool the reaction chamber to 350℃, maintain the flatness of the graphite base at 0.4mm, and place the silicon substrate in the center of the graphite base pit.

[0130] Step 5: The reaction chamber is heated to 1060℃ for 16 minutes, and then the temperature is maintained for 1 minute. Hydrogen carrying gaseous trichlorosilane enters the venting pipe of the silicon epitaxial furnace. The hydrogen flow rate is set to 160 L / min, the trichlorosilane flow rate is set to 13 L / min, the ramp-up time is set to 30 seconds, and the venting time in the venting pipe is set to 30 seconds. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite substrate is set to 4 r / min, and the growth rate of the silicon epitaxial layer is set to 2.0 μm / min.

[0131] Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 350°C for 15 minutes. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 60°C, it is removed from the wafer carrier basket.

[0132] The silicon epitaxial wafer prepared in Comparative Example 9 exhibits dense short straight-line cracks 11 at the reference plane location, as shown in the schematic diagram. Figure 10 As shown, the silicon epitaxial wafer does not meet the requirements of the invention, and the growth quality of the silicon epitaxial wafer is poor. This indicates that the radial temperature field difference of the silicon substrate is too large, resulting in a large accumulation of thermal stress in the initial growth stage of the silicon epitaxial layer, which leads to serious crystal quality problems in the thick silicon epitaxial layer.

[0133] The experimental results of Examples 1-4 and Comparative Examples 1-9 show that the silicon epitaxial wafers grown using the preparation techniques of Examples 1-4 of the present invention do not have edge chipping, breakage, or cracking, thus meeting the purpose of the present invention. However, the silicon epitaxial wafers grown using the preparation techniques of Comparative Examples 1-9 have varying degrees of edge chipping, breakage, and cracking, thus failing to meet the purpose of the present invention.

[0134] This invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of this invention, various simple modifications can be made to the technical solution of this invention, and these simple modifications all fall within the protection scope of this invention.

Claims

1. A method for preparing large-size thick-film silicon epitaxial wafers with improved crystal quality, characterized in that, The steps are as follows: Step 1: Adjust the height adjustment rod of the induction heating coil in the reaction chamber of the multi-wafer silicon epitaxial furnace, set the distance between the induction heating coil and the horizontal disc-shaped graphite base above it, and adjust the radial temperature field of the area where the silicon substrate is placed in the pit of the graphite base so that the temperature gradient difference is 2~5℃. Step 2: Heat the reaction chamber to 1110~1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and the graphite substrate inside to remove impurities in the chamber. The hydrogen chloride gas flow rate is set to 34~36 L / min, and the etching time is set to 10~12 min. Step 3: Hydrogen carries gaseous trichlorosilane into the reaction chamber. The hydrogen flow rate is set to 140~160 L / min and the trichlorosilane flow rate is set to 10~16 L / min. A polycrystalline silicon coating layer with a thickness of 1~2 μm is deposited on the graphite substrate in the reaction chamber. The deposition time is set to 60~120 sec. Step 4: Cool the reaction chamber to 300~350℃, keep the flatness of the graphite base at 0.3~0.5mm, and place the silicon substrate in the center of the pit in the graphite base; Step 5: The reaction chamber is heated to 1050~1060℃ for 12~16 min, and then held at this temperature for 1~2 min. Hydrogen carries gaseous trichlorosilane into the venting pipe of the multi-wafer silicon epitaxial furnace. The hydrogen flow rate is set to 140~160 L / min, the trichlorosilane flow rate is set to 10~13 L / min, the ramp-up time is set to 30~60 sec, and the venting time in the venting pipe is set to 30~60 sec. Trichlorosilane and hydrogen then enter the reaction chamber to grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The rotation speed of the graphite base is set to 3~4 r / min, and the growth rate of the silicon epitaxial layer is set to 1.8~2.0 μm / min. Step 6: After the silicon epitaxial layer is grown, the reaction chamber is cooled to 300~350℃ and the cooling time is set to 15~20min. The silicon epitaxial wafer is then removed from the reaction chamber and placed in the wafer carrier basket. After the silicon epitaxial wafer cools down to 50~60℃ naturally, it is removed from the wafer carrier basket. In step 1, the distance between the induction heating coil and the horizontal disc-shaped graphite base above it is set to 15~30 mm; The target growth thickness of the silicon epitaxial layer is greater than 100 μm; The heating power of the reaction chamber of the multi-wafer silicon epitaxial furnace during the silicon epitaxial layer growth process is set to 80~84KW, and the pressure of the reaction chamber is maintained at -1.3~-1.7 mbar.

2. The method for preparing large-size thick-film silicon epitaxial wafers according to claim 1, characterized in that: In step 1, the silicon substrate is placed centered in the pit of the graphite base. The edge chamfer type of the silicon substrate is set to R-type, the chamfer angle is set to 22°, and the chamfer width is set to 300~400 μm.

3. The method for preparing large-size thick-film silicon epitaxial wafers with improved crystal quality according to claim 1, characterized in that: The silicon substrate has a crystal orientation of <100> ±0.5°, diameter 150~200mm, resistivity 0.002~0.005Ω·cm, oxygen content 14~18ppma, front surface polished, back surface successively coated with a polycrystalline silicon layer with a thickness of 800~1000nm and a silicon dioxide layer with a thickness of 450~550nm.

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