Defect monitoring structure and monitoring method of through silicon via structure

Abstract

The present invention relates to a defect monitoring structure for a through-silicon via (TSV) structure and a monitoring method thereof. The defect monitoring structure for the TSV structure comprises: a semiconductor substrate, a TSV structure, a first conductive wire layer, a second conductive wire layer, and an induction coil; the TSV structure comprises a first TSV structure and a second TSV structure, each of which comprises a TSV, a dielectric layer, and a conductive column; the induction coil is connected to the conductive columns of the first conductive wire layer and the second TSV structure; and the antenna structure is located above the inductor structure having the TSV structure and is spaced apart from the inductor structure having the TSV structure. Based on the inductive coupling between the antenna structure and the inductor structure having the TSV structure, the scattering parameter corresponding to the antenna structure can be quickly determined, and based on the scattering parameter, it can be quickly and accurately determined whether there are defects in the TSV structure. In this way, while reducing costs, it is possible to quickly and accurately monitor whether there are defects in the TSV structure in real time.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a defect monitoring structure of a through silicon via (TSV) structure and a monitoring method thereof. Background Art

[0002] With the development of integrated circuit technology, through-silicon-via (TSV) technology has become a popular technology in semiconductor device packaging due to its advantages such as the shortest interconnect path in three-dimensional stacking, low power consumption, and high operating speed. The TSV structure produced by TSV technology can directly penetrate the substrate, providing high-speed interconnection between the top and bottom of the substrate.

[0003] Due to reasons such as the preparation process and materials, some TSV structures have defects. For example, due to the different thermal expansion coefficients of the dielectric layer and the substrate, pinhole defects will be generated on the surface of the dielectric layer around the TSV (for example, silicon dioxide insulator) or inside the dielectric layer. The pinhole defects will cause leakage current of the TSV structure to flow into the substrate. In addition, due to incomplete filling, stress cracking or imperfect manufacturing technology inside the TSV, cavity or void defects will be generated in the TSV structure. The void defects will cause a delay in the length of the TSV structure data. However, most of these defects are concentrated in the TSV structure and are difficult to monitor intuitively from the outside, which seriously hinders the development of integrated circuit technology. The currently commonly used defect monitoring methods for TSV structures have problems such as high cost, long time consumption and inaccurate defect monitoring, which seriously affect the promotion of integrated circuits.

[0004] Therefore, how to quickly and accurately monitor defects in silicon through-via structures in real time while reducing costs is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] Based on this, it is necessary to provide a defect monitoring structure and a monitoring method for a through silicon via structure, aiming to achieve rapid and accurate real-time monitoring of whether the through silicon via structure has defects while reducing costs.

[0006] The present invention provides a defect monitoring structure for a through silicon via structure, including:

[0007] An inductor structure having a through-silicon via (TSV) structure comprises: a semiconductor substrate, a TSV structure, a first conductive line layer, a second conductive line layer, and an inductive coil; the TSV structure comprises a first TSV structure and a second TSV structure, each of the first TSV structure and the second TSV structure comprising a TSV, a dielectric layer, and a conductive pillar; the TSV is located within the semiconductor substrate and penetrates the semiconductor substrate along its thickness direction; the dielectric layer covers the sidewalls of the TSV; the conductive pillar is located within the TSV and fills the TSV; the first conductive line layer is located above the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars of the first TSV structure; the second conductive line layer is located below the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars in the first TSV structure and the conductive pillars in the second TSV structure; the inductive coil is located above the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars in the first TSV structure and the second TSV structure;

[0008] The antenna structure is located above the inductor structure having the through silicon via structure and has a distance therebetween from the inductor structure having the through silicon via structure.

[0009] The defect monitoring structure of the above-mentioned through silicon via structure includes: an inductor structure and an antenna structure with a through silicon via structure, wherein the inductor structure with the through silicon via structure includes: a semiconductor substrate, a through silicon via structure, a first wire layer, a second wire layer and an induction coil; the through silicon via structure includes a first through silicon via structure and a second through silicon via structure, and the first through silicon via structure and the second through silicon via structure both include a through silicon via, a dielectric layer and a conductive column; the through silicon via is located in the semiconductor substrate and penetrates the semiconductor substrate along the thickness direction; the dielectric layer covers the sidewall of the through silicon via; the conductive column is located in the through silicon via and fills the through silicon via; A first conductive layer is located above the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars of the first through-silicon via structure; a second conductive layer is located below the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to both the conductive pillars of the first through-silicon via structure and the conductive pillars of the second through-silicon via structure; an induction coil is located above the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to both the conductive pillars of the first conductive layer and the conductive pillars of the second through-silicon via structure; an antenna structure is located above the inductor structure having the through-silicon via structure and is spaced apart from the inductor structure having the through-silicon via structure. In the present application, a scattering parameter corresponding to the antenna structure can be quickly determined based solely on the inductive coupling between the antenna structure and the inductor structure having the through-silicon via structure, and based on the scattering parameter, a rapid and accurate determination can be made as to whether there are defects in the through-silicon via structure. This allows for rapid and accurate real-time monitoring of defects in the through-silicon via structure while reducing costs, thereby preventing the impact of defects in the through-silicon via structure on the integrated circuit.

[0010] Optionally, the shape of the antenna structure is the same as that of the induction coil, and the orthographic projection of the antenna structure in the plane where the induction coil is located coincides with the induction coil.

[0011] Optionally, the shape of the antenna structure and the shape of the induction coil are both spiral.

[0012] Optionally, the inductor structure having through silicon vias further includes:

[0013] a first isolation layer, located on the upper surface of the semiconductor substrate; the first wire layer and the induction coil are both located on the upper surface of the first isolation layer;

[0014] a second isolation layer, located on the lower surface of the semiconductor substrate; and the second conductive line layer is located on the lower surface of the second isolation layer;

[0015] The through silicon via also penetrates the first isolation layer and the second isolation layer along a thickness direction.

[0016] Based on the same inventive concept, the present application also provides a method for preparing a defect monitoring structure of a through silicon via structure, comprising:

[0017] Providing a defect monitoring structure for the through silicon via structure described in the above embodiment;

[0018] Applying an excitation current to the inductor structure having the through silicon via structure;

[0019] Obtaining a scattering parameter based on inductive coupling between the antenna structure and the inductive structure having the through-silicon via structure;

[0020] It is determined whether there is a defect in the through silicon via structure based on the scattering parameter.

[0021] The method for preparing the above-mentioned defect monitoring structure for a through-silicon via structure includes: providing the defect monitoring structure for the through-silicon via structure described in the above-mentioned embodiment; applying an excitation current to an inductor structure having the through-silicon via structure; obtaining a scattering parameter based on the inductive coupling between the antenna structure and the inductor structure having the through-silicon via structure; and determining whether a defect exists in the through-silicon via structure based on the scattering parameter. In the present application, the scattering parameter corresponding to the antenna structure can be quickly determined based solely on the inductive coupling between the antenna structure and the inductor structure having the through-silicon via structure, and the presence of a defect in the through-silicon via structure can be quickly and accurately determined based on the scattering parameter. This allows for rapid and accurate real-time monitoring of defects in the through-silicon via structure while reducing costs, thereby preventing the impact of defects in the through-silicon via structure on the integrated circuit.

[0022] Optionally, the scattering parameter includes insertion loss; and judging whether there is a defect in the through silicon via structure based on the scattering parameter includes:

[0023] Obtaining a curve of the scattering parameter changing with frequency;

[0024] Comparing the variation curve with a target curve, wherein the target curve is a target variation curve of the scattering parameter of a defect monitoring structure of a defect-free through silicon via structure as a function of frequency under the excitation current;

[0025] If the peak value of the variation curve becomes smaller than the peak value of the target curve or shifts toward a lower frequency, it is determined that there is a defect in the through silicon via structure.

[0026] Optionally, after determining that there are defects in the through silicon via structure, the method further includes:

[0027] If the peak value of the change curve becomes smaller than the peak value of the target curve, it is determined that the defect existing in the silicon via structure includes at least one of a void defect and a pinhole defect; if it is determined that the peak value of the change curve shifts toward a small frequency direction compared to the peak value of the target curve, it is determined that the defect existing in the silicon via structure includes an open circuit defect.

[0028] Optionally, before providing the defect monitoring structure of the through silicon via structure as described in the above embodiment, the method further includes: setting a distance between the antenna structure and the inductor structure having the through silicon via.

[0029] Optionally, the distance between the antenna structure and the inductor structure having the through silicon via is 5 μm-30 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 A schematic cross-sectional view of a defect monitoring structure of a through silicon via structure provided in one embodiment of the present application;

[0032] Figure 2 A schematic top view of a defect monitoring structure of a through silicon via structure provided in one embodiment of the present application;

[0033] Figure 3 A schematic cross-sectional view of a defect monitoring structure of another through silicon via structure provided in one embodiment of the present application;

[0034] Figure 4A flowchart of a defect monitoring method for a through silicon via structure provided in different embodiments of the present application;

[0035] Figures 5A-5B A comparison diagram of a curve showing insertion loss versus frequency when a void defect exists in a through silicon via structure provided in different embodiments of the present application and a target curve;

[0036] Figures 6A-6B A comparison diagram of a curve showing a change in insertion loss versus frequency and a target curve when a pinhole defect exists in a through silicon via structure provided in an embodiment of the present application;

[0037] Figure 7 A comparison diagram of a curve showing a change in insertion loss versus frequency and a target curve when an open defect exists in a through silicon via structure provided in an embodiment of the present application;

[0038] Figure 8 This is a graph showing how insertion loss varies with frequency at different distances between an antenna structure and an inductor structure having through-silicon vias according to an embodiment of the present application.

[0039] Description of reference numerals:

[0040] 1. Inductor structure; 2. Antenna structure; 10. Semiconductor substrate; 20. Through-silicon via (TSV) structure; 201. First TSV structure; 202. Second TSV structure; 2011. TSV; 2012. Dielectric layer; 2013. Conductive pillar; 30. First conductor layer; 40. Second conductor layer; 50. Induction coil; 60. First isolation layer; 70. Second isolation layer. DETAILED DESCRIPTION

[0041] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0044] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0045] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0047] Currently, common defect monitoring methods for through-silicon via (TSV) structures are categorized as contact and non-contact. Contact monitoring methods primarily include probes, while non-contact methods include capacitive coupling, ultrasonic monitoring, and lock-in thermal imaging. While the probe method can accurately determine TSV failure, existing contact monitoring methods suffer from poor mobility, high cost, and a high failure rate. Non-contact monitoring methods also suffer from short monitoring distances, long monitoring times, and high costs. Furthermore, they are unable to conduct real-time monitoring during the product's service life, severely hindering the widespread adoption of 3D integrated circuits.

[0048] Therefore, how to quickly and accurately monitor defects in silicon through-via structures in real time while reducing costs is a technical problem that needs to be solved urgently.

[0049] In view of the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a defect monitoring structure for a through-silicon via structure and a monitoring method thereof, aiming to achieve rapid and accurate real-time monitoring of defects in the through-silicon via structure while reducing costs, thereby avoiding the impact of defects in the through-silicon via structure on integrated circuits.

[0050] See also Figure 1The present application provides a defect monitoring structure of a through silicon via structure, comprising: an inductor structure 1 having a through silicon via structure, comprising: a semiconductor substrate 10, a through silicon via structure 20, a first wire layer 30, a second wire layer 40 and an induction coil 50; the through silicon via structure 20 comprises a first through silicon via structure 201 and a second through silicon via structure 202, each of the first through silicon via structure 201 and the second through silicon via structure 202 comprising a through silicon via 2011, a dielectric layer 2012 and a conductive pillar 2013; the through silicon via 2011 is located in the semiconductor substrate 10 and penetrates the semiconductor substrate 10 along the thickness direction; the dielectric layer 2012 covers the sidewall of the through silicon via 2011; the conductive pillar 2013 ... conductive pillar 2013 is located in the semiconductor substrate 10 and penetrates the semiconductor substrate 10 along the thickness direction; the conductive pillar 2013 is located in the semiconductor substrate 10 and penetrates the semiconductor substrate 10 along the thickness direction; the conductive pillar 2013 is located in the semiconductor substrate 10 and penetrates the semiconductor substrate 10 along the thickness direction; the conductive pillar 2013 is located in the semiconductor substrate The first conductive layer 30 is located above the semiconductor substrate 10, insulated and isolated from the semiconductor substrate 10, and connected to the conductive pillar 2013 of the first through-silicon via structure 201. The second conductive layer 40 is located below the semiconductor substrate 10, insulated and isolated from the semiconductor substrate 10, and connected to the conductive pillar 2013 of the first through-silicon via structure 201 and the conductive pillar 2013 of the second through-silicon via structure 202. The induction coil 50 is located above the semiconductor substrate 10, insulated and isolated from the semiconductor substrate 10, and connected to the first conductive layer 30 and the conductive pillar 2013 of the second through-silicon via structure 202.

[0051] The antenna structure 2 is located above the inductor structure 1 having the through silicon via structure and has a distance therebetween from the inductor structure 1 having the through silicon via structure.

[0052] Optionally, the semiconductor substrate 10 may include a high-resistance silicon substrate, the conductivity of which may be but not limited to 10 S / M. The height of the semiconductor substrate 10 may be but not limited to 50 μm, and the length and width may be but not limited to 100 μm.

[0053] Optionally, the TSV structure 20 includes a first TSV structure 201 and a second TSV structure 202. The spacing between the first TSV structure 201 and the second TSV structure 202 may be, but is not limited to, 40 μm. In this embodiment, the TSV structure 20 can reduce interconnect length, signal delay, and inductance through vertical interconnection, thereby achieving low power consumption, high-speed communication between chips, increased bandwidth, and miniaturized device integration.

[0054] Optionally, both the first TSV structure 201 and the second TSV structure 202 include a TSV 2011, a dielectric layer 2012, and a conductive pillar 2013. Optionally, a dry etching process may be used to etch the TSV 2011 in the semiconductor substrate 10, wherein the TSV 2011 may have a radius of 2-12 μm. For example, the TSV 2011 may have a radius of 2 μm, 5 μm, 10 μm, or 12 μm.

[0055] Dielectric layer 2012 may be an annular dielectric layer, wherein the annular dielectric layer is a benzocyclobutene layer. Benzocyclobutene has a low dielectric constant and a large thickness, and has high isolation performance. The thickness of dielectric layer 2012 may be 0.1-2 μm, and the thickness of dielectric layer 2012 may be 0.1 μm, 0.5 μm, 1 μm, 1.5 μm, or 2 μm.

[0056] Alternatively, the conductive pillars 2013 may be any conductive structure. Alternatively, the conductive pillars 2013 may be metal pillars, enabling signal transmission. Exemplarily, the conductive pillars 2013 may be made of a conductive material such as copper, tungsten, or aluminum, and are used to fill the through-silicon vias 2011. Specifically, physical vapor deposition may be used to prepare a structure having the dielectric layer 2012, and then the conductive pillars 2013 may be used to fill the through-silicon vias 2011.

[0057] Optionally, a first conductive layer 30 can be formed on the upper surface of the first TSV structure 201 using a mask, wherein the first conductive layer 30 can be isolated from the semiconductor substrate 10 using an insulating material. Furthermore, a second conductive layer 40 can be formed on the lower surfaces of the first TSV structure 201 and the second TSV structure 202 using a mask, wherein the second conductive layer 40 can also be isolated from the semiconductor substrate 10 using an insulating material. In this embodiment, the first conductive layer 30 and the second conductive layer 40 respectively connect the upper and lower surfaces of the conductive pillars 2013 in the vertically distributed TSV structure 20, thereby achieving metal interconnection and thus enabling signal transmission. For example, the first conductive layer 30 and the second conductive layer 40 can be copper, aluminum, or gold layers.

[0058] Optionally, in this embodiment, the induction coil 50 can be formed on the upper surface of the semiconductor substrate 10 by electroplating, physical / magnetron sputtering, evaporation, deposition, etc. The induction coil 50 can be a coil with any number of turns, and the number of turns of the induction coil 50 is not limited in this embodiment.

[0059] Similarly, the antenna structure 2 can be fabricated above the inductor structure 1 having a through-silicon via structure using the same method as that used to fabricate the induction coil 50. Specifically, the antenna structure 2 can be fabricated above the inductor structure 1 having a through-silicon via structure using methods such as electroplating, physical / magnetron sputtering, evaporation, and deposition. That is, in this embodiment, the antenna structure 2 and the inductor structure 1 are non-contact, which facilitates the subsequent generation of an induced magnetic field on the antenna structure 2 under the excitation of the induced current.

[0060] In an optional embodiment, the spacing between the antenna structure 2 and the inductor structure 1 having through-silicon vias is 5μm-30μm. For example, the spacing between the antenna structure 2 and the inductor structure 1 having through-silicon vias is 5μm, 8μm, 10μm, 15μm, 20μm, and 30μm. Preferably, the spacing between the antenna structure 2 and the inductor structure 1 having through-silicon vias can be set to 5-20μm. In this case, the energy interaction between the antenna structure 2 and the inductor structure 1 having through-silicon vias is large, which facilitates the subsequent monitoring of changes in the corresponding scattering parameters in the antenna structure 2. Since the antenna structure 2 and the inductor structure 1 having through-silicon vias are non-contact, this can avoid direct contact between the antenna structure 2 and the inductor structure 1 having through-silicon vias, reduce the interference of the antenna structure 2 on the circuit in the inductor structure 1, and enable the circuit in the inductor structure 1 to operate normally.

[0061] In another optional embodiment, please refer to Figure 2 The shape of the antenna structure 2 is the same as that of the induction coil 50, and the orthographic projection of the antenna structure 2 in the plane where the induction coil 50 is located coincides with the induction coil 50. Optionally, the shape of the antenna structure 2 and the shape of the induction coil 50 are both spiral. Exemplarily, the shape of the antenna structure 2 and the shape of the induction coil 50 can both be spiral coils, and the line width of the antenna structure 2 can be 10 μm, the coil spacing can be 2 μm, and the thickness can be 1 μm.

[0062] In this embodiment, when an excitation current is applied to the inductive structure 1, inductive coupling can be formed between the antenna structure 2 and the inductive coil 50 by utilizing the fact that the antenna structure 2 and the inductive coil 50 are isolated from each other, have the same spiral shape, and are disposed in a corresponding manner. That is, under the excitation of the induced current applied to the inductive structure 1, an induced magnetic field is generated around the antenna structure 2. By observing the changes in the distribution of the induced magnetic field around the antenna structure 2, the changes in the coupling between the antenna structure 2 and the inductive coil 50 can be determined, and the changes in signal transmission performance can be intuitively compared to determine whether the monitoring silicon via structure 20 has defects. Optionally, the corresponding scattering parameters of the antenna structure 2 can be used to determine whether the signal transmission performance of the silicon via structure 20 has degraded. If degraded, it indicates that the silicon via structure 20 has defects.

[0063] The defect monitoring structure of the through silicon via structure includes: an inductor structure 1 with a through silicon via structure and an antenna structure 2, wherein the inductor structure 1 with a through silicon via structure includes: a semiconductor substrate 10, a through silicon via structure 20, a first wire layer 30, a second wire layer 40 and an induction coil 50; the through silicon via structure 20 includes a first through silicon via structure 201 and a second through silicon via structure 202, and the first through silicon via structure 201 and the second through silicon via structure 202 each include a through silicon via 2011, a dielectric layer 2012 and a conductive pillar 2013; the through silicon via 2011 is located in the semiconductor substrate 10 and penetrates the semiconductor substrate 10 along the thickness direction; the dielectric layer 2012 covers the sidewall of the through silicon via 2011; the conductive pillar 2013 is located in the through silicon via 2011 and is filled with silicon. Through hole 2011; the first conductive layer 30 is located above the semiconductor substrate 10, insulated and isolated from the semiconductor substrate 10, and connected to the conductive pillar 2013 of the first through-silicon via structure 201; the second conductive layer 40 is located below the semiconductor substrate 10, insulated and isolated from the semiconductor substrate 10, and connected to the conductive pillar 2013 of the first through-silicon via structure 201 and the conductive pillar 2013 in the second through-silicon via structure 202; the induction coil 50 is located above the semiconductor substrate 10, insulated and isolated from the semiconductor substrate 10, and connected to the first conductive layer 30 and the conductive pillar 2013 of the second through-silicon via structure 202; the antenna structure 2 is located above the inductor structure 1 having the through-silicon via structure, and is spaced apart from the inductor structure 1 having the through-silicon via structure. In the present application, the scattering parameters corresponding to the antenna structure can be quickly determined based solely on the inductive coupling between the antenna structure 1 and the inductive structure 2 having a through-silicon via structure, and based on the scattering parameters, it can be quickly and accurately determined whether there are defects in the through-silicon via structure 20. In this way, while reducing costs, it is possible to quickly and accurately monitor in real time whether there are defects in the through-silicon via structure, thereby avoiding the impact of defects in the through-silicon via structure on the integrated circuit.

[0064] See also Figure 3 In an optional embodiment, the inductor structure 10 with a through silicon via further includes a first isolation layer 60 located on the upper surface of the semiconductor substrate 10; the first conductive layer 30 and the inductive coil 50 are both located on the upper surface of the first isolation layer 60; a second isolation layer 70 located on the lower surface of the semiconductor substrate 10; the second conductive layer 40 is located on the lower surface of the second isolation layer 70; and the through silicon via 2011 further penetrates the first isolation layer 60 and the second isolation layer 70 along the thickness direction.

[0065] Optionally, a physical spin coating method can be used to prepare a first isolation layer 60 on the upper surface of the semiconductor substrate 10, and a second isolation layer 70 on the lower surface of the semiconductor substrate 10. The first isolation layer 60 and the second isolation layer 70 can be any one or more of a silicon dioxide layer, a polyimide resin layer, etc., wherein the first isolation layer 60 and the second isolation layer 70 have a good isolation effect. The thickness of the first isolation layer 60 and the second isolation layer 7 can include 1-20 μm. Exemplarily, the first isolation layer 60 can include: 1 μm, 4 μm, 10 μm, 14 μm and 20 μm, and the second isolation layer 70 can include: 1 μm, 2 μm, 4 μm, 11 μm, 15 μm and 20 μm.

[0066] Based on the same invention concept, please combine Figures 1 to 3 See Figure 4 , the present application also provides a method for monitoring defects in a through silicon via structure, such as Figure 4 As shown, the following steps are included:

[0067] S10: providing a defect monitoring structure for the through silicon via structure provided in the above embodiment;

[0068] S20: applying an excitation current to the inductor structure having the through-silicon via structure;

[0069] S30: obtaining a scattering parameter based on inductive coupling between the antenna structure and the inductive structure having the through-silicon via structure;

[0070] S40: Determine whether there is a defect in the TSV structure based on the scattering parameters.

[0071] The above-mentioned method for monitoring defects in a through-silicon via structure provides the defect monitoring structure for the through-silicon via structure described in the above-mentioned embodiment; applies an excitation current to an inductor structure having a through-silicon via structure; obtains a scattering parameter based on the inductive coupling between the antenna structure and the inductor structure having the through-silicon via structure; and determines whether a defect exists in the through-silicon via structure based on the scattering parameter. In the present application, the scattering parameter corresponding to the antenna structure can be quickly determined based solely on the inductive coupling between the antenna structure and the inductor structure having the through-silicon via structure, and the presence of a defect in the through-silicon via structure can be quickly and accurately determined based on the scattering parameter. This allows for rapid and accurate real-time monitoring of defects in the through-silicon via structure while reducing costs, thereby preventing the impact of defects in the through-silicon via structure on the integrated circuit.

[0072] In step S10, a defect monitoring structure for a through silicon via structure is provided. In an optional embodiment, please refer to Figure 1 The preparation process of the defect monitoring structure of the through silicon via structure includes the following steps:

[0073] S101: providing a semiconductor substrate 10;

[0074] S102: etching a through silicon via 2011 on the semiconductor substrate 1;

[0075] S103: preparing a dielectric layer 2012 on the inner surface of the through silicon via 2011;

[0076] S104: forming a conductive pillar 2013 in the dielectric layer 2012; wherein the conductive pillar 2013 is located in the through silicon via 2011 and fills the through silicon via 2011; the through silicon via 2011, the dielectric layer 2012 and the conductive pillar 2013 form a through silicon via structure 20, wherein the through silicon via structure 20 includes a first through silicon via structure 201 and a second through silicon via structure 202;

[0077] S105: forming an induction coil 50 on the upper surface of the semiconductor substrate 10; the induction coil 50 is located above the semiconductor substrate 10, insulated from the semiconductor substrate 10, and connected to the first conductive layer 30 and the conductive pillar 2013 of the second through-silicon via structure 202;

[0078] S106: preparing a first conductive line layer 30 on the upper surface of the semiconductor substrate 10; wherein the first conductive line layer 30 is located above the semiconductor substrate 10, insulated from the semiconductor substrate 10, and connected to the conductive pillar 2013 of the first through silicon via structure 201;

[0079] S107: Preparing a second conductive line layer 40 on the lower surface of the semiconductor substrate 10; wherein the second conductive line layer 40 is located below the semiconductor substrate 10, insulated from the semiconductor substrate 10, and connected to the conductive pillars 2013 of the first through silicon via structure 201 and the conductive pillars 2013 of the second through silicon via structure 202;

[0080] S108 : forming an antenna structure 2 on the semiconductor substrate 10 .

[0081] Based on the above steps, another optional implementation method is to refer to Figure 3 ,exist Figure 1 Based on the defect monitoring structure of the TSV structure described above, the preparation process of the defect monitoring structure of the TSV structure further includes the following steps:

[0082] S109: preparing a first isolation layer 60 on the upper surface of the semiconductor substrate 10 ; wherein the first conductive line layer 30 and the induction coil 50 are both located on the upper surface of the first isolation layer 60 ;

[0083] S110 : preparing a second isolation layer 70 on the lower surface of the semiconductor substrate 10 ; the second conductive line layer 40 is located on the lower surface of the second isolation layer 70 ; and the through silicon via 2011 also penetrates the first isolation layer 60 and the second isolation layer 70 along the thickness direction.

[0084] Optionally, in step S101 , the semiconductor substrate 10 may include a high-resistance silicon substrate with a conductivity of 10 S / M. The height of the semiconductor substrate 10 may be 50 μm, and the length and width may both be 100 μm.

[0085] Optionally, in step S102, a dry etching process may be used to etch TSVs 2011 in the semiconductor substrate 10, wherein the TSVs 2011 may have a radius of 2-12 μm. For example, the radius of the TSVs 2011 may be 2 μm, 5 μm, 10 μm, 12 μm, etc.

[0086] Optionally, in step S103, a dielectric layer 2012 may be formed within the through-silicon via 2011 using physical vapor deposition (PVD), chemical vapor deposition (CVD), or PVD. The dielectric layer 2012 may be an annular dielectric layer, wherein the annular dielectric layer is a benzocyclobutene layer. Benzocyclobutene has a low dielectric constant and a large thickness, resulting in high isolation performance. The thickness of the dielectric layer 2012 may be 0.1-2 μm, and the thickness of the dielectric layer 2012 may be 0.1 μm, 0.5 μm, 1 μm, 1.5 μm, or 2 μm.

[0087] Optionally, in step S104, physical vapor deposition can be used to fill the through-silicon vias 2011 with conductive pillars 2013 in the structure having the dielectric layer 2012. The conductive pillars 2013 can be any conductive structure. Optionally, the conductive pillars 2013 can be metal pillars, which can be used to transmit signals. For example, the conductive pillars 2013 can be made of a conductive material such as copper, tungsten, or aluminum, and are used to fill the through-silicon vias 2011.

[0088] Optionally, in step S105, the induction coil 50 may be formed on the upper surface of the semiconductor substrate 10 by electroplating, physical / magnetron sputtering, evaporation, deposition, etc. The induction coil 50 may be a coil with any number of turns, and the number of turns of the induction coil 50 is not limited in this embodiment.

[0089] Optionally, in step S106 , a mask may be used to prepare a first conductive line layer 30 on the upper surface of the first through silicon via structure 201 , wherein the first conductive line layer 30 may be isolated from the semiconductor substrate 10 by an insulating material.

[0090] Optionally, in step S107 , a second conductive line layer 40 may be formed on the lower surfaces of the first TSV structure 201 and the second TSV structure 202 using a mask, wherein the second conductive line layer 40 may be isolated from the semiconductor substrate 10 by an insulating material.

[0091] In this embodiment, the first conductive layer 30 and the second conductive layer 40 respectively connect the upper and lower surfaces of the conductive pillars 2013 in the vertically distributed through-silicon via structure 20, thereby achieving metal interconnection and thus realizing signal transmission. For example, the first conductive layer 30 and the second conductive layer 40 can be copper, aluminum, or gold.

[0092] Optionally, in step S108, the antenna structure 2 can be fabricated above the inductor structure 1 having a through-silicon via structure using the same method as for fabricating the induction coil 50. Specifically, the antenna structure 2 can be fabricated above the inductor structure 1 having a through-silicon via structure using methods such as electroplating, physical / magnetron sputtering, evaporation, and deposition. In this embodiment, the antenna structure 2 and the inductor structure 1 are non-contact, facilitating the subsequent generation of an induced magnetic field on the antenna structure 2 under the excitation of the induced current.

[0093] Optionally, in steps S109 and S110, a physical spin coating method can be used to prepare a first isolation layer 60 on the upper surface of the semiconductor substrate 10, and a second isolation layer 70 on the lower surface of the semiconductor substrate 10. The first isolation layer 60 and the second isolation layer 70 can be any one or more of a silicon dioxide layer, a polyimide resin layer, etc., wherein the first isolation layer 60 and the second isolation layer 70 have good isolation effect.

[0094] Optionally, in step S20, an excitation current is applied to the inductor structure 1 having a through-silicon via structure. Optionally, the inductor structure 1 having a through-silicon via structure includes a port 1. Optionally, the port 1 can be provided on the second conductive layer 40. The port 1 is a lump port (lumped port) and can have a size of 2 μm×4 μm. The excitation frequency can be set to 300 GHz (near the resonant frequency), and the impedance can be set to 50 ohms.

[0095] Optionally, in step S30 , a scattering parameter is obtained based on the inductive coupling between the antenna structure 2 and the inductor structure 1 having a through-silicon via structure.

[0096] Among them, the scattering parameter, that is, the S parameter, is an important parameter in microwave transmission, wherein the scattering parameter includes: return loss and insertion loss, etc. Optionally, in this embodiment, whether there is a defect in the silicon through-hole via structure is mainly determined based on the insertion loss included in the scattering parameter. Specifically, the insertion loss can be obtained at port 2 in the antenna structure 2. Optionally, the shape and structure of port 2 and port 1 can be the same. Specifically, port 2 is a lump port (lump port) with a size of 2μm×4μm. The excitation solution frequency can be set to 300GHz (near the resonant frequency), and the impedance can be set to 50ohm.

[0097] In this embodiment, when an excitation current is applied to the inductive structure 1, inductive coupling can be formed between the antenna structure 2 and the inductive coil 50 by utilizing the fact that the antenna structure 2 and the inductive coil 50 are isolated from each other, have the same spiral shape, and are arranged correspondingly in the upper and lower parts. That is, under the excitation of the inductive current applied to the inductive structure 1, an induced magnetic field is generated around the antenna structure 2. By judging the distribution change of the induced magnetic field around the antenna structure 2, the coupling change between the antenna structure 2 and the inductive coil 50 can be judged, and the change in signal transmission performance can be intuitively compared, thereby judging whether there is a defect in the monitoring silicon via structure 20.

[0098] Optionally, in step S40 , it may be determined whether there are defects in the TSV structure 20 based on the scattering parameters.

[0099] Specifically, the corresponding scattering parameters of the antenna structure 2 can be used to determine whether the signal transmission performance of the TSV structure 20 has changed, for example, whether it has decreased. If it has decreased, it indicates that there is a defect in the TSV structure 20. For details, see Figures 5-7.

[0100] In an optional embodiment, referring to Figures 5-7, in step S40, whether there is a defect in the silicon via structure 20 can be determined based on the scattering parameters, including: obtaining a curve of the change of the scattering parameters with frequency; comparing the change curve with a target curve, where the target curve is a target change curve of the scattering parameters with frequency obtained by the defect monitoring structure of the defect-free silicon via structure under the excitation current; if the peak value of the change curve becomes smaller than the peak value of the target curve or shifts toward the small frequency direction, it is determined that there is a defect in the silicon via structure.

[0101] In this embodiment, when monitoring defects in a through-silicon-via structure, a defect monitoring structure of a defect-free through-silicon-via structure is obtained, and a target variation curve of the scattering parameter with frequency is obtained under an excitation current. Then, a defect monitoring structure of the through-silicon-via structure is determined, and a variation curve of the scattering parameter with frequency is obtained under an excitation current. The variation curve is compared with the target curve to determine whether the peak value of the variation curve becomes smaller than the peak value of the target curve; alternatively, the peak value of the variation curve is compared with the peak value of the target curve to determine whether it is shifted toward a lower frequency direction.

[0102] As an example, after determining that there are defects in the through silicon via structure, the method further includes:

[0103] If the peak value of the change curve becomes smaller than the peak value of the target curve, it is determined that the defects present in the silicon via structure include at least one of a void defect and a pinhole defect; if the peak value of the change curve is determined to be shifted toward a lower frequency direction compared to the peak value of the target curve, it is determined that the defects present in the silicon via structure include an open circuit defect.

[0104] Specifically, refer to Figures 5-6. If the peak value of the variation curve becomes smaller than the peak value of the target curve, it is determined that there is a defect in the TSV structure, wherein the defect includes at least one of a void defect and a pinhole defect. Figure 7 If the peak of the variation curve shifts toward a lower frequency compared to the peak of the target curve, an open circuit defect is determined to exist in the TSV structure. For a detailed description of various TSV defects, see below.

[0105] In this embodiment, please refer to FIG5. It should be noted that FIG5 includes Figure 5A and Figure 5B , Figure 5A The image in the lower left corner is an enlarged view of area 1, that is, Figure 5B It is an enlarged view of area 1 in 5A. Optionally, when a void defect (Void) exists in the through-silicon via structure, the resonant frequency is 303 GHz, which does not change, but the insertion loss (S21 parameter) decreases, and when the defect radius r increases from 0.5 μm to 1.5 μm, the S21 parameter decreases with the increase of the defect size; specifically, when the defect radius r increases from 0.5 μm to 1.5 μm with a step size of 0.5 μm, the S21 parameter decreases from -12.29 dB to -12.32 dB. This phenomenon is caused by the reduction of the internal working current of the inductor structure of the through-silicon via structure. Specifically, due to the existence of a current opposite to the current in the inductor structure generated in the void defect, the current in the inductor structure decreases. When the void defect radius r increases, the larger the defect size, the greater the reverse current induced inside the inductor structure, and the more obvious the reduction in the S21 parameter.

[0106] Optional, please refer to Figure 6, it should be noted that Figure 6 includes Figure 6A and Figure 6B , Figure 6A The image in the lower left corner is an enlarged view of area 1, that is, Figure 6B It is an enlarged view of area 1 in 6A. When a pinhole defect (Pinhole) exists in the through-silicon via structure, the resonant frequency is 303 GHz, which does not change, but the insertion loss (S21 parameter) decreases, and when the defect radius r increases from 0.8 μm to 2 μm, the S21 parameter decreases with the increase of the defect size; specifically, when the defect radius r increases from 0.8 μm to 2 μm with a step size of 0.6 μm, the S21 parameter decreases from -12.32 to -12.36 dB. Specifically, the reason for the change in the corresponding change curve when a pinhole defect exists in the through-silicon via structure can be referred to the reason for the change in insertion loss when a void defect exists in the through-silicon via structure, and will not be repeated here.

[0107] In this embodiment, please refer to Figure 7When an open defect (void) exists in the TSV structure, the resonant frequency changes from 303 GHz to a new resonant frequency of 173 GHz. The insertion loss (S21) peak also decreases from -9.56 dB to -9.9 dB. This phenomenon is caused by changes in capacitive coupling. Specifically, when an open defect exists in the TSV structure, the capacitance in the TSV structure decreases, resulting in a worse capacitive coupling effect, which in turn leads to a decrease in the S21 parameter. The S21 parameter decreases as the defect height h increases.

[0108] In this embodiment, before providing the defect monitoring structure of the TSV structure described in the above embodiment, the method further includes setting a distance between the antenna structure 2 and the inductor structure 1 having the TSV. Optionally, the distance between the antenna structure 2 and the inductor structure 1 having the TSV is 5 μm-30 μm.

[0109] In this embodiment, the antenna structure 2 can be fabricated above the inductor structure 1 having a through-silicon via structure by electroplating, physical / magnetron sputtering, evaporation, deposition, or the like. Specifically, the spacing between the antenna structure 2 and the inductor structure 1 having the through-silicon via is set to 5 μm-30 μm. For example, the spacing between the antenna structure 2 and the inductor structure 1 having the through-silicon via is 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, and 30 μm. Preferably, the spacing between the antenna structure 2 and the inductor structure 1 having the through-silicon via can be set to 5-20 μm. In this case, the energy interaction between the antenna structure 2 and the inductor structure 1 having the through-silicon via is large, facilitating subsequent monitoring of changes in the corresponding scattering parameters in the antenna structure 2. Furthermore, since the antenna structure 2 and the inductor structure 1 having the through-silicon via are non-contact, direct contact between the antenna structure 2 and the inductor structure 1 having the through-silicon via is avoided, reducing interference of the antenna structure 2 with the circuits in the inductor structure 1, allowing the circuits in the inductor structure 1 to operate normally.

[0110] Optionally, the distance between the antenna structure 2 and the inductor structure 1 having the through silicon via directly affects the coupling strength between the two. Figure 8 When the spacing between antenna structure 2 and inductor structure 1 with TSVs is set to 5μm, 10μm, 15μm, and 20μm, the S21 parameter varies from -6.8dB to -29dB. This indicates that the coupling strength between antenna structure 2 and inductor structure 1 with TSVs decreases as the spacing between them increases.

[0111] It should be noted that the insertion loss versus frequency curves corresponding to the various defects in the TSV structures in Figures 5-7, as well as Figure 8 In the figure, the curve of the variation of insertion loss with frequency at different distances between the antenna structure and the inductor structure with silicon vias is only an example. This embodiment does not limit the curve of the variation of insertion loss with frequency in Figures 5-8.

[0112] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0113] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A defect monitoring structure for a through silicon via structure, characterized in that: include: An inductor structure having a through-silicon via (TSV) structure comprises: a semiconductor substrate, a TSV structure, a first conductive line layer, a second conductive line layer, and an inductive coil; the TSV structure comprises a first TSV structure and a second TSV structure, each of the first TSV structure and the second TSV structure comprising a TSV, a dielectric layer, and a conductive pillar; the TSV is located within the semiconductor substrate and penetrates the semiconductor substrate along its thickness direction; the dielectric layer covers the sidewalls of the TSV; the conductive pillar is located within the TSV and fills the TSV; the first conductive line layer is located above the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars of the first TSV structure; the second conductive line layer is located below the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars in the first TSV structure and the conductive pillars in the second TSV structure; the inductive coil is located above the semiconductor substrate, insulated and isolated from the semiconductor substrate, and connected to the conductive pillars in the first TSV structure and the second TSV structure; The antenna structure is located above the inductor structure having the through silicon via structure and has a distance therebetween from the inductor structure having the through silicon via structure.

2. The defect monitoring structure of the through silicon via structure according to claim 1, characterized in that: The shape of the antenna structure is the same as that of the induction coil, and an orthographic projection of the antenna structure within the plane where the induction coil is located coincides with the induction coil.

3. The defect monitoring structure of the through silicon via structure according to claim 2, characterized in that: The shape of the antenna structure and the shape of the induction coil are both spiral.

4. The defect monitoring structure of the through silicon via structure according to claim 1, characterized in that: The inductor structure having through silicon vias further includes: a first isolation layer, located on the upper surface of the semiconductor substrate; the first wire layer and the induction coil are both located on the upper surface of the first isolation layer; a second isolation layer, located on the lower surface of the semiconductor substrate; and the second conductive line layer is located on the lower surface of the second isolation layer; The through silicon via also penetrates the first isolation layer and the second isolation layer along a thickness direction.

5. The defect monitoring structure of the through silicon via structure according to any one of claims 1 to 4, characterized in that: The distance between the antenna structure and the inductor structure having the through silicon via is 5 μm-30 μm.

6. A method for monitoring defects in a through silicon via structure, characterized in that: include: Providing a defect monitoring structure for a through silicon via structure according to any one of claims 1 to 5; Applying an excitation current to the inductor structure having the through silicon via structure; Obtaining a scattering parameter based on inductive coupling between the antenna structure and the inductive structure having the through-silicon via structure; It is determined whether there is a defect in the through silicon via structure based on the scattering parameter.

7. The defect monitoring method of a through silicon via structure according to claim 6, characterized in that: The scattering parameter includes insertion loss; and judging whether there is a defect in the through silicon via structure based on the scattering parameter includes: Obtaining a curve of the scattering parameter changing with frequency; Comparing the variation curve with a target curve, wherein the target curve is a target variation curve of the scattering parameter of a defect monitoring structure of a defect-free through silicon via structure as a function of frequency under the excitation current; If the peak value of the variation curve becomes smaller than the peak value of the target curve or shifts toward a lower frequency, it is determined that there is a defect in the through silicon via structure.

8. The defect monitoring method for a through silicon via structure according to claim 7, wherein: After determining that there are defects in the through silicon via structure, the method further includes: If the peak value of the change curve becomes smaller than the peak value of the target curve, it is determined that the defect existing in the silicon via structure includes at least one of a void defect and a pinhole defect; if it is determined that the peak value of the change curve shifts toward a small frequency direction compared to the peak value of the target curve, it is determined that the defect existing in the silicon via structure includes an open circuit defect.

9. The defect monitoring method for a through silicon via structure according to any one of claims 6 to 8, characterized in that: Before providing the defect monitoring structure of the through silicon via structure according to any one of claims 1 to 5, the method further comprises: setting a distance between the antenna structure and the inductor structure having the through silicon via.

10. The defect monitoring method of a through silicon via structure according to claim 9, characterized in that: The distance between the antenna structure and the inductor structure having the through silicon via is 5 μm-30 μm.

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