A low-walk-error laser pulse phase method receiving front-end system

Abstract

This invention discloses a laser pulse phase-based ranging system with low walking error, comprising a TIA circuit, a pulse amplification unit, a timing discrimination circuit, an RS latch circuit, and an ADC circuit. The output of the TIA circuit is connected to the pulse amplification unit, the output of the pulse amplification unit is connected to the timing discrimination circuit, and the output of the timing discrimination circuit is connected to the RS latch circuit and the ADC circuit. The pulse amplification circuit includes a differential amplification circuit and a post-amplifier circuit connected to the output of the differential amplification circuit. This invention proposes that the phase-based ranging section directly performs undersampling of the acquired analog pulse signal to a sine wave using an ADC, eliminating the need for a subsequent mixing and filtering circuit unit, thus simplifying the system circuitry and reducing power consumption. Furthermore, it proposes using the comparator delay to compensate for the walking error of pulses with different amplitudes, thereby reducing the walking error of pulses with different amplitudes and overcoming the negative impact of comparator delay on walking error.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a laser pulse phase method receiving front-end system with low walking error. Background Technology

[0002] Applying laser technology to ranging is a widely used method, and in recent years, much research has been conducted on related optoelectronic devices, ranging methods, and circuit systems. Because lidar ranging does not depend on the distance being measured or the user's experience, its ranging error is determined solely by the instrument itself. Therefore, laser ranging is not only of great significance for national defense applications but also plays an indispensable role in our daily lives. Furthermore, with the recent surge in deep learning and autonomous driving, lidar research has also become a popular area of ​​research.

[0003] Laser ranging methods mainly include pulse ranging and phase ranging. Pulse ranging systems primarily convert the laser's time of flight directly into distance information by acquiring the emitted and received pulse times. This method offers short ranging times and long distances, but its accuracy is relatively low. Phase ranging systems, on the other hand, convert the phase information between emitted and received sinusoidal signals into time information, and then into distance information. The advantage of this method is that it converts the time information of light into indirect, low-frequency phase information, thus simplifying backend processing and achieving higher ranging accuracy. However, its disadvantage is that it is limited by the signal frequency, resulting in a shorter ranging distance.

[0004] A typical phase-pulse ranging system usually includes a pulse generation circuit, a sine wave generation circuit, a laser emission channel, a laser receiving channel, a mixer circuit, a filter circuit, an ADC circuit, and an FPGA control unit. The pulse generation circuit generates the pulse signal, and the emission channel includes a laser emission driver and a laser emitter. The laser receiving channel includes a receiving photodiode, a TIA circuit, a pulse amplification circuit, and a time discrimination circuit. The mixer and filter unit circuit typically requires a large integrated circuit area and consumes a lot of power, which is detrimental to the miniaturization and integration of this phase-pulse ranging system.

[0005] Furthermore, in the laser receiving channel of the pulse phase method circuit, the square wave shaped by the comparator will cause a walking error due to the difference in pulse amplitude. A schematic diagram of the specific principle is shown below. Figure 8 As shown (comparator delay is not considered). However, the comparator also has a certain delay, which is related to the pulse amplitude: the smaller the pulse amplitude, the greater the pulse delay. The specific principle is as follows... Figure 9As shown, a typical leading-edge timing discrimination circuit will generate a larger timing discrimination error due to the superposition of its own pulse amplitude error and comparator delay error. This phase error caused by the walking error will also be mapped to the phase error of the final output sine wave, thus affecting the ranging accuracy. Therefore, how to reduce the walking error caused by different pulse amplitudes is a key problem we need to solve. Currently, the mainstream timing discrimination methods mainly include leading-edge timing discrimination, constant ratio timing method, and high-pass RC method. Among them, leading-edge timing discrimination has a simple structure but a large error; the constant ratio timing method achieves high ranging accuracy by delaying and attenuating the signal along one path and using the pulse triangle approximation principle to find the intersection of the two, but its structure is complex and it cannot achieve high accuracy when the signal is distorted, and it cannot completely solve the influence of comparator delay; the high-pass RC method uses pulse differentiation to transform the pulse peak point into a zero-crossing point. The advantage of this method is its simple implementation principle and high discrimination accuracy, but the disadvantage is that it requires a significant pulse signal peak and cannot overcome the influence of comparator delay. Summary of the Invention

[0006] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by the present invention is to provide a laser pulse phase method receiving front-end system with low walking error, so as to overcome the shortcomings of the prior art.

[0007] To achieve the above objectives, this invention provides a laser pulse phase method receiving front-end system with low walking error, including a TIA circuit, a pulse amplification unit, a timing discrimination circuit, an RS latch circuit, and an ADC circuit. The output of the TIA circuit is connected to the pulse amplification unit, the output of the pulse amplification unit is connected to the timing discrimination circuit, and the output of the timing discrimination circuit is connected to the RS latch circuit and the ADC circuit. The pulse amplification circuit includes a differential amplification circuit and a post-amplifier circuit connected to the output of the differential amplification circuit, wherein:

[0008] The TIA circuit converts the received current pulses into voltage signal pulses;

[0009] Differential amplifier circuits amplify weak voltage signals while converting single-ended signals into double-ended signals.

[0010] The post-amplifier circuit further amplifies the voltage signal;

[0011] The time-of-flight discrimination circuit aims to minimize the walking error caused by differences in pulse amplitude.

[0012] The RS latch circuit enables the acquisition of the rising edge of the received signal, thus facilitating backend data processing.

[0013] An ADC circuit implements the function of undersampling a sinusoidal signal by transmitting or receiving pulses, thereby converting it into a digital signal containing phase information.

[0014] Preferably, the ADC circuit is an 8-bit ADC circuit with an input sampling frequency of 15MHz and a sine wave signal to be sampled of 15.05MHz.

[0015] Preferably, the TIA circuit employs a voltage parallel negative feedback circuit, which includes a feedback resistor and a current-voltage amplifier circuit.

[0016] Preferably, the timing discrimination circuit includes a level shifting circuit, a comparator circuit with delay compensation, and a low-walking-error pulse generation logic unit, wherein:

[0017] The level shifting circuit is based on the principle of resistor voltage division to shift the positive level down and the negative voltage up, and then inputs the positive and negative levels to the comparator circuit with delay compensation.

[0018] The comparator circuit with delay compensation obtains a square wave pulse by comparing the level-shifted signal.

[0019] The low-walk-error pulse generation logic unit generates pulse square wave signals at the rising edge and falling edge of the low-walk-error pulse.

[0020] Preferably, the ADC circuit has two paths: a receiving ADC circuit and a transmitting ADC circuit. The input terminals of the receiving ADC circuit and the transmitting ADC circuit are connected to a sine wave generator circuit. The ADC circuit uses the transmitted pulse and the processed received pulse as the ADC input clock, and the sine wave signal generated by the sine wave generator circuit as the input sampled signal, thus converting the pulse signal with phase difference information into a sine wave digital signal with phase difference information.

[0021] The beneficial effects of this invention are:

[0022] 1. This invention abandons the mixing and filtering unit of the phase method part in the traditional pulse phase method ranging circuit, and directly uses the ADC circuit to undersample the input sine wave signal using the pulse input signal. This simplifies the system structure and circuit, and better realizes the miniaturization and integration of the circuit, thereby reducing the overall power consumption of the circuit.

[0023] 2. Currently, mainstream time identification methods mainly include leading-edge time identification, constant-ratio timing method, and high-pass RC method. Among them, leading-edge time identification has a simple structure but a large error; the constant-ratio timing method achieves high ranging accuracy by delaying and attenuating one signal path and using the pulse triangle approximation principle to find the intersection of the two, but its structure is complex and it fails to achieve high accuracy when the signal is distorted, and it cannot completely solve the influence of comparator delay; the high-pass RC method uses pulse differentiation to transform the pulse peak point into a zero-crossing point. This method has the advantages of simple implementation principle and high identification accuracy, but the disadvantages are that it requires a significant pulse signal peak and cannot overcome the influence of comparator delay. This invention innovatively proposes to directly compensate for the falling edge travel error of the pulse by utilizing the comparator delay error, and uses a low travel error generation logic to obtain a pulse square wave signal with a low travel error rising edge and a low travel error falling edge. The circuit is simple, has low requirements for the pulse signal shape, has high identification accuracy, and overcomes the influence of different comparator delays for different amplitudes compared to traditional rising-edge time identification circuits.

[0024] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a common pulse phase laser ranging system.

[0026] Figure 2 A schematic diagram of a phase-based laser undersampling phase detection method and device, which is a similar patent.

[0027] Figure 3 This is a schematic diagram of the overall system for pulse phase ranging proposed in this invention;

[0028] Figure 4 This is a schematic diagram of the analog receiving front-end (AFE) structure proposed in this invention;

[0029] Figure 5 This is a block diagram of the timing discrimination circuit proposed in this invention;

[0030] Figure 6 A simplified diagram illustrating the principle of ADC undersampling;

[0031] Figure 7 This is a schematic diagram of the waveform for comparator delay compensation of walking error;

[0032] Figure 8 Schematic diagram of travel error in pulse phase method circuit;

[0033] Figure 9 This is a schematic diagram illustrating the walking error principle when a comparator is present. Detailed Implementation

[0034] See Figure 1 This is a common system structure for laser pulse phase-based ranging. The system first generates a pulse signal using a transmitter driver. This pulse signal then drives a laser transmitter to emit a laser signal. After reflection from the target, a photodiode converts the received light signal into a current signal. This current signal is then converted into a voltage signal by a TIA (Transmitter Amplifier), and subsequently passes through a signal amplification and shaping circuit, which includes a voltage amplifier and a timing discrimination circuit. The signal can then be output through two channels: phase-based and pulse-based. In the phase-based section, the comparator output signal is first processed by a mixer and filter unit to produce a low-frequency sine wave signal. An ADC (Analog-to-Digital Converter) circuit then converts this low-frequency sine wave analog signal into a digital signal and transmits it to the FPGA. Similarly, the transmitter driver signal undergoes mixing and filtering to produce a low-frequency sine wave signal, which is then converted back to a digital signal by the ADC circuit and transmitted to the FPGA. In the pulse-based section, a timing unit directly times the time difference between the transmitted and received pulses and transmits this time difference signal to the FPGA.

[0035] See Figure 2 This is a schematic diagram of the phase-based laser undersampling phase detection method. Figure 2 The principle behind the phase-based laser ranging system is that a sinusoidal signal modulates the transmission drive to emit a laser signal carrying sinusoidal information. Then, a photodiode receives this laser sinusoidal signal. The pulse signal generated by the crystal oscillator undersamples the transmitted and received signals carrying phase information, thereby converting the phase difference information between the transmitted and received signals into time information to complete the ranging.

[0036] See Figure 3 The diagram shows the overall structure of the proposed pulse phase method. First, the laser emission driver emits a narrow pulse to drive the laser emission tube to emit laser light. The emission frequency of this laser light is the same as the pulse frequency generated by the laser emission driver. At the same time, the pulse signal generated by the emission driver is input to the Vstart and Vdrive signals in the analog receiving front-end chip for processing. After the pulse signal is reflected by the target object, it is first converted into a current signal Ipulse by the APD avalanche photodiode. Then, the Ipulse signal is input to the proposed analog receiving front-end circuit. The Vsin signal is an externally generated sine wave signal, mainly generated by the signal generator. Finally, the digital signals of the three ports output by the AFE are sent to the FPGA chip to complete the digital information processing.

[0037] See Figure 4The above is a schematic diagram of the overall structure of the internal AFE chip described in this invention. This invention mainly includes four input ports and three output ports. The input ports mainly include Ipulse, Vsin, Vdrive, and Vstart. The laser light can be converted from an optical signal to a current signal Ipulse by the photodiode at the receiving end. Vsin represents the ADC sampling signal. Vdrive represents the transmission signal drive pulse. The frequency of this transmission drive pulse signal is theoretically the same as the frequency of the receiving pulse, both being 15MHz. However, due to the time difference between the transmission and receiving signals, the initial phases between the two pulses are different. The Vstart signal is one of the input terminals of the RS latch. This voltage signal is the same as the Vdrive signal and represents the transmission signal input by the pulse method.

[0038] The Figure 4 The characterization system mainly consists of a TIA circuit, a differential amplifier circuit, a post-amplifier circuit, a timing discrimination circuit, an RS latch circuit, and an ADC sampling circuit. The TIA circuit converts the received current pulse into a voltage signal pulse; the differential amplifier circuit amplifies the weak voltage signal and converts the single-ended signal into a double-ended signal; the post-amplifier circuit further amplifies the voltage signal; the timing discrimination circuit minimizes the walking error caused by different pulse amplitudes; the RS flip-flop acquires the rising edge of the received signal to facilitate backend data processing; and the ADC sampling circuit uses the transmitted or received pulses to undersample the sinusoidal signal, converting it into a digital signal containing phase information. Figure 4 In this circuit, there are two ADC circuits: a receiving ADC circuit and a transmitting ADC circuit. The input terminals of the receiving ADC circuit and the transmitting ADC circuit are connected to a sine wave generator circuit. The ADC circuit uses the transmitted pulse and the processed received pulse as the ADC input clock, and the sine wave signal generated by the sine wave generator circuit as the input sampled signal, thus converting the pulse signal with phase difference information into a sine wave digital signal with phase difference information. Figure 4 In this diagram, Vdrive represents the transmitted pulse signal, REd0-REd7 represents the digital signal output of the received sine wave, and TRd0-TRd7 represents the digital signal output of the transmitted sine wave. REd0-REd7 and TRd0-TRd7 are ultimately input to the FPGA for digital processing to distinguish the phase difference between the received and transmitted signals.

[0039] The Figure 5To establish the circuit block diagram for real-time identification, the differential pulse signal is first shifted through a level shifter circuit to shift the positive voltage down and the negative voltage up. Then, the positive and negative levels are input to the comparator circuit to improve the comparator's anti-interference capability. The comparator circuit with delay compensation mainly obtains a square wave pulse by comparing the level-shifted signal. This circuit primarily utilizes the comparator's delay error to compensate for the falling edge travel error. The low travel error generation logic unit mainly generates pulse square wave signals for both the rising and falling edges of the low travel error.

[0040] The Figure 6 This is a simplified diagram of the ADC undersampling principle. As we can see from the diagram, the ADC circuit uses the received signal pulse (transmitted signal pulse) as the sampling signal and the blue sine wave signal as the sampled signal. Ultimately, it can convert the time-of-flight signal between the high-frequency transmitted and received pulses into the phase difference signal between the yellow and green sine waves. This is consistent with the previous method of mixing and filtering to convert the signal into a low-frequency sine wave analog signal, and then using an ADC to convert the analog signal into a digital signal.

[0041] The Figure 7 The diagram illustrates the waveform of comparator delay compensation for walking error. It clearly shows that using the rising edge for identification results in a superposition relationship between the pulse walking error and the comparator's delay error. By automatically adjusting the gate-source voltage difference of the current-discharging transistor in the comparator latch section, the falling edge delay of the comparator can be controlled. This ensures that the pulse walking error and the comparator's delay error mutually compensate for each other, thus obtaining low walking error timing identification. The low walking error generation unit logic can then generate pulse square wave signals for both the rising and falling edges of the low walking error.

[0042] In summary, this invention proposes a receiver front-end system structure based on laser pulse phase method ranging, mainly composed of a TIA circuit, a pulse amplification unit, a time discrimination circuit, an RS latch circuit, and an ADC circuit. The phase method part mainly includes the TIA circuit, pulse amplification unit, time discrimination circuit, and ADC circuit. The pulse method part mainly includes the TIA circuit, pulse amplification unit, time discrimination circuit, and RS latch circuit.

[0043] The ADC circuit uses an 8-bit ADC with an input sampling frequency of 15MHz and a sine wave signal to be sampled at 15.05MHz. The TIA circuit mainly employs a voltage parallel negative feedback circuit, which includes a feedback resistor and a current-voltage amplifier circuit. The pulse amplifier circuit mainly includes a fully differential amplifier circuit and a post-amplifier circuit. This receiver front-end system circuit does not require mixing and filtering the input signal with a sine wave before sampling the difference frequency with the ADC circuit to obtain a 50kHz sine wave digital signal. Instead, it directly uses the ADC circuit to undersample the sine wave signal using the input pulse signal to obtain a 50kHz sine wave digital signal. The timing discrimination circuit mainly includes a level shifting circuit, a comparator circuit, and a low-travel-error generation logic unit. The level shifting circuit mainly uses the resistor voltage divider principle to shift the positive voltage down and the negative voltage up, and then inputs the positive and negative levels to the comparator circuit to improve the comparator's anti-interference capability. The comparator circuit mainly obtains a square wave pulse by comparing the level-shifted signal. The low-walk-error generation logic unit mainly obtains the pulse square wave signal at the rising and falling edges of the low-walk-error signal. The RS latch mainly acquires the rising edge of the received pulse arrival time.

[0044] contrast Figure 1 and Figure 4 The difference is clear: the proposed circuit differs from the previous method of mixing pulse signals and sine wave signals, filtering the difference frequency to obtain a low-frequency sine wave signal, and then converting the analog sine wave signal into a digital signal through an ADC. Instead, it directly uses the pulse signal as the sampling signal and the sine wave signal as the sampled signal to obtain a corresponding digital sine wave signal containing phase information through undersampling. This simplifies the system circuit structure and reduces the power consumption of the system circuit.

[0045] contrast Figure 2 and Figure 4 Differences in ranging principles Figure 2 The method in this context relies solely on the phase difference information of a sine wave to complete ranging, with both the transmitted and received signals being sine wave signals; while the aforementioned... Figure 4In pulse phase laser ranging, both the transmitted and received signals are pulse signals. Compared to sinusoidal signals, pulse signals have stronger anti-interference capabilities, can achieve longer ranging distances, and require lower power from the transmitting circuit. Using the transmitted and received signals as the ADC clock signals, the pulse method first calculates the coarse distance based on the time interval between transmission and reception, which is equivalent to the portion greater than half the wavelength. For example, a 15MHz light pulse signal with a light speed of 3*10^8 m / s has a wavelength of 3*10^8 / 15000000 = 20m. Considering that the light is first emitted to the target and then reflected back, 10m is the fine distance measurement portion of the phase method. If the coarse distance is 35m, then 30m is taken as the coarse measurement, and the remaining distance (whether it is 5m or not) is determined by the phase method. Therefore, the proposed laser pulse phase ranging method achieves a longer ranging distance without reducing the ranging accuracy compared to the phase laser ranging method.

[0046] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A laser pulse phase method receiving front-end system with low walking error, characterized in that... It includes a TIA circuit, a pulse amplification unit, a timing discrimination circuit, an RS latch circuit, and an ADC circuit. The output of the TIA circuit is connected to the pulse amplification unit, the output of the pulse amplification unit is connected to the timing discrimination circuit, and the output of the timing discrimination circuit is connected to the RS latch circuit and the ADC circuit. The pulse amplification unit includes a differential amplification circuit and a post-amplifier circuit connected to the output of the differential amplification circuit, wherein: The TIA circuit converts the received current pulses into voltage signal pulses; Differential amplifier circuits amplify weak voltage signals while converting single-ended signals into double-ended signals. The post-amplifier circuit further amplifies the voltage signal; The time-of-flight discrimination circuit aims to minimize the walking error caused by differences in pulse amplitude. The RS latch circuit enables the acquisition of the rising edge of the received signal, thus facilitating backend data processing. The ADC circuit implements the function of undersampling a sinusoidal signal by transmitting or receiving pulses, thereby converting it into a digital signal containing phase information; The TIA circuit employs a voltage parallel negative feedback circuit, which includes a feedback resistor and a current-voltage amplifier circuit. The timing discrimination circuit includes a level shifting circuit, a comparator circuit with delay compensation, and a low-walking-error pulse generation logic unit, wherein: The level shifting circuit is based on the principle of resistor voltage division to shift the positive level down and the negative voltage up, and then inputs the positive and negative levels to the comparator circuit with delay compensation. The comparator circuit with delay compensation obtains a square wave pulse by comparing the level-shifted signal. The low-walk-error pulse generation logic unit generates pulse square wave signals at the rising edge and falling edge of the low-walk-error pulse.

2. The laser pulse phase method receiving front-end system with low walking error as described in claim 1, characterized in that: The ADC circuit is an 8-bit ADC circuit with an input sampling frequency of 15MHz and a sine wave signal to be sampled of 15.05MHz.

3. The laser pulse phase method receiving front-end system with low walking error as described in claim 1, characterized in that: The ADC circuit has two paths: a receiving ADC circuit and a transmitting ADC circuit. The input terminals of the receiving ADC circuit and the transmitting ADC circuit are connected to a sine wave generator circuit. The ADC circuit uses the transmitted pulse and the processed received pulse as the ADC input clock, and the sine wave signal generated by the sine wave generator circuit as the input sampled signal, thus converting the pulse signal with phase difference information into a sine wave digital signal with phase difference information.

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