LDO circuit topology against gamma transient irradiation effect

Abstract

The application discloses a kind of LDO circuit topological structure of anti gamma transient irradiation effect, including voltage reference, error amplifier, output drive circuit, PMOS power regulating tube P1, NMOS transistor N1 and feedback resistance;Voltage reference is connected with the opposite phase end of error amplifier, the output end of error amplifier is connected with the input end of output drive circuit, the output end of output drive circuit is connected with the gate of PMOS power regulating tube P1, the source of PMOS power regulating tube P1 is connected with input node V IN , the drain of PMOS power regulating tube P1 is connected with output node V OUT , the gate of NMOS transistor N1 is connected with input node V IN , the drain of NMOS transistor N1 is connected with output node V OUT , the source of NMOS transistor N1 is connected with the noninverting terminal of error amplifier through feedback resistance.The application can reduce the disturbance amplitude of LDO output voltage when suffering gamma transient irradiation and the recovery time of output voltage after irradiation.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic component anti-radiation reinforcement, and relates to improvement of the anti-gamma transient irradiation effect capability of a power management integrated circuit and a circuit reinforcement topology structure, in particular to an LDO circuit topology structure for resisting gamma transient irradiation effects. BACKGROUND

[0002] Gamma-ray pulse (gamma dose rate) generated by nuclear explosion can cause semi-permanent or permanent damage or even failure of electronic components in a nuclear radiation environment. The irradiation damage mechanism is that under the irradiation of gamma-ray pulse (gamma dose rate), the reverse-biased PN junction inside the electronic component will generate a transient photocurrent; when this current is large enough, a transient irradiation effect will be generated, thereby causing irradiation damage of the electronic component, and further causing transient disturbance or permanent damage of the electronic system. Domestic and foreign literature research shows that in order to improve the anti-gamma transient irradiation effect capability of bipolar electronic components, diode shunt, diode clamping, negative feedback shunt and emitter resistance negative feedback circuit topologies have been proposed to limit the photocurrent caused by gamma transient irradiation effect. Since the above topologies are mainly proposed for bipolar integrated circuits, they are not very suitable for CMOS integrated circuits. Low-dropout regulator (LDO) is widely used in various electronic devices and electronic systems due to its high precision, small ripple, low power consumption and simple use. Early LDOs were designed using bipolar technology, but with the development of microelectronic technology, CMOS technology has become the mainstream technology for integrated circuit product design. High-performance LDOs also use CMOS technology, so it is necessary to study the circuit topology structure for improving the anti-gamma transient irradiation effect of LDO circuits based on CMOS technology design.

[0003] Under the gamma transient high dose rate irradiation, the secondary photocurrent is generated in the CMOS device. This is due to the photocurrent rising of the isolation junction, the source junction or the drain junction reaching the forward bias, and thus causing the parasitic vertical transistor to turn on. In this case, the initial photocurrent is amplified. The amplified current is the secondary photocurrent. It can cause the power current to change suddenly. Therefore, the gamma transient irradiation effects of the integrated circuits designed based on the CMOS process usually mainly include the transient disturbance, the latch-up and the burnout. Since the advanced CMOS process adopts the process measures for preventing the latch-up, and the anti-radiation reinforcement design is performed on the layout design, the latch-up effect is rarely observed in the integrated circuits designed based on the CMOS process when the integrated circuits are subjected to the gamma transient irradiation. The gamma transient irradiation effect mainly shows the voltage transient disturbance. The gamma transient irradiation test results of multiple varieties of the LDO circuits designed based on the CMOS process also show that during the transient irradiation, the output voltage of the LDO is disturbed at the irradiation moment, the disturbance time lasts for about several hundred microseconds to several milliseconds, then the output voltage is gradually stabilized, but the function is not normal; the power current is also disturbed and changed; after the circuit is powered off and then powered on again, the function is restored to normal, and the latch-up phenomenon and the permanent damage are not observed. The actual problem is that when the LDO is used as the board-level power supply, the fluctuation lasting for several hundred microseconds or even milliseconds will have an adverse effect on the load carried by the LDO, and finally can cause the catastrophic failure of the electronic equipment, so it is necessary to reduce the disturbance amplitude of the high-performance LDO when the LDO is subjected to the gamma transient irradiation and the output voltage recovery time after the irradiation. SUMMARY

[0004] In view of the problem that the existing anti-gamma transient irradiation effect reinforcement circuit topology based on the bipolar process cannot solve the gamma transient irradiation effect problem of the LDO circuit designed based on the CMOS process, the application provides an LDO circuit topology capable of effectively reducing the disturbance amplitude of the output voltage of the LDO designed based on the CMOS process when the LDO is subjected to the gamma transient irradiation and the output voltage recovery time after the irradiation.

[0005] The application is achieved by the following technical scheme.

[0006] The LDO circuit topology comprises a voltage reference, an error amplifier, an output driving circuit, a PMOS power adjusting tube P1, an NMOS transistor N1 and a feedback resistor.

[0007] The voltage reference is connected with the inverting terminal of the error amplifier, the output end of the error amplifier is connected with the input end of the output driving circuit, the output end of the output driving circuit is connected with the gate of the PMOS power adjusting tube P1, the source of the PMOS power adjusting tube P1 is connected with the input node V IN , the drain of the PMOS power adjusting tube P1 is connected with the output node V OUTConnect, NMOS transistor N1 gate and input node V IN Connect, NMOS transistor N1 drain and output node V OUT Connect, NMOS transistor N1 source is connected with the positive terminal of error amplifier through feedback resistance.

[0008] Preferably, the feedback resistance comprises feedback resistance R1 and feedback resistance R2; the source of NMOS transistor N1 is connected with one end of feedback resistance R1, the other end of feedback resistance R1 is connected with one end of feedback resistance R2 and the positive terminal of error amplifier, and the other end of feedback resistance R2 is grounded.

[0009] Preferably, the circuit topology for compensating the gate photoelectric current of PMOS power adjusting tube P1 is further included.

[0010] Further, the circuit topology for compensating the gate photoelectric current of PMOS power adjusting tube P1 comprises PMOS transistor P2, NMOS transistor N2, transistor Q1, resistance R3 and resistance R4.

[0011] The source of PMOS transistor P2 and one end of resistance R3 are both connected with input node V IN Connect, PMOS transistor P2 gate and the other end of resistance R3, one end of resistance R4 and the source of NMOS transistor N2 are connected, the drain of PMOS transistor P2 is connected with the drain of NMOS transistor N2 and the gate of PMOS transistor P1, the emitter of transistor Q1 is connected with the other end of resistance R3, the gate of PMOS transistor P1, one end of resistance R4 and the source of NMOS transistor N2, the base of transistor Q1 is connected with the other end of resistance R4, the collector of transistor Q1 is grounded, and the gate of NMOS transistor N2 is grounded.

[0012] Further, the drain area of PMOS transistor P2 is equal to the drain area of NMOS transistor N2.

[0013] Further, the gate length of PMOS transistor P2 is equal to the gate length of NMOS transistor N2, and the width ratio is 2:1.

[0014] Further, the gate length of PMOS transistor P2 is equal to the gate length of PMOS power adjusting tube P1, and the width ratio is 1:10.

[0015] Further, the gate length of NMOS transistor N2 is equal to the gate length of NMOS transistor N1, and the width ratio is 1:10.

[0016] Preferably, the drain area of PMOS power adjusting tube P1 is equal to the drain area of NMOS transistor N1. Compared with the prior art, the present application has the following beneficial effects:

[0017] The application provides a novel anti-gamma transient irradiation circuit topology of a power management integrated circuit suitable for an LDO circuit or a structure similar circuit designed based on a CMOS process, which adds an NMOS tube for compensating a photoelectric current of a PMOS power adjusting tube between an output feedback resistor and an output of a classical LDO circuit, a photoelectric current generated by the PMOS power adjusting tube P1 in a gamma transient irradiation effect is flowed out of the output node V OUT , and a photoelectric current generated by the NMOS tube N1 in the gamma transient irradiation effect is flowed into the output node V OUT , so that when the total photoelectric current of the drain of the PMOS power adjusting tube P1 and the NMOS tube N1 is close to matching, a transient output voltage caused by the gamma transient irradiation effect can be greatly reduced, and the disturbance amplitude of the output voltage of the LDO designed based on the CMOS process when subjected to the gamma transient irradiation and the recovery time of the output voltage after irradiation are effectively reduced.

[0018] Further, the application adds a photoelectric current gate compensation circuit topology at the gate of the PMOS power adjusting tube, when the photoelectric current generated in the gamma transient irradiation effect reaches a certain order of magnitude, the transistor Q1 is turned on, the gate potential of the PMOS tube P2 is pulled down, the output is high, the gate potential of the PMOS power adjusting tube P1 is increased, the output current is reduced, and thus the disturbance amplitude of the transient output voltage caused by the gamma transient irradiation effect is greatly reduced, and the disturbance amplitude of the output voltage of the LDO designed based on the CMOS process when subjected to the gamma transient irradiation and the recovery time of the output voltage after irradiation are further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a typical LDO circuit topology structure diagram.

[0020] Figure 2 It is a typical LDO circuit topology structure diagram using a PMOS power adjusting tube.

[0021] Figure 3 It is an LDO circuit topology structure diagram with a compensation NMOS.

[0022] Figure 4 It is an LDO circuit topology structure diagram with a compensation NMOS and a gate compensation.

[0023] Figure 5 The output voltage waveform diagram of the LDO circuit of the present application in a gamma transient irradiation test.

[0024] Figure 6 The output voltage waveform of the embodiment 2 of the present application in a gamma transient irradiation test. DETAILED DESCRIPTION

[0025] In order to further understand the present application, the present application is described below in combination with embodiments, which are only used to further explain the features and advantages of the present application, and are not used to limit the claims of the present application.

[0026] The topology structure of a typical LDO circuit is shown in Figure 1 The power device in the topology structure of a modern mainstream LDO circuit adopts a PMOS power adjusting tube, as shown in Figure 2 It mainly includes a voltage reference, an error amplifier, an output driving circuit, a power device (output adjusting tube) and a sampling resistor, etc. After the LDO circuit is powered on, the reference voltage source is started to generate a precise reference voltage V REF , which is input to the inverting terminal of the error amplifier. The sampling resistor network divides the output voltage V OUT to obtain a feedback voltage, and feeds it into the non-inverting terminal of the error amplifier. The difference between the reference voltage and the feedback voltage is amplified by the error amplifier, and then drives the power device through the output driving circuit, so as to control the output voltage of the voltage regulator by changing the conduction of the power device, i.e. the PMOS power adjusting tube. When the feedback voltage is less than the reference voltage, the output of the error amplifier controls the PMOS power adjusting tube to flow a larger current, so that the output voltage V OUT rises, and vice versa.

[0027] Embodiment 1

[0028] The topology structure of the LDO circuit of the present application against gamma transient irradiation effect is shown in Figure 3 It is based on the typical LDO circuit topology structure shown in Figure 2 which adopts a PMOS power adjusting tube, and an NMOS transistor N1 for compensating the photoelectric current generated by the PMOS power adjusting tube P1 is added. The transistor N1 is inserted between the feedback resistor R1 and the drain of the PMOS power adjusting tube P1, and also between the feedback resistor R1 and the output V OUT .

[0029] Specifically, the LDO circuit topology of the present application comprises a voltage reference, an error amplifier, an output driving circuit, a PMOS power adjusting tube P1, an NMOS transistor N1, a feedback resistor R1 and a feedback resistor R2. The voltage reference is connected with the inverting terminal of the error amplifier, the output terminal of the error amplifier is connected with the input terminal of the output driving circuit, the output terminal of the output driving circuit is connected with the gate of the PMOS power adjusting tube P1, the source of the PMOS power adjusting tube P1 is connected with the input node V IN , the drain of the PMOS power adjusting tube P1 is connected with the output node V OUT , the gate of the NMOS transistor N1 is connected with the input node V IN , the drain of the NMOS transistor N1 is connected with the output node V OUT , the source of the NMOS transistor N1 is connected with one end of the feedback resistor R1, the other end of the feedback resistor R1 is connected with one end of the feedback resistor R2 and the non-inverting terminal of the error amplifier, and the other end of the feedback resistor R2 is grounded.

[0030] The drain areas of the PMOS power adjusting tube P1 and the NMOS transistor N1 need to be equal; the gate of the NMOS transistor N1 is connected with V IN , and is kept in an always-on state.

[0031] The working principle is that the photoelectric current generated by the PMOS power adjusting tube P1 in the gamma transient irradiation effect is flowed out of the output node V OUT , while the photoelectric current generated by the NMOS transistor N1 in the gamma transient irradiation effect is flowed into the output node V OUT , so when the total photoelectric current of the drains of the PMOS power adjusting tube P1 and the NMOS transistor N1 is close to matching, the transient output voltage caused by the gamma transient irradiation effect can be greatly reduced.

[0032] Embodiment 2

[0033] As shown in Figure 4 , on the basis of embodiment 1, the present application further proposes a circuit topology structure for compensating the photoelectric current of the gate of the PMOS power adjusting tube P1, which is composed of a PMOS transistor P2, an NMOS transistor N2, a transistor Q1, a resistor R3 and a resistor R4.

[0034] The LDO circuit topology structure of the present embodiment, specifically, comprises a voltage reference, an error amplifier, an output driving circuit, a PMOS power adjusting tube P1, an NMOS transistor N1, a feedback resistor R1, a feedback resistor R2, a PMOS transistor P2, an NMOS transistor N2, a transistor Q1, a resistor R3 and a resistor R4.

[0035] The voltage reference is connected to the inverting terminal of the error amplifier, the output terminal of the error amplifier is connected to the input terminal of the output driving circuit, the output terminal of the output driving circuit is connected to the gate of the PMOS power regulating tube P1, the source of the PMOS power regulating tube P1 is connected to the input node V IN , the drain of the PMOS power regulating tube P1 is connected to the output node V OUT , the gate of the NMOS transistor N1 is connected to the input node V IN , the drain of the NMOS transistor N1 is connected to the output node V OUT , the source of the NMOS transistor N1 is connected to one end of the feedback resistor R1, the other end of the feedback resistor R1 is connected to one end of the feedback resistor R2 and the non-inverting terminal of the error amplifier, and the other end of the feedback resistor R2 is grounded.

[0036] The source of the PMOS transistor P2 is connected to one end of the resistor R3 and the input node V IN , the gate of the PMOS transistor P2 is connected to the other end of the resistor R3, one end of the resistor R4 and the source of the NMOS transistor N2, the drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N2 and the gate of the PMOS power regulating tube P1, the emitter of the transistor Q1 is connected to the other end of the resistor R3, the gate of the PMOS power regulating tube P1 and the source of the NMOS transistor N2, the base of the transistor Q1 is connected to the other end of the resistor R4, the collector of the transistor Q1 is grounded, and the gate of the NMOS transistor N2 is grounded.

[0037] The drain areas of the PMOS transistor P2 and the NMOS transistor N2 are equal. The gate lengths of the PMOS transistor P2 and the NMOS transistor N2 are equal, and the width ratio is 2:1; the gate lengths of the PMOS transistor P2 and the PMOS power regulating tube P1 are equal, and the width ratio is 1:10; the gate lengths of the NMOS transistor N2 and the NMOS transistor N1 are equal, and the width ratio is 1:10.

[0038] The working principle is: set the resistance R4 to a suitable resistance value, so that the voltage value between the two ends is less than the voltage threshold value that makes the transistor Q1 open, so in the normal state the transistor Q1 does not open. The gate of the NMOS transistor N2 is grounded, and in the normal state the NMOS transistor N2 does not open. The upper end of the resistor R3 is connected to V IN , and the lower end is connected to the gate of the PMOS transistor P2 and the emitter of the transistor Q1. The gate of the PMOS transistor P2 is connected to the lower end of the resistor R3, and its potential is high, so in the normal state the PMOS transistor P2 does not open. When the photoelectric current generated in the gamma transient irradiation effect reaches a certain order of magnitude, the transistor Q1 opens, pulling down the gate potential of the PMOS transistor P2, and its output is high, which increases the gate potential of the PMOS power regulating tube P1 and reduces its output current, thereby greatly reducing the transient output voltage disturbance amplitude caused by the gamma transient irradiation effect.

[0039] Gamma transient irradiation test verification:

[0040] The gamma transient irradiation test of the LDO circuit topology uses a dynamic biasing method, and is connected to a typical application. The test conditions are as follows: the host charging voltage is 41 kV, the average energy is 1.5 MeV, the pulse width is 25.5 ns, the dose rate is 1x10 11 rad(Si) / s, and the dose uncertainty is 14.2%.

[0041] The output voltage waveform of the LDO circuit not using the application during the gamma transient irradiation test is as shown in Figure 5 Figure 5 1, 2 and 3 are respectively the output voltage waveforms of the output voltage of the LDO circuit not using the application topology before, at and after zero power-on during the gamma transient irradiation. It can be seen that: when the LDO circuit not using the application topology is subjected to gamma transient irradiation, the output voltage is first transiently disturbed at zero time, then the output voltage sharply rises and gradually decreases, and no recovery is seen within 800 μs; after re-powering on, the circuit output is normal, indicating that although the circuit has been latched, it has not caused permanent damage; the output rises after disturbance at zero time because the transient radiation generates a transient photoelectric current inside the circuit, leading to the failure of the circuit function, resulting in the gradual decrease of the output voltage.

[0042] The output voltage waveform of the LDO circuit topology of the embodiment 2 of the application during the gamma transient irradiation test is as shown in Figure 6 During the gamma transient irradiation process of the designed reinforced LDO sample circuit, the output voltage is transiently disturbed at zero time, the disturbance time is less than 100 μs, and then the output voltage returns to normal, and the circuit function is normal. The gamma transient irradiation test verifies the effectiveness of the application.​

Claims

1. An LDO circuit topology structure resistant to gamma transient radiation effects, characterized in that: The invention comprises a voltage reference, an error amplifier, an output drive circuit, a PMOS power adjustment tube P1, an NMOS transistor N1 and a feedback resistor, and a circuit topology structure for compensating for a gate photocurrent of the PMOS power adjustment tube P1; The voltage reference is connected to the inverting terminal of the error amplifier, the output terminal of the error amplifier is connected to the input terminal of the output drive circuit, the output terminal of the output drive circuit is connected to the gate of the PMOS power adjustment tube P1, and the source of the PMOS power adjustment tube P1 is connected to the input node V IN Connect the drain of the PMOS power regulator P1 to the output node V OUT Connect the gate of NMOS transistor N1 to the input node V IN Connect the drain of NMOS transistor N1 to the output node V OUT The source of the NMOS transistor N1 is connected to the positive terminal of the error amplifier through a feedback resistor; The circuit topology for compensating the gate photocurrent of the PMOS power adjustment tube P1 includes a PMOS transistor P2, an NMOS transistor N2, a transistor Q1, a resistor R3 and a resistor R4; The source of the PMOS transistor P2 and one end of the resistor R3 are both connected to the input node V IN The gate of the PMOS transistor P2 is connected to the other end of the resistor R3, one end of the resistor R4 and the source of the NMOS transistor N2. The drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N2 and the gate of the PMOS transistor P1. The emitter of the transistor Q1 is connected to the other end of the resistor R3, the gate of the PMOS transistor P2, one end of the resistor R4 and the source of the NMOS transistor N2. The base of the transistor Q1 is connected to the other end of the resistor R4. The collector of the transistor Q1 is grounded, and the gate of the NMOS transistor N2 is grounded.

2. The LDO circuit topology structure for resisting gamma transient radiation effect according to claim 1, characterized in that: The feedback resistor includes a feedback resistor R1 and a feedback resistor R2; the source of the NMOS transistor N1 is connected to one end of the feedback resistor R1, the other end of the feedback resistor R1 is connected to one end of the feedback resistor R2 and the non-inverting end of the error amplifier, and the other end of the feedback resistor R2 is grounded.

3. The LDO circuit topology structure resistant to gamma transient radiation effect according to claim 1, characterized in that: The drain area of ​​the PMOS transistor P2 is equal to the drain area of ​​the NMOS transistor N2.

4. The LDO circuit topology structure resistant to gamma transient radiation effect according to claim 1, characterized in that: The gate lengths of the PMOS transistor P2 and the NMOS transistor N2 are equal, and the width ratio thereof is 2:

1.

5. The LDO circuit topology structure resistant to gamma transient radiation effect according to claim 1, characterized in that: The gate lengths of the PMOS transistor P2 and the PMOS power adjustment tube P1 are equal, and the width ratio thereof is 1:

10.

6. The LDO circuit topology structure resistant to gamma transient radiation effect according to claim 1, characterized in that: The gate lengths of the NMOS transistor N2 and the NMOS transistor N1 are equal, and the width ratio thereof is 1:

10.

7. The LDO circuit topology structure resistant to gamma transient radiation effect according to claim 1, characterized in that: The drain area of ​​the PMOS power adjustment tube P1 is equal to the drain area of ​​the NMOS transistor N1.

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