A bandgap reference circuit

Abstract

The present invention discloses a bandgap reference circuit, comprising: a startup circuit connected to an external power supply for generating a startup current; a multi-stage temperature compensation circuit connected to the external power supply and comprising multiple cascaded temperature compensation circuits; and a reference circuit comprising a generation circuit and a regulation output circuit. The generation circuit is connected to the startup circuit to operate under the action of the startup current and transmit a first output voltage generated by the external power supply to the multi-stage temperature compensation circuit, so that the multiple cascaded temperature compensation circuits compensate for the first output voltage. The regulation output circuit is connected to the multi-stage temperature compensation circuit to output a reference voltage based on the compensated first output voltage. In the bandgap reference circuit of the present invention, by cascading multiple temperature compensation circuits, multi-stage compensation can be achieved, thereby improving the accuracy of the reference voltage output by the regulation output circuit.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more particularly to a bandgap reference circuit. Background Art

[0002] Bandgap reference circuits are widely used in analog circuits, primarily to provide reference voltages for power management chips and data conditioning output circuits. In practical applications, some systems require high reference voltage accuracy. However, traditional bandgap reference circuits cannot compensate for the logarithmic term in the negative temperature voltage inherent in transistors, limiting the accuracy of the reference voltage. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a bandgap reference circuit which can improve the accuracy of the reference voltage.

[0004] In order to solve the above technical problems, the present invention provides a bandgap reference circuit, comprising:

[0005] A starting circuit, connected to an external power supply, for generating a starting current;

[0006] a multi-stage temperature compensation circuit connected to an external power supply, comprising a plurality of cascaded temperature compensation circuits;

[0007] The reference circuit includes a generating circuit and an adjusting output circuit. The generating circuit is connected to the starting circuit to operate under the action of the starting current and transmits a first output voltage generated according to an external power supply to a multi-stage temperature compensation circuit so that multiple cascaded temperature compensation circuits compensate for the first output voltage. The adjusting output circuit is connected to the multi-stage temperature compensation circuit to output a reference voltage according to the compensated first output voltage.

[0008] A further technical solution is as follows: each of the temperature compensation circuits includes a ninth capacitor, a tenth PMOS transistor, an eleventh PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-sixth PMOS transistor, a ninth transistor, a tenth transistor, and a sixth NMOS transistor;

[0009] The sources of the tenth PMOS tube, the eleventh PMOS tube, the twentieth PMOS tube, and the twenty-first PMOS tube are all connected to an external power supply, the base of the ninth transistor is connected to the base of the tenth transistor and the drain of the twentieth PMOS tube, the gate and source of the twenty-first PMOS tube are connected, and are also connected to the gate of the twentieth PMOS tube and the source of the twenty-sixth PMOS tube, the collectors of the ninth transistor and the tenth transistor are connected to the drains of the tenth PMOS tube and the eleventh PMOS tube, respectively, and the tenth PMOS tube and the eleventh PMOS tube are connected. The gates of the transistors are connected to the reference circuit, the collector of the tenth transistor is also connected to the gate of the twenty-sixth PMOS transistor, the emitter of the ninth transistor is grounded through the sixth NMOS transistor, and the emitter of the ninth transistor serves as the output end of the temperature compensation circuit, one end of the ninth capacitor is connected to the gate of the sixth NMOS transistor and the collector of the ninth transistor, and the other end of the ninth capacitor, the emitter of the tenth transistor and the drain of the twenty-sixth PMOS transistor serve as the input end of the temperature compensation circuit, which is used to connect to the output end of the reference circuit or another temperature compensation circuit.

[0010] A further technical solution is: the temperature compensation circuit further includes a fifth capacitor, and the two ends of the fifth capacitor are respectively connected to the base and collector of the transistor.

[0011] Its further technical solution is: the multi-stage temperature compensation circuit includes three temperature compensation circuits, namely a first temperature compensation circuit, a second temperature compensation circuit and a third temperature compensation circuit. The first temperature compensation circuit, the second temperature compensation circuit and the third temperature compensation circuit have the same structure, and the input end of the first temperature compensation circuit is connected to the reference circuit, and its output end is connected to the input end of the second temperature compensation circuit, so that the second temperature compensation circuit compensates for the first output voltage after compensation by the first temperature compensation circuit, the output end of the second temperature compensation circuit is connected to the input end of the third temperature compensation circuit, and the output end of the third temperature compensation circuit is connected to the adjustment output circuit to input the first output voltage after three compensation processes into the adjustment output circuit.

[0012] Its further technical solution is: the startup circuit includes a PMOS tube, a first PMOS tube, an NMOS tube and a diode, the gate and drain of the NMOS tube are connected, and are also connected to the gate of the PMOS tube, the anode of the diode and the drain of the first PMOS tube, the source of the first PMOS tube and the PMOS tube and the cathode of the diode are connected to an external power supply, the drain of the first PMOS tube and the PMOS tube are connected to a generating circuit, and the source of the NMOS tube is grounded through a first resistor.

[0013] Its further technical solution is: the startup circuit includes multiple PMOS tubes, multiple NMOS tubes, a diode, a first PMOS tube and a first resistor, the source and drain of the multiple PMOS tubes connected in series are respectively connected to the external power supply and the generating circuit, the drain of the multiple NMOS tubes connected in series is connected to the anode of the diode, the drain of the first PMOS tube and the gates of the multiple PMOS tubes, and the gate of each NMOS tube is connected to its drain, the source of the multiple NMOS tubes connected in series is grounded through the first resistor, the source of the first PMOS tube and the cathode of the diode are connected to the external power supply, and the gate of the first PMOS tube is connected to the generating circuit.

[0014] A further technical solution is as follows: the generating circuit includes a second PMOS transistor, a third PMOS transistor, a first transistor, a second transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor and a twenty-second PMOS transistor; wherein the sources of the second PMOS transistor, the third PMOS transistor, the twelfth PMOS transistor and the thirteenth PMOS transistor are all connected to an external power supply, the base of the first transistor is connected to the starting circuit, the base of the second transistor and the drain of the twelfth PMOS transistor, the gate and source of the thirteenth PMOS transistor are connected, and are connected to the gate of the twelfth PMOS transistor and the gate of the twenty-second PMOS transistor. The source, the collectors of the first transistor and the second transistor are connected to the drains of the second PMOS transistor and the third PMOS transistor respectively, the gate of the second PMOS transistor is also connected to the drain, and is connected to the startup circuit and the gate of the third PMOS transistor, the collector of the second transistor is also connected to the gate of the twenty-second PMOS transistor, the emitter of the first transistor is grounded through a second resistor, and the emitter of the first transistor serves as the output end of the generating circuit, connected to the multi-stage temperature compensation circuit to output a first output voltage to the multi-stage temperature compensation circuit, and the emitter of the second transistor and the drain of the twenty-second PMOS transistor are both grounded.

[0015] Its further technical solution is: the generating circuit also includes a first capacitor and a third resistor, one end of the first capacitor is connected to the base of the first transistor, the drain of the twelfth PMOS tube and the third resistor, and the other ends of the first capacitor and the third resistor are respectively connected to the collector and base of the second transistor.

[0016] A further technical solution is as follows: the regulating output circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a third transistor, a fourth transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a twenty-third PMOS transistor, a fifth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a seventh resistor, and an eighth resistor;

[0017] Among them, the sources of the fourth PMOS tube, the fifth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are all connected to the external power supply, the base of the third triode is connected to the base of the fourth triode, the drain of the fourteenth PMOS tube, the gate of the third NMOS tube and one end of the fifth resistor, the gate and source of the fifteenth PMOS tube are connected, and are connected to the gate of the fourteenth PMOS tube and the source of the twenty-third PMOS tube, the collectors of the third triode and the fourth triode are respectively connected to the drains of the fourth PMOS tube and the fifth PMOS tube, the gate of the fourth PMOS tube is also connected to the drain, and is connected to the startup circuit and the gate of the fifth PMOS tube, the second The collector of the transistor is also connected to the gate of the twenty-third PMOS transistor, the gate and drain of the first NMOS transistor are connected, and are connected to the other end of the fifth resistor, the gate and drain of the second NMOS transistor are connected, and are connected to the source of the first NMOS transistor, and serve as the output end of the regulation output circuit to output a reference voltage, the emitters of the third and fourth transistors are respectively connected to the seventh resistor and the drain of the third NMOS transistor, and the emitter of the fourth transistor serves as the input end of the regulation output circuit and is connected to the multi-stage temperature compensation circuit, the sources of the third and second NMOS transistors and the other end of the seventh resistor are all connected to the eighth resistor, and the other end of the eighth resistor is grounded.

[0018] Its further technical solution is: the regulation output circuit also includes a fourth resistor, a sixth resistor, a second capacitor, a sixth capacitor and a seventh NMOS transistor, the fourth resistor and the sixth resistor are both connected to the bases of the third transistor and the fourth transistor, the other end of the fourth resistor is connected to the collector of the fourth transistor through the second capacitor, the other end of the sixth resistor is connected to the source of the second NMOS transistor and the eighth resistor through the sixth capacitor, the drain and gate of the seventh NMOS transistor are respectively connected to the emitter and collector of the third transistor, and its source is grounded.

[0019] Compared with the prior art, the bandgap reference circuit of the present invention is provided with a multi-stage temperature compensation circuit, and the multi-stage temperature compensation circuit is composed of multiple cascaded temperature compensation circuits. The multi-stage temperature compensation circuit is connected to the generating circuit of the reference circuit, and the multiple cascaded temperature compensation circuits compensate for the first output voltage output by the generating circuit. It can be seen that by cascading multiple temperature compensation circuits, multi-stage compensation can be achieved, thereby improving the accuracy of the reference voltage output by the adjustment output circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 1 is a circuit diagram of a specific embodiment of the bandgap reference circuit of the present invention.

[0021] Figure 2 yes Figure 1The specific circuit structure diagram of the multi-order temperature compensation circuit in the bandgap reference circuit shown in FIG.

[0022] Figure 3 This is a schematic diagram of the temperature curve of a traditional bandgap reference circuit.

[0023] Figure 4 It is a schematic diagram of the temperature curve of the bandgap reference circuit of the present invention.

[0024] Figure 5 It is a schematic diagram of an embodiment in which the startup circuit in the bandgap reference circuit of the present invention includes multiple MOS transistors. Implementation Method

[0025] In order to enable those skilled in the art to more clearly understand the objectives, technical solutions and advantages of the present invention, the present invention is further described below with reference to the accompanying drawings and embodiments.

[0026] Reference Figures 1 to 2 , Figures 1 to 2 A specific embodiment of the bandgap reference circuit of the present invention is presented. In the embodiment shown in the accompanying drawings, the bandgap reference circuit includes a startup circuit, a multi-stage temperature compensation circuit, and a reference circuit. The startup circuit is connected to an external power supply VDD to generate a startup current. The multi-stage temperature compensation circuit is connected to the external power supply VDD and includes multiple cascaded temperature compensation circuits. The reference circuit includes a generation circuit and an adjustment output circuit. The generation circuit is connected to the startup circuit to operate under the action of the startup current and transmits a first output voltage generated based on the external power supply VDD to the multi-stage temperature compensation circuit, so that the multiple cascaded temperature compensation circuits compensate for the first output voltage. The adjustment output circuit is connected to the multi-stage temperature compensation circuit to output a reference voltage VBG based on the compensated first output voltage. Based on this design, the multiple cascaded temperature compensation circuits perform multi-stage compensation on the first output voltage. The output reference voltage VBG can be adjusted based on the compensated first output voltage. That is, the compensated first output voltage can compensate for the negative temperature voltage of the reference circuit, thereby improving the accuracy of the output reference voltage VBG.

[0027] In some embodiments, each of the temperature compensation circuits includes a ninth capacitor, a tenth PMOS transistor, an eleventh PMOS transistor, a twentieth PMOS transistor, a twenty-first PMOS transistor, a twenty-sixth PMOS transistor, a ninth transistor, a tenth transistor, and a sixth NMOS transistor; wherein the sources of the tenth PMOS transistor, the eleventh PMOS transistor, the twentieth PMOS transistor, and the twenty-first PMOS transistor are all connected to an external power supply VDD, the base of the ninth transistor is connected to the base of the tenth transistor and the drain of the twentieth PMOS transistor, the gate and source of the twenty-first PMOS transistor are connected, and are connected to the gate of the twentieth PMOS transistor and the source of the twenty-sixth PMOS transistor, and the ninth transistor and the thirteenth transistor are connected. The collector of the transistor is respectively connected to the drain of the tenth PMOS transistor and the eleventh PMOS transistor, the gates of the tenth PMOS transistor and the eleventh PMOS transistor are both connected to the reference circuit, the collector of the tenth triode is also connected to the gate of the twenty-sixth PMOS transistor, the emitter of the ninth triode is grounded through the sixth NMOS transistor, and the emitter of the ninth triode serves as the output end of the temperature compensation circuit, one end of the ninth capacitor is connected to the gate of the sixth NMOS transistor and the collector of the ninth triode, the other end of the ninth capacitor, the emitter of the tenth triode and the drain of the twenty-sixth PMOS transistor serve as the input end of the temperature compensation circuit, and are used to be connected to the output end of the reference circuit or another temperature compensation circuit.

[0028] Furthermore, the temperature compensation circuit also includes a fifth capacitor, and two ends of the fifth capacitor are respectively connected to the base and collector of the transistor.

[0029] In this embodiment, the multi-stage temperature compensation circuit includes three cascaded temperature compensation circuits, namely a first temperature compensation circuit, a second temperature compensation circuit and a third temperature compensation circuit. The first temperature compensation circuit, the second temperature compensation circuit and the third temperature compensation circuit have the same structure, and the input end of the first temperature compensation circuit is connected to the reference circuit, and the output end thereof is connected to the input end of the second temperature compensation circuit, so that the second temperature compensation circuit compensates for the first output voltage after compensation by the first temperature compensation circuit. The output end of the second temperature compensation circuit is connected to the input end of the third temperature compensation circuit, and the output end of the third temperature compensation circuit is connected to the adjustment output circuit to input the first output voltage after three compensation processes into the adjustment output circuit. Based on the above design, the multi-stage temperature compensation circuit is composed of three cascaded temperature compensation circuits of the same structure. Each stage of the temperature compensation circuit generates a PTAT voltage which is transmitted to the next stage of the temperature compensation circuit. By accumulating the PTAT voltages in the three-stage structure, the negative temperature voltage is adjusted. Perform temperature compensation.

[0030] Specifically, if Figure 2As shown, the first temperature compensation circuit includes a fifth capacitor C5, a ninth capacitor C9, a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twentieth PMOS transistor PM20, a twenty-first PMOS transistor PM21, a twenty-sixth PMOS transistor PM26, a ninth transistor Q9, a tenth transistor Q10, and a sixth NMOS transistor NM6; the second temperature compensation circuit includes a fifth capacitor C4, a ninth capacitor C8, a tenth PMOS transistor PM8, an eleventh PMOS transistor PM9, a twentieth PMOS transistor PM18, a twenty-first PMOS transistor PM19, a twenty-sixth PMOS transistor PM25, a ninth transistor Q7, a tenth transistor Q8, and a sixth NMOS transistor NM5; and the third temperature compensation circuit includes a fifth capacitor C3, a ninth capacitor C7, a tenth PMOS transistor PM6, an eleventh PMOS transistor PM7, a twentieth PMOS transistor PM16, a twenty-first PMOS transistor PM17, a twenty-sixth PMOS transistor PM24, a ninth transistor Q5, a tenth transistor Q6, and a sixth NMOS transistor NM4; wherein the ninth capacitor C9, the emitter of the tenth transistor Q10, and the drain of the twenty-sixth PMOS transistor PM26 are connected to the generating circuit; the emitter of the ninth transistor Q9 is connected to the emitter of the tenth transistor Q8 in the second temperature compensation circuit, the drain of the twenty-sixth PMOS transistor PM25, and the ninth capacitor C8; the emitter of the ninth transistor Q7 is connected to the emitter of the tenth transistor Q6 in the third temperature compensation circuit, the drain of the twenty-sixth PMOS transistor PM24, and the ninth capacitor C7; and the emitter of the ninth transistor Q5 is connected to the regulating output circuit. In the above circuit structure, taking the first temperature compensation circuit as an example, when the current on the 20th PMOS transistor PM20 increases, Q10 enters a low-resistance state, and the gate voltage of the 26th PMOS transistor PM26 decreases, thereby reducing the current flowing through PM26. The current mirror formed by PM20 and PM21 mirrors this current to PM20, thereby reducing the current flowing through PM20, forming a negative feedback network and improving the stability of the circuit.

[0031] like Figure 1 As shown, in this embodiment, the startup circuit includes a PMOS transistor PM, a first PMOS transistor PM1, an NMOS transistor NM, and a diode D. The gate and drain of the NMOS transistor NM are connected, and are also connected to the gate of the PMOS transistor PM, the anode of the diode D, and the drain of the first PMOS transistor PM1. The sources of the first PMOS transistor PM1 and the PMOS transistors, as well as the cathode of the diode D, are connected to an external power supply VDD. The drains of the first PMOS transistor PM1 and the PMOS transistor PM are connected to a generating circuit. The source of the NMOS transistor NM is grounded through a first resistor.

[0032] In some embodiments, the generating circuit includes a second PMOS transistor PM2, a third PMOS transistor PM3, a first transistor Q1, a second transistor Q2, a twelfth PMOS transistor PM12, a thirteenth PMOS transistor PM13, and a twenty-second PMOS transistor PM22; wherein the sources of the second PMOS transistor PM2, the third PMOS transistor PM3, the twelfth PMOS transistor PM12, and the thirteenth PMOS transistor PM13 are all connected to an external power supply VDD, the base of the first transistor Q1 is connected to the drain of the PMOS transistor PM, the base of the second transistor Q2, and the drain of the twelfth PMOS transistor PM12, the gate and source of the thirteenth PMOS transistor PM13 are connected, and are also connected to the gate of the twelfth PMOS transistor PM12 and the gate of the twenty-second PMOS transistor PM22. The source of the PMOS transistor PM22, the collectors of the first transistor Q1 and the second transistor Q2 are connected to the drains of the second PMOS transistor PM2 and the third PMOS transistor PM3, respectively. The gate of the second PMOS transistor PM2 is also connected to the drain and to the gates of the first PMOS transistor PM1 and the third PMOS transistor PM3. The collector of the second transistor Q2 is also connected to the gate of the twenty-second PMOS transistor PM22. The emitter of the first transistor Q1 is grounded via a second resistor R2. The emitter of the first transistor Q1 serves as the output end of the generating circuit and is connected to the input end of the first temperature compensation circuit to output the first output voltage to the multi-stage temperature compensation circuit. The emitter of the second transistor Q2 and the drain of the twenty-second PMOS transistor PM22 are both grounded. Preferably, the size of the first transistor Q1 is n times that of the second transistor Q2. Preferably, the value of n is generally a positive integer between 8 and 24. Based on the above design, when the external power supply VDD rises, the PMOS transistor PM in the startup circuit is turned on and transmits current to the base of the first transistor Q1 and the second transistor Q2. When the current reaches a certain level, the current on the second PMOS transistor PM2 increases, and the current is mirrored to the first PMOS transistor PM1 through the current mirror, thereby raising the gate voltage of the PMOS transistor and causing it to enter the cut-off state and stop transmitting current. In the generation circuit, through the first transistor Q1 and the second transistor Q2, The voltage difference generates a PTAT voltage on the second resistor R2 that gradually increases with increasing temperature. After passing through the three-stage temperature compensation circuit, the regulated output circuit outputs a voltage VB that is not affected by temperature.

[0033] Furthermore, the generating circuit also includes a first capacitor C1 and a third resistor R3, one end of the first capacitor C1 is connected to the base of the first transistor Q1, the drain of the twelfth PMOS transistor PM12 and the third resistor R3, and the other ends of the first capacitor C1 and the third resistor R3 are respectively connected to the collector and base of the second transistor Q2.

[0034] In some embodiments, the regulating output circuit includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a third transistor Q3, a fourth transistor Q4, a fourteenth PMOS transistor PM14, a fifteenth PMOS transistor PM15, a twenty-third PMOS transistor PM23, a fifth resistor R5, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a seventh resistor R7, and an eighth resistor R8; wherein the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the tenth The sources of the fourth PMOS transistor PM14 and the fifteenth PMOS transistor PM15 are both connected to the external power supply VDD. The base of the third transistor Q3 is connected to the base of the fourth transistor Q4, the drain of the fourteenth PMOS transistor PM14, the gate of the third NMOS transistor NM3, and one end of the fifth resistor R5. The gate and source of the fifteenth PMOS transistor PM15 are connected, and are also connected to the gate of the fourteenth PMOS transistor PM14 and the source of the twenty-third PMOS transistor PM23. The collectors of the third transistor Q3 and the fourth transistor Q4 are connected. The electrodes are respectively connected to the drains of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5. The gate of the fourth PMOS transistor PM4 is also connected to the drain and is connected to the gates of the first PMOS transistor PM1 and the fifth PMOS transistor PM5. The collector of the second transistor Q2 is also connected to the gate of the twenty-third PMOS transistor PM23. The gate and drain of the first NMOS transistor NM1 are connected and are connected to the other end of the fifth resistor R5. The gate and drain of the second NMOS transistor NM2 are connected and are connected to the source of the first NMOS transistor NM1, and serve as the output end of the regulation output circuit to output the reference voltage VBG. The emitters of the third transistor Q3 and the fourth transistor Q4 are respectively connected to the seventh resistor R7 and the drain of the third NMOS transistor NM3. The emitter of the fourth transistor Q4 serves as the input end of the regulation output circuit and is connected to the output end of the third temperature compensation circuit. The sources of the third NMOS transistor NM3 and the second NMOS transistor NM2 and the other end of the seventh resistor R7 are all connected to an eighth resistor R8, and the other end of the eighth resistor R8 is grounded.

[0035] The temperature characteristic curve of the traditional bandgap reference circuit is as follows Figure 3 As shown in FIG. 1 , the output voltage is positively correlated with the temperature at low temperatures, and negatively correlated with the temperature at high temperatures. In the bandgap reference circuit of the present invention, when the temperature decreases, the output voltage of the third transistor Q3 decreases. As the temperature decreases, the voltage of the third transistor Q3 increases, making it more difficult for the third transistor Q3 to turn on and put it in a high-resistance state, thereby raising the gate voltage of the seventh NMOS transistor NM7. At this time, the seventh NMOS transistor NM7 turns on and shunts the emitter current of the third transistor Q3, that is, the PTAT current which is positively correlated with the temperature, so that the PTAT current flowing through the seventh resistor R7 decreases. When the temperature rises, the voltage of the third transistor Q3 decreases. As the temperature increases, the third transistor Q3 is more likely to be turned on and in a low-resistance state, thereby raising the gate voltage of the seventh NMOS transistor NM7. At this time, the seventh NMOS transistor NM7 is cut off and does not shunt the PTAT current, which increases the PTAT current. The temperature characteristic curve of the bandgap reference circuit of the present invention is shown in FIG. Figure 4 shown.

[0036] Preferably, the regulation output circuit further includes a fourth resistor R4, a sixth resistor R6, a second capacitor C2, a sixth capacitor C6 and a seventh NMOS transistor NM7. The fourth resistor R4 and the sixth resistor R6 are both connected to the bases of the third transistor Q3 and the fourth transistor Q4. The other end of the fourth resistor R4 is connected to the collector of the fourth transistor Q4 through the second capacitor C2. The other end of the sixth resistor R6 is connected to the source of the second NMOS transistor NM2 and the eighth resistor R8 through the sixth capacitor C6. The drain and gate of the seventh NMOS transistor NM7 are respectively connected to the emitter and collector of the third transistor Q3, and its source is grounded.

[0037] Understandably, since the output voltage of the traditional bandgap reference circuit is a linear combination of the positive temperature voltage and the negative temperature voltage, ,in, is proportional to the absolute temperature, so The high-order temperature term introduced can be ignored. The high-order temperature coefficient mainly comes from the Temperature characteristics.

[0038] , where η is the electric field factor, a constant determined by the process, is a given constant temperature, It is related to temperature and will produce a high-order temperature term containing TlnT. Traditional temperature compensation cannot offset the influence of this high-order temperature term. The present invention uses a multi-stage temperature compensation circuit to accumulate multiple compensations. The voltage difference between the transistors is reduced by the difference in temperature characteristics between the transistors. The impact of logarithmic terms.

[0039] like Figure 5 As shown, Figure 5 Schematic diagram of an embodiment of the present invention wherein the start-up circuit in the bandgap reference circuit includes multiple MOS transistors. Figure 1The embodiment shown differs in the specific structure of the startup circuit. In this embodiment, the startup circuit includes multiple PMOS transistors, multiple NMOS transistors, a diode DX, a first PMOS transistor PM1, and a first resistor R1. As shown in the figure, the startup circuit includes five PMOS transistors, namely PM01, PM02, PM03, PM04, and PM05, and five NMOS transistors, namely NM01, NM02, NM03, NM04, and NM05. The sources and drains of the five PMOS transistors connected in series are connected to the external power supply VDD and the generating circuit, respectively. The drains of the five NMOS transistors connected in series are connected to the anode of the diode DX, the drain of the first PMOS transistor PM1, and the gates of the five PMOS transistors PM. The gate of each NMOS transistor is connected to its drain. The sources of the NMOS transistors NM01, NM02, NM03, NM04, and NM05 connected in series are grounded via the first resistor R1. The source of the first PMOS transistor PM1 and the cathode of the diode DX are connected to the external power supply VDD. The gate of the first PMOS transistor PM1 is connected to the generating circuit.

[0040] To sum up, the bandgap reference circuit of the present invention is provided with a multi-stage temperature compensation circuit, and the multi-stage temperature compensation circuit is composed of multiple cascaded temperature compensation circuits. The multi-stage temperature compensation circuit is connected to the generating circuit of the reference circuit, and the multiple cascaded temperature compensation circuits compensate for the first output voltage output by the generating circuit. It can be seen that by cascading multiple temperature compensation circuits, multi-stage compensation can be achieved, thereby improving the accuracy of the reference voltage output by the adjustment output circuit.

[0041] The above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention in any form.

[0042] Those skilled in the art may make various equivalent changes and improvements based on the above embodiments. All equivalent changes or modifications made within the scope of the claims should fall within the protection scope of the present invention.

Claims

1. A bandgap reference circuit, characterized in that: include: A starting circuit, connected to an external power supply, for generating a starting current; a multi-stage temperature compensation circuit connected to an external power supply, comprising a plurality of cascaded temperature compensation circuits; A reference circuit comprising a generating circuit and a regulating output circuit, wherein the generating circuit is connected to the starting circuit to operate under the action of the starting current and transmits a first output voltage generated by an external power supply to the multi-stage temperature compensation circuit so that the multiple cascaded temperature compensation circuits compensate for the first output voltage; and the regulating output circuit is connected to the multi-stage temperature compensation circuit to output a reference voltage based on the compensated first output voltage; Wherein, each of the temperature compensation circuits includes a ninth capacitor, a tenth PMOS tube, an eleventh PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-sixth PMOS tube, a ninth transistor, a tenth transistor and a sixth NMOS tube; the sources of the tenth PMOS tube, the eleventh PMOS tube, the twentieth PMOS tube and the twenty-first PMOS tube are all connected to an external power supply, the base of the ninth transistor is connected to the base of the tenth transistor and the drain of the twentieth PMOS tube, the gate and source of the twenty-first PMOS tube are connected, and are connected to the gate of the twentieth PMOS tube and the source of the twenty-sixth PMOS tube, and the collector of the ninth transistor is connected to the base of the tenth PMOS tube. The drain of the tenth triode is connected to the drain of the eleventh PMOS tube. The gates of the tenth PMOS tube and the eleventh PMOS tube are both connected to the reference circuit. The collector of the tenth triode is also connected to the gate of the twenty-sixth PMOS tube. The emitter of the ninth triode is grounded through the sixth NMOS tube, and the emitter of the ninth triode serves as the output end of the temperature compensation circuit. One end of the ninth capacitor is connected to the gate of the sixth NMOS tube and the collector of the ninth triode. The other end of the ninth capacitor, the emitter of the tenth triode and the drain of the twenty-sixth PMOS tube serve as the input end of the temperature compensation circuit, which is used to connect to the output end of the reference circuit or another temperature compensation circuit.

2. The bandgap reference circuit according to claim 1, wherein: The temperature compensation circuit further includes a fifth capacitor, and two ends of the fifth capacitor are respectively connected to the base and the collector of the transistor.

3. The bandgap reference circuit according to claim 1, wherein: The multi-stage temperature compensation circuit includes three temperature compensation circuits, namely a first temperature compensation circuit, a second temperature compensation circuit and a third temperature compensation circuit. The first temperature compensation circuit, the second temperature compensation circuit and the third temperature compensation circuit have the same structure, and the input end of the first temperature compensation circuit is connected to the reference circuit, and its output end is connected to the input end of the second temperature compensation circuit, so that the second temperature compensation circuit compensates for the first output voltage after compensation by the first temperature compensation circuit, the output end of the second temperature compensation circuit is connected to the input end of the third temperature compensation circuit, and the output end of the third temperature compensation circuit is connected to the adjustment output circuit to input the first output voltage after three compensation processes into the adjustment output circuit.

4. The bandgap reference circuit according to claim 1, wherein: The startup circuit includes a PMOS transistor PM, a first PMOS transistor PM1, an NMOS transistor NM, and a diode. The gate and drain of the NMOS transistor NM are connected, and are also connected to the gate of the PMOS transistor PM, the anode of the diode, and the drain of the first PMOS transistor PM1. The sources of the first PMOS transistor PM1 and the PMOS transistor PM, as well as the cathode of the diode, are connected to an external power supply. The drains of the first PMOS transistor PM1 and the PMOS transistor PM are connected to a generating circuit. The source of the NMOS transistor NM is grounded via a first resistor.

5. The bandgap reference circuit according to claim 1, wherein: The startup circuit includes multiple PMOS transistors PM, multiple NMOS transistors NM, a diode, a first PMOS transistor PM1, and a first resistor. The sources and drains of the multiple PMOS transistors PM connected in series are respectively connected to an external power supply and a generating circuit. The drains of the multiple NMOS transistors NM connected in series are connected to the anode of the diode, the drain of the first PMOS transistor PM1, and the gates of the multiple PMOS transistors PM. The gate of each NMOS transistor NM is connected to its drain. The sources of the multiple NMOS transistors NM connected in series are grounded via the first resistor. The source of the first PMOS transistor PM1 and the cathode of the diode are connected to the external power supply. The gate of the first PMOS transistor PM1 is connected to the generating circuit.

6. The bandgap reference circuit according to claim 1, wherein: The generating circuit includes a second PMOS tube, a third PMOS tube, a first transistor, a second transistor, a twelfth PMOS tube, a thirteenth PMOS tube and a twenty-second PMOS tube; wherein the sources of the second PMOS tube, the third PMOS tube, the twelfth PMOS tube and the thirteenth PMOS tube are all connected to an external power supply, the base of the first transistor is connected to the starting circuit, the base of the second transistor and the drain of the twelfth PMOS tube, the gate and source of the thirteenth PMOS tube are connected, and are connected to the gate of the twelfth PMOS tube and the source of the twenty-second PMOS tube, and the The collectors of the first transistor and the second transistor are connected to the drains of the second PMOS transistor and the third PMOS transistor, respectively. The gate of the second PMOS transistor is also connected to the drain, and is connected to the startup circuit and the gate of the third PMOS transistor. The collector of the second transistor is also connected to the gate of the twenty-second PMOS transistor. The emitter of the first transistor is grounded via a second resistor. The emitter of the first transistor serves as the output end of the generating circuit and is connected to the multi-stage temperature compensation circuit to output a first output voltage to the multi-stage temperature compensation circuit. The emitter of the second transistor and the drain of the twenty-second PMOS transistor are both grounded.

7. The bandgap reference circuit according to claim 6, wherein: The generating circuit also includes a first capacitor and a third resistor, one end of the first capacitor is connected to the base of the first transistor, the drain of the twelfth PMOS transistor and the third resistor, and the other ends of the first capacitor and the third resistor are respectively connected to the collector and base of the second transistor.

8. The bandgap reference circuit according to claim 1, wherein: The regulating output circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a third transistor, a fourth transistor, a fourteenth PMOS transistor, a fifteenth PMOS transistor, a twenty-third PMOS transistor, a fifth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a seventh resistor, and an eighth resistor; Among them, the sources of the fourth PMOS tube, the fifth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are all connected to the external power supply, the base of the third transistor is connected to the base of the fourth transistor, the drain of the fourteenth PMOS tube, the gate of the third NMOS tube and one end of the fifth resistor, the gate and source of the fifteenth PMOS tube are connected, and are connected to the gate of the fourteenth PMOS tube and the source of the twenty-third PMOS tube, the collectors of the third and fourth transistors are respectively connected to the drains of the fourth PMOS tube and the fifth PMOS tube, the gate of the fourth PMOS tube is also connected to the drain, and is connected to the startup circuit and the gate of the fifth PMOS tube, and the collector of the fourth transistor The gate of the twenty-third PMOS transistor is also connected, the gate and drain of the first NMOS transistor are connected, and are connected to the other end of the fifth resistor, the gate and drain of the second NMOS transistor are connected, and are connected to the source of the first NMOS transistor, and serve as the output end of the regulation output circuit to output a reference voltage, the emitters of the third and fourth triodes are respectively connected to the seventh resistor and the drain of the third NMOS transistor, and the emitter of the fourth triode serves as the input end of the regulation output circuit and is connected to the multi-stage temperature compensation circuit, the sources of the third and second NMOS transistors, and the other end of the seventh resistor are all connected to the eighth resistor, and the drain of the twenty-third PMOS transistor and the other end of the eighth resistor are grounded.

9. The bandgap reference circuit according to claim 8, wherein: The regulation output circuit also includes a fourth resistor, a sixth resistor, a second capacitor, a sixth capacitor and a seventh NMOS transistor. The fourth resistor and the sixth resistor are both connected to the bases of the third transistor and the fourth transistor. The other end of the fourth resistor is connected to the collector of the fourth transistor through the second capacitor. The other end of the sixth resistor is connected to the source of the second NMOS transistor and the eighth resistor through the sixth capacitor. The drain and gate of the seventh NMOS transistor are respectively connected to the emitter and collector of the third transistor, and its source is grounded.

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