A graph structure-aware graph neural network hardware acceleration device and method

Abstract

The specification discloses a kind of graph structure perception's graph neural network hardware acceleration device and method, can be filtered out from each node included in original graph data The node with degree higher than preset threshold value is used as the pivot node for connecting each community, and then each neighbor node of pivot node can be used as starting node, by accessing other nodes with the connection between this neighbor node, as the associated node of this neighbor node, so that the neighbor node and the associated node of this neighbor node can be divided out as a graph data block of original graph data, and node update processing is carried out for each graph data block, and then redundant calculation caused by directly using the feature matrix corresponding to all nodes included in original graph data for calculation can be avoided, to improve data processing efficiency.

Description

TECHNICAL FIELD

[0001] The present specification relates to the technical field of graph computing, and particularly relates to a graph structure-aware graph neural network hardware acceleration device and method. BACKGROUND

[0002] At present, in the process of processing graph data by using a graph convolutional neural network, since the graph data to be processed has the characteristics of large size and sparse data distribution, when a feature matrix corresponding to the graph data is used for calculation, there are many invalid calculation operations, which further reduces the processing efficiency.

[0003] Therefore, how to improve the data processing efficiency is a problem to be solved. SUMMARY

[0004] The present specification provides a graph structure-aware graph neural network hardware acceleration device and method to partially solve the above problems existing in the prior art.

[0005] The present specification adopts the following technical solutions:

[0006] The present specification provides a graph structure-aware graph neural network hardware acceleration device, which comprises a first processor and a second processor.

[0007] The first processor is configured to determine whether the degree of each node in the original graph data exceeds a preset threshold value, and if so, determine the node as a hub node, and for each neighbor node of the hub node, determine other nodes having a connection relationship with the neighbor node in the original graph data as associated nodes of the neighbor node through multiple rounds of node queries, and determine a graph data block of the original graph data according to the neighbor node and the associated nodes of the neighbor node.

[0008] The second processor is configured to update the node feature representation of each node in the graph data block according to the node feature representation of each neighbor node of the node in the graph data block, to obtain an updated feature representation of the node, and update the original graph data according to the updated feature representation of the node and other nodes.

[0009] Optionally, the first processor is configured to determine the associated nodes of each neighbor node of the hub node as a starting node through multiple rounds of node queries; and wherein,

[0010] For each round of node query, determine each target node in the round of node query, judge whether there is an unvisited node in each neighbor node of the target node, if yes, take the unvisited node as an associated node of the starting node, set the unvisited node as a visited node, and take the unvisited node as a target node of the next round of node query, the target node is obtained by iterating the starting node to the last round;

[0011] After it is determined that the preset first termination condition is met, each associated node of the starting node is obtained.

[0012] Optionally, the first processor is configured to, for each target node in each round of node query, judge whether the target node is included in a preset global visited node set, if not, determine that the target node is a visited neighbor node corresponding to the starting node, and add the target node to the global visited node set, if yes, determine that the starting node has no associated node, and remove the visited neighbor node corresponding to the starting node from the global visited node set.

[0013] Optionally, the second processor includes at least one processing unit.

[0014] At least part of the processing units is configured to, for each node included in the graph data block, aggregate node feature representations of at least part of neighbor nodes of the node in the graph data block to obtain a sub-aggregated feature representation of the node; and

[0015] The other processing units are configured to update the node feature representation of the node according to each sub-aggregated feature representation of the node to obtain an updated feature representation of the node.

[0016] Optionally, the graph structure-aware graph neural network hardware acceleration device further includes a task scheduler.

[0017] The task scheduler is configured to generate a first data processing task for the graph data block, and distribute the first data processing task to the processing units according to load values of the processing units, the first data processing task being configured to aggregate node feature representations of part of nodes; and

[0018] The task scheduler is configured to generate a second data processing task for the graph data block, and distribute the second data processing task to the processing units according to load values of the processing units, the second data processing task being configured to update a node feature representation of at least one node in the graph data block.

[0019] Optionally, the task scheduler is configured to, for each processing unit, determine whether a load value of the processing unit exceeds a preset first load threshold, and if so, determine processing units adjacent to the processing unit in the processing units as candidate processing units, determine at least one candidate processing unit with a lowest load value among the candidate processing units as a target processing unit, and assign the first data processing task or the second data processing task being processed by the processing unit to the target processing unit.

[0020] Optionally, the task scheduler is configured to, for each processing unit among the processing units, determine whether a difference between a load value of the processing unit and load values of other processing units exceeds a preset second load threshold, and if so, split the first data processing task or the second data processing task being processed by the processing unit to obtain sub data processing tasks, and assign the sub data processing tasks to a processing unit with a smallest load value among the processing units.

[0021] Optionally, the second processor is configured to, for each node included in the graph data block, determine an updated feature representation of the node through multiple rounds of iteration; wherein,

[0022] For each round of iteration, an updated node feature representation of the node is determined, the updated node feature representation is updated according to an aggregated feature representation corresponding to the node determined in a previous round of iteration to obtain an updated feature representation of the node in the round of iteration, and the updated feature representation of the node in the round of iteration is taken as an updated node feature representation in a next round of iteration, the aggregated feature representation is used to represent an aggregation result of neighbor nodes of the node in the graph data block, and the updated node feature representation is obtained by iterating a node feature representation of the node to the previous round;

[0023] When it is determined that a preset second termination condition is met, the updated feature representation of the node is obtained.

[0024] The specification provides a graph structure-aware graph neural network hardware acceleration method, which is applied to a graph structure-aware graph neural network hardware acceleration device, the graph structure-aware graph neural network hardware acceleration device includes a first processor and a second processor, and the method includes:

[0025] The first processor determines whether a degree of each node included in original graph data exceeds a preset threshold.

[0026] If yes, the node is determined as a pivot node, and for each neighbor node of the pivot node, other nodes in the original graph data having a connection relationship with the neighbor node are determined as associated nodes of the neighbor node through multi-round node query;

[0027] According to the neighbor node and the associated nodes of the neighbor node, a graph data block of the original graph data is determined, so that for each node included in the graph data block, the node feature representation of the node is updated according to the node feature representations of the neighbor nodes of the node in the graph data block through the second processor, to obtain an updated feature representation of the node, and the original graph data is updated according to the updated feature representations of the node and other nodes.

[0028] Optionally, for each neighbor node of the pivot node, other nodes in the original graph data having a connection relationship with the neighbor node are determined as associated nodes of the neighbor node through multi-round node query, and specifically comprising:

[0029] For each neighbor node of the pivot node, the neighbor node is taken as a starting node, and the associated nodes of the neighbor node are determined through multi-round node query; wherein,

[0030] For each round of node query, each target node in the round of node query is determined, and it is judged whether the target nodes have neighbor nodes or not. If yes, the target nodes are taken as associated nodes of the starting node, and the neighbor nodes of the target nodes are taken as target nodes of the next round of node query, and the target nodes are obtained by iterating the starting node to the last round;

[0031] After it is determined that the preset first termination condition is met, the associated nodes of the starting node are obtained.

[0032] Optionally, it is judged whether the target nodes have neighbor nodes or not, and specifically comprising:

[0033] For each target node in each round of node query, it is judged whether the target node is included in a preset global visited node set or not;

[0034] If yes, it is determined that the starting node has no associated node, and the visited neighbor node corresponding to the starting node is removed from the global visited node set;

[0035] If no, the target node is determined as a visited neighbor node corresponding to the starting node, the target node is added to the global visited node set, and it is judged whether the target nodes have neighbor nodes or not.

[0036] Optionally, the second processor comprises at least one processing unit;

[0037] According to the node feature representation of each neighbor node of the node in the graph data block, the node feature representation of the node is updated to obtain an updated feature representation of the node, specifically including:

[0038] By at least part of the processing units, for each node contained in the graph data block, the node feature representation of at least part of the neighbor nodes of the node in the graph data block is aggregated to obtain a sub-aggregated feature representation of the node; and

[0039] According to the sub-aggregated feature representations of the node, the node feature representation of the node is updated by other processing units to obtain an updated feature representation of the node.

[0040] Optionally, the graph structure-aware graph neural network hardware acceleration device further comprises a task scheduler;

[0041] By at least part of the processing units, for each node contained in the graph data block, the node feature representation of at least part of the neighbor nodes of the node in the graph data block is aggregated to obtain a sub-aggregated feature representation of the node, specifically including:

[0042] The task scheduler generates a first data processing task for the graph data block, and according to the load values of the processing units, the first data processing task is allocated to the processing units, so that the processing units aggregate the node feature representations of at least part of the neighbor nodes of each node contained in the graph data block to obtain a sub-aggregated feature representation of the node;

[0043] According to the sub-aggregated feature representations of the node, the node feature representation of the node is updated by other processing units to obtain an updated feature representation of the node, specifically including:

[0044] The task scheduler generates a second data processing task for the graph data block, and according to the load values of the processing units, the second data processing task is allocated to the processing units, so that the processing units update the node feature representation of the node according to the sub-aggregated feature representations of the node to obtain an updated feature representation of the node.

[0045] Optionally, the method further comprises:

[0046] The task scheduler determines, for each processing unit, whether a load value of the processing unit exceeds a preset first load threshold value, and if so, determines, as candidate processing units, each processing unit adjacent to the processing unit in the processing units, determines, as a target processing unit, at least one candidate processing unit having a lowest load value among the candidate processing units, and assigns a first data processing task or a second data processing task being processed by the processing unit to the target processing unit.

[0047] Optionally, the method further comprises:

[0048] The task scheduler determines, for each processing unit among the processing units, whether a difference between a load value of the processing unit and a load value of another processing unit exceeds a preset second load threshold value, and if so, splits a first data processing task or a second data processing task being processed by the processing unit to obtain sub data processing tasks, and assigns the sub data processing tasks to a processing unit having a smallest load value among the processing units.

[0049] Optionally, for each node included in the graph data block, an updated node feature representation of the node is obtained by updating a node feature representation of the node according to node feature representations of neighbor nodes of the node in the graph data block, and the updating specifically comprises:

[0050] For each node included in the graph data block, an updated node feature representation of the node is determined through multiple rounds of iteration; wherein,

[0051] For each round of iteration, a node feature representation to be updated of the node is determined, the node feature representation to be updated is updated according to an aggregated feature representation corresponding to the node determined in a previous round of iteration to obtain an updated node feature representation corresponding to the node in the round of iteration, and the updated node feature representation corresponding to the node in the round of iteration is taken as a node feature representation to be updated in a next round of iteration, the aggregated feature representation is used to represent an aggregation result of neighbor nodes of the node in the graph data block, and the node feature representation to be updated is obtained by iterating a node feature representation of the node to the previous round;

[0052] When it is determined that a preset second termination condition is met, the updated node feature representation of the node is obtained.

[0053] The present specification provides a computer-readable storage medium, the storage medium stores a computer program, and the computer program is executed by a processor to implement the above-mentioned graph structure-aware graph neural network hardware acceleration method.

[0054] The specification provides an electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the above-mentioned graph structure-aware graph neural network hardware acceleration method when executing the program.

[0055] The above-mentioned at least one technical solution adopted by the specification can achieve the following beneficial effects:

[0056] In the graph structure-aware graph neural network hardware acceleration method provided by the specification, the first processor determines whether the degree of each node contained in the original graph data exceeds a preset threshold, and if so, determines that the node is a hub node, and determines, for each neighbor node of the hub node, other nodes having a connection relationship with the neighbor node in the original graph data as associated nodes of the neighbor node, determines a graph data block of the original graph data according to the neighbor node and the associated nodes of the neighbor node, and updates the node feature representation of each node contained in the graph data block by the second processor according to the node feature representation of each neighbor node of the node in the graph data block to obtain an updated feature representation of the node, and updates the original graph data according to the updated feature representations of the node and other nodes.

[0057] As can be seen from the above method, nodes with a degree higher than a preset threshold can be selected from each node contained in the original graph data as hub nodes for connecting communities, and each neighbor node of the hub node can be taken as a starting node, and other nodes having a connection relationship with the neighbor node can be accessed as associated nodes of the neighbor node, so that the neighbor node and the associated nodes of the neighbor node can be divided out as a graph data block of the original graph data, and node update processing can be performed on each graph data block, thereby avoiding redundant calculation caused by directly using the feature matrix corresponding to all nodes contained in the original graph data for calculation, and improving data processing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0058] The accompanying drawings described herein are used to provide further understanding of the specification, and form a part of the specification. The illustrative embodiments of the specification and their descriptions serve to explain the specification, and do not constitute an improper limitation on the specification. In the drawings:

[0059] Figure 1 A schematic diagram of a graph structure-aware graph neural network hardware acceleration device provided in the specification;

[0060] Figure 2 A schematic diagram of a task scheduler provided in the specification;

[0061] Figure 3A schematic diagram of a load balancing process provided in the present specification;

[0062] Figure 4 A schematic diagram of the effect of a load balancing process provided in the present specification;

[0063] Figure 5 A schematic diagram of a graph structure-aware graph neural network hardware acceleration method provided in the present specification;

[0064] Figure 6 A schematic diagram of an electronic device corresponding to Figure 5 provided in the present specification. DETAILED DESCRIPTION

[0065] In order to make the objects, technical solutions and advantages of the present specification clearer, the technical solutions of the present specification will be described below in conjunction with specific embodiments of the present specification and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present specification, but not all the embodiments. Based on the embodiments in the present specification, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present specification.

[0066] The technical solutions provided by the embodiments of the present specification will be described in detail below in conjunction with the drawings.

[0067] A graph structure-aware graph neural network hardware acceleration device is provided in the present specification, as shown in Figure 1 .

[0068] Figure 1 A schematic diagram of a graph structure-aware graph neural network hardware acceleration device provided in the present specification.

[0069] As can be seen from Figure 1 , the graph structure-aware graph neural network hardware acceleration device comprises a first processor and a second processor.

[0070] The first processor is configured to determine, for each node contained in the original graph data, whether the degree of the node exceeds a preset threshold, and if so, determine the node as a hub node, and for each neighbor node of the hub node, determine, through multiple rounds of node queries, other nodes in the original graph data that have a connection relationship with the neighbor node as associated nodes of the neighbor node, and determine, according to the neighbor node and the associated nodes of the neighbor node, a graph data block of the original graph data.

[0071] It should be noted that the degree of the node mentioned above can refer to the sum of the in-degree and the out-degree of the node, the in-degree of the node indicating the number of edges entering the node in the graph data, and the out-degree of the node indicating the number of edges departing from the node.

[0072] The preset threshold can be set according to actual needs, and can be gradually reduced as execution progresses, for example: assuming that the value of the preset threshold in the first round is 10, all nodes with a degree greater than 10 will be selected as the hub node in this round, and after all nodes of the original graph data are screened with 10 as the preset threshold, the second round of graph data blocking can be started, and the preset threshold can be adjusted to 8 in the second round of graph data blocking, and nodes with a degree greater than 8 are selected from all nodes of the original graph data as hub nodes, and the like.

[0073] Specifically, the first processor can determine, for each neighbor node of the hub node, the other nodes in the original graph data that have a connection relationship with the neighbor node as the associated nodes of the neighbor node by multiple rounds of node queries, wherein for each round of node query, the target nodes in the round of node query are determined, it is judged whether there is an unvisited node in each neighbor node of each target node, if yes, the unvisited nodes in each neighbor node of each target node are taken as the associated nodes of the starting node, and the unvisited nodes in each neighbor node of each target node are set as visited nodes, and the unvisited nodes in each neighbor node of each target node are taken as the target nodes of the next round of node query, each target node is obtained by iterating the starting node to the last round, and after the preset first termination condition is met, each associated node of the starting node is obtained.

[0074] The first termination condition can be set according to actual needs, for example: each neighbor node of each target node in the round of node query is a visited node. For another example: the number of visited nodes exceeds a preset threshold.

[0075] It should be noted that the process of the first processor querying each neighbor node of each target node can be executed in parallel through multiple threads.

[0076] In addition, as can be seen from the above, in the process of the first processor taking each neighbor node of the hub node as the starting node and determining the associated nodes of each neighbor node through multiple rounds of node queries, a situation that a node is repeatedly accessed multiple times can occur, that is, a node that is not accessed in the multiple rounds of node queries of the current starting node can have been accessed in the multiple rounds of node queries of other starting nodes.

[0077] Based on this, the first processor can determine, for each target node in each round of node query, whether the target node is included in the preset global visited node set, and if not, determine that the target node is the visited neighbor node corresponding to the starting node, and add the target node to the global visited node set, and if yes, determine that the starting node does not exist associated node, and remove the visited neighbor node corresponding to the starting node from the global visited node set.

[0078] It should be noted that the graph data block determined by the first processor contains not only the data of the corresponding node, but also the structure information of the graph data block. The structure information includes the number of nodes contained in the graph data block, the index of the hub node connected by the graph data block, the number of hub nodes connected by the graph data block, and the like.

[0079] Further, the second processor is configured to update the node feature representation of each node in the graph data block according to the node feature representation of each neighbor node of the node in the graph data block, obtain the updated feature representation of the node, and update the original graph data according to the updated feature representation of the node and other nodes.

[0080] Further, the second processor comprises at least one processing unit, and at least part of the processing units in each processing unit are configured to aggregate the node feature representation of at least part of the neighbor nodes of each node in the graph data block to obtain the sub-aggregated feature representation of the node, and the other processing units in each processing unit are configured to update the node feature representation of the node according to each sub-aggregated feature representation of the node to obtain the updated feature representation of the node.

[0081] In addition, the graph structure-aware graph neural network hardware acceleration device further comprises a task scheduler, specifically as shown in Figure 2

[0082] Figure 2 The schematic diagram of the task scheduler provided in the present specification.

[0083] In combination with Figure 2 ​It can be seen that the first data processing task for the graph data block can be generated by the task scheduler, and the first data processing task is used to aggregate the node feature representation of the partial nodes, and the first data processing task is allocated to the processing unit according to the load value of each processing unit. And the task scheduler can generate a second data processing task for the graph data block, and the second data processing task is used to update the node feature representation of at least one node in the graph data block, and the second data processing task is allocated to the processing unit according to the load value of each processing unit.

[0084] Further, the task scheduler can also balance the load of each processing unit by two different load balancing methods, which will be described in detail below.

[0085] The first load balancing method can be that the task scheduler determines whether the load value of each processing unit exceeds a preset first load threshold, and if so, determines the processing units adjacent to the position of the processing unit as candidate processing units, determines at least one candidate processing unit with the lowest load value among the candidate processing units as a target processing unit, and allocates the first data processing task or the second data processing task being processed by the processing unit to the target processing unit.

[0086] It should be noted that the above-mentioned allocation of the first data processing task or the second data processing task being processed by the processing unit to the target processing unit is not directly transferring the first data processing task or the second data processing task to the target processing unit, but borrowing the computing resources of the target processing unit to execute at least part of the computing tasks in the first data processing task or the second data processing task, and sending the execution result to the processing unit.

[0087] It should be noted that the target processing unit is selected from the processing units adjacent to the position of the processing unit because the data transmission efficiency between adjacent processing units is higher and it is easier to realize the transfer of the first data processing task or the second data processing task.

[0088] The second load balancing method can be that the task scheduler determines whether the difference between the load value of each processing unit and the load value of other processing units exceeds a preset second load threshold, and if so, the first data processing task or the second data processing task being processed by the processing unit is split to obtain sub-data processing tasks, and each sub-data processing task is allocated to a processing unit with the smallest load value among the processing units.

[0089] It should be noted that the two load balancing methods described above can be used alone or simultaneously, and the specific use is as follows:Figure 3 as shown.

[0090] Figure 3 is a schematic diagram of the load balancing process provided in the present specification.

[0091] In combination Figure 3 As can be seen, preferably, since the efficiency of data transmission is high, the overhead is small, and the first load balancing method is executed quickly when the first load balancing method is used to balance the load of adjacent processing units, the task scheduler can determine, for each processing unit, whether the load value of the processing unit exceeds the preset first load threshold, and if so, determine the processing units adjacent to the position of the processing unit in the processing units as target processing units, and evenly distribute the first data processing task or the second data processing task being processed by the processing unit to each target processing unit.

[0092] Further, since in actual application scenarios, there can be some first data processing tasks or second data processing tasks that require a large amount of data processing, so that after the task scheduler evenly distributes the task to the adjacent target processing units processing the task, the load of the processing unit and the target processing units still far exceeds that of other processing units, at this time, the task scheduler can use the first load balancing method described above, and then for each processing unit in the processing units, determine whether the difference between the load value of the processing unit and the load value of other processing units exceeds the preset second load threshold, and if so, split the first data processing task or the second data processing task being processed by the processing unit to obtain sub-data processing tasks, and distribute the sub-data processing tasks to the processing unit with the smallest load value in the processing units, and can again determine, for each processing unit in the processing units, whether the difference between the load value of the processing unit and the load value of other processing units exceeds the preset second load threshold, until the difference between the load value of each processing unit and the load value of other processing units is less than the second load threshold.

[0093] To explain the above in more detail, the following describes the effect of balancing the load of each processing unit by the two load balancing methods, as shown in Figure 4

[0094] Figure 4 is a schematic diagram of the load balancing process provided in the present specification.

[0095] From Figure 4 ​As can be seen from the above, due to the power-law distribution characteristics of the graph data, a small number of processing units can be in a busy state (i.e., a high workload percentage), while other processing units are in an idle state at some time, resulting in low overall efficiency. Based on this, the first load balancing method can be used to perform load balancing processing for each processing unit with a high load.

[0096] However, after load balancing processing by the first load balancing method, the loads of the processing units can still be unbalanced. At this time, the second load balancing method can be used to continue load balancing processing, so that the loads of the processing units are more balanced, thereby improving the overall efficiency.

[0097] Further, the second processor can update the node feature representation of the node according to the node feature representations of the neighbor nodes of the node in the graph data block, to obtain the updated feature representation of the node. The method for obtaining the updated feature representation of the node can be that, for each node included in the graph data block, the updated feature representation of the node is determined through multiple iterations.

[0098] For each iteration, the second processor can determine a to-be-updated node feature representation of the node, update the to-be-updated node feature representation according to the aggregated feature representation corresponding to the to-be-updated node determined in the last iteration, obtain the updated feature representation corresponding to the node in the iteration, and use the updated feature representation corresponding to the node in the iteration as the to-be-updated node feature representation in the next iteration. The aggregated feature representation is used to represent the aggregation result of the neighbor nodes of the node in the graph data block. The to-be-updated node feature representation is obtained by iterating the node feature representation of the node to the last iteration. When a preset second termination condition is met, the updated feature representation of the node is obtained.

[0099] The second termination condition can be set according to actual needs, for example, the number of iterations reaches a preset number of iterations. The method for updating the to-be-updated node feature representation according to the aggregated feature representation corresponding to the to-be-updated node to obtain the updated feature representation of the to-be-updated node in the iteration can be that, the aggregated feature representation corresponding to the to-be-updated node and the node feature representation of the to-be-updated node are weighted and fused to obtain the updated node feature representation of the to-be-updated node.

[0100] As can be seen from the above, in the process of updating the node for each node in the graph data block, the process mainly includes two stages, i.e., an aggregation stage of aggregating the neighbor nodes of the node in the graph data block to obtain the aggregated feature representation corresponding to the node, and an update stage of updating the to-be-updated node feature representation according to the aggregated feature representation corresponding to the node.

[0101] In an actual application scenario, some nodes in the graph data block can have a large number of neighbor nodes, and thus, if the aggregated feature representation of each neighbor node obtained in each iteration is used to update the to-be-updated node, the time required for aggregating each neighbor node of the to-be-updated node to obtain the aggregated feature representation can be long, which can affect the efficiency of updating the to-be-updated node. Therefore, the aggregated feature representation of each neighbor node obtained in the last iteration can be used in each iteration. In this way, the aggregation phase and the updating phase can be performed simultaneously in each iteration, thereby improving the efficiency of updating the nodes in the graph data block.

[0102] Further, in each iteration, the neighbor nodes required for aggregation in the iteration can be divided into neighbor node groups, and aggregation can be performed on each neighbor node group to obtain sub-aggregated feature representations. Finally, the sub-aggregated feature representations can be aggregated to obtain the aggregated feature representation of each neighbor node.

[0103] It should be noted that the hub node is a node used to connect the graph data blocks, and thus, the hub node does not belong to any graph data block. When updating the node feature representation of each node in the graph data block, the node feature representation of the hub node is not updated. Based on this, the second processor can update the node feature representation of each hub node separately.

[0104] As can be seen from the above, nodes with a degree higher than a preset threshold can be selected from each node in the original graph data as hub nodes used to connect communities. Each neighbor node of the hub node can be used as a starting node, and other nodes connected to the neighbor node can be used as associated nodes of the neighbor node by accessing the associated nodes. In this way, the neighbor node and the associated nodes of the neighbor node can be divided out as a graph data block of the original graph data, and node updating processing can be performed on each graph data block. In this way, redundant calculations caused by directly using the feature matrix corresponding to all nodes in the original graph data for calculation can be avoided, thereby improving the data processing efficiency.

[0105] It should be noted that the data size of the original graph data is often large, and thus, when directly updating the original graph data, the original graph data cannot be loaded into the memory at one time, which results in a large number of swap-in and swap-out operations of the memory and a large number of redundant operations in the processing process. Therefore, the processing efficiency of the original graph data is greatly reduced.

[0106] And through the above method, the internal relationship between part of the nodes in the original graph data can be used to block the original graph data, so that the original graph data can be updated for each graph data block, thereby reducing the redundant calculation amount, and part of the data of the original graph data can be loaded into the memory each time, thereby improving the update efficiency of the original graph data.

[0107] For example, in a social relationship network graph data, the internal relationship between the nodes in the above graph data block can correspond to people working in the same institute, and for example, in a paper citation network, the internal relationship between the nodes in the above graph data block can correspond to papers published in the same series conference.

[0108] In order to further illustrate the above-mentioned graph structure-aware graph neural network hardware acceleration device, the present specification also provides a method for processing data by the above-mentioned graph structure-aware graph neural network hardware acceleration device, as shown in Figure 5 .

[0109] Figure 5 A schematic diagram of a graph structure-aware graph neural network hardware acceleration method provided in the present specification includes the following steps:

[0110] S501: The first processor determines whether the degree of each node contained in the original graph data exceeds a preset threshold;

[0111] S502: If yes, determine the node as a hub node, and for each neighbor node of the hub node, determine other nodes in the original graph data that have a connection relationship with the neighbor node as the associated nodes of the neighbor node through multiple rounds of node queries;

[0112] S503: According to the neighbor node and the associated nodes of the neighbor node, determine the graph data block of the original graph data, so that the second processor updates the node feature representation of each node contained in the graph data block according to the node feature representation of each neighbor node of the node in the graph data block, to obtain the updated feature representation of the node, and updates the original graph data according to the updated feature representation of the node and other nodes.

[0113] The first processor determines whether the degree of each node contained in the original graph data exceeds a preset threshold, and if so, determines the node as a hub node. For each neighbor node of the hub node, the first processor determines other nodes having a connection relationship with the neighbor node in the original graph data as associated nodes of the neighbor node. The first processor determines a graph data block of the original graph data according to the neighbor node and the associated nodes of the neighbor node. The second processor updates the node feature representation of each node contained in the graph data block according to the node feature representations of the neighbor nodes of the node in the graph data block, to obtain an updated feature representation of the node. The original graph data is updated according to the updated feature representations of the node and other nodes.

[0114] For each neighbor node of the hub node, the neighbor node is taken as a starting node, and the associated nodes of the neighbor node are determined through multiple rounds of node queries.

[0115] For each round of node query, the first processor determines target nodes in the round of node query, and determines whether the target nodes have neighbor nodes. If so, the target nodes are taken as associated nodes of the starting node, and the neighbor nodes of the target nodes are taken as target nodes of the next round of node query. The target nodes are obtained by iteratively taking the starting node to the last round. When a preset first termination condition is met, the associated nodes of the starting node are obtained.

[0116] For each target node in each round of node query, the first processor determines whether the target node is contained in a preset global visited node set. If so, it is determined that the starting node has no associated nodes, and the visited neighbor node corresponding to the starting node is removed from the global visited node set. If not, the target node is determined to be the visited neighbor node corresponding to the starting node, and the target node is added to the global visited node set. The first processor determines whether the target nodes have neighbor nodes.

[0117] The first processor aggregates the node feature representations of at least part of the neighbor nodes of each node contained in the graph data block in the graph data block to obtain a sub-aggregated feature representation of the node. The second processor updates the node feature representation of the node according to each sub-aggregated feature representation of the node to obtain an updated feature representation of the node.

[0118] The task scheduler generates a first data processing task for the graph data block, and allocates the first data processing task to the processing units according to the load values of the processing units. The processing units aggregate the node feature representations of at least part of the neighbor nodes of each node contained in the graph data block in the graph data block to obtain a sub-aggregated feature representation of the node.

[0119] The second data processing task for the graph data block is generated by the task scheduler, and the second data processing task is allocated to the processing units according to the load values of the processing units, so that the processing units update the node feature representation of the node according to the sub-aggregated feature representation of the node in the node, to obtain the updated feature representation of the node.

[0120] For each processing unit, the task scheduler determines whether the load value of the processing unit exceeds a preset first load threshold. If yes, the processing units adjacent to the processing unit in position are determined as candidate processing units, at least one candidate processing unit with the lowest load value among the candidate processing units is determined as a target processing unit, and the first data processing task or the second data processing task being processed by the processing unit is allocated to the target processing unit.

[0121] For each processing unit, the task scheduler determines whether the difference between the load value of the processing unit and the load values of other processing units exceeds a preset second load threshold. If yes, the processing unit with the smallest load value is selected from the processing units as a target processing unit, and the first data processing task or the second data processing task being processed by the processing unit is allocated to the target processing unit.

[0122] For each processing unit, the task scheduler determines whether the difference between the load value of the processing unit and the load values of other processing units exceeds a preset second load threshold. If yes, the first data processing task or the second data processing task being processed by the processing unit is split to obtain sub-data processing tasks, and the sub-data processing tasks are allocated to the processing unit with the smallest load value.

[0123] For each node included in the graph data block, the updated feature representation of the node is determined through multiple rounds of iteration.

[0124] For each round of iteration, the to-be-updated node feature representation of the node is determined, the to-be-updated node feature representation is updated according to the aggregated feature representation corresponding to the node determined in the last round of iteration, to obtain the updated feature representation corresponding to the node in the round of iteration, and the updated feature representation corresponding to the node in the round of iteration is taken as the to-be-updated node feature representation in the next round of iteration. The aggregated feature representation is used to represent the aggregation result of each neighbor node of the node in the graph data block. The to-be-updated node feature representation is obtained by iterating the node feature representation of the node to the last round. When a preset second termination condition is met, the updated feature representation of the node is obtained.

[0125] As can be seen from the above, nodes with a degree higher than a preset threshold can be selected from each node in the original graph data to serve as hub nodes connecting various communities. Then, each neighbor node of the hub node can be used as a starting node. By accessing other nodes that have connections with the neighbor node, these nodes can be identified as associated nodes of the neighbor node. This allows the neighbor node and its associated nodes to be separated into graph data blocks, which are then used as graph data segments in the original graph data. Node update processing is then performed on each graph data segment. This avoids redundant calculations caused by directly using the feature matrices corresponding to all nodes in the original graph data, thereby improving data processing efficiency.

[0126] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 5 One method provided.

[0127] This instruction manual also provides Figure 6 The one shown corresponds to Figure 5 A schematic diagram of the structure of an electronic device. (e.g.) Figure 6 As shown, at the hardware level, this electronic device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then runs it to achieve the above. Figure 1 The method.

[0128] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0129] In the 1990s, it was quite obvious to distinguish whether an improvement in a technology was in hardware (e.g., improvement in circuit structures of diodes, transistors, switches, etc.) or in software (improvement in method flow). However, as technology has evolved, many improvements in method flow today can be considered as direct improvements in hardware circuit structures. Designers almost always obtain the corresponding hardware circuit structures by programming the improved method flow into hardware circuits. Therefore, it cannot be said that an improvement in a method flow cannot be implemented by hardware entity modules. For example, a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)) is an integrated circuit whose logic function is determined by user programming of the device. A digital system is "integrated" on a PLD by the designer programming it, rather than by asking a chip manufacturer to design and fabricate a custom integrated circuit chip. Moreover, instead of manually fabricating integrated circuit chips, this programming is now mostly implemented by "logic compiler" software, which is similar to software compilers used in program development, and the original code to be compiled is written in a specific programming language, which is called a hardware description language (HDL), and there are many such languages, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., and the most commonly used are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should be aware that, as long as the method flow is logically programmed in the above-mentioned hardware description languages and programmed into an integrated circuit, a hardware circuit implementing the logical method flow can be easily obtained.

[0130] The controller can be implemented in any suitable way, for example, the controller can take the form of a microprocessor or processor and a computer readable medium storing computer readable program code, such as software or firmware, executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller and an embedded microcontroller, examples of which include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicone Labs C8051F320, the memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also know that, in addition to being implemented in pure computer readable program code, the controller can equally well be implemented to perform the same functions using logic gates, switches, an application specific integrated circuit, a programmable logic controller and an embedded microcontroller, etc. by means of a logical programming of the method steps. The controller can thus be considered as a hardware component, and the means comprised therein for performing the various functions can be considered as structures within the hardware component. Alternatively, the means for performing the various functions can even be considered as both a software module implementing the method and a structure within the hardware component.

[0131] The systems, apparatuses, modules or units illustrated by the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0132] For the sake of description, the above apparatuses are described in various units by functions respectively. Of course, the functions of the units can be implemented in one or more software and / or hardware in implementing the present specification.

[0133] Those skilled in the art will understand that the embodiments of the present specification can be provided as a method, a system or a computer program product. Therefore, the present specification can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present specification can take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0134] The specification is presented with reference to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing element or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagram and / or block diagram in the flow diagrams and / or block diagrams can represent one or more of any appropriate circuitry configured to perform the specified functions. In this regard, one or more flow diagrams and / or block diagrams in the flow diagrams and / or block diagrams can represent a means for performing the specified functions. Figure 1 The flow diagram and / or block diagram in the flow diagrams and / or block diagrams can represent one or more of any appropriate circuitry configured to perform the specified functions. In this regard, one or more flow diagrams and / or block diagrams in the flow diagrams and / or block diagrams can represent a means for performing the specified functions.

[0135] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagram and / or block diagram in the flow diagrams and / or block diagrams can represent one or more of any appropriate circuitry configured to perform the specified functions. In this regard, one or more flow diagrams and / or block diagrams in the flow diagrams and / or block diagrams can represent a means for performing the specified functions. Figure 1 The flow diagram and / or block diagram in the flow diagrams and / or block diagrams can represent one or more of any appropriate circuitry configured to perform the specified functions. In this regard, one or more flow diagrams and / or block diagrams in the flow diagrams and / or block diagrams can represent a means for performing the specified functions.

[0136] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flow diagrams and / or block diagrams block or blocks. Figure 1 The flow diagram and / or block diagram in the flow diagrams and / or block diagrams can represent one or more of any appropriate circuitry configured to perform the specified functions. In this regard, one or more flow diagrams and / or block diagrams in the flow diagrams and / or block diagrams can represent a means for performing the specified functions. Figure 1 The flow diagram and / or block diagram in the flow diagrams and / or block diagrams can represent one or more of any appropriate circuitry configured to perform the specified functions. In this regard, one or more flow diagrams and / or block diagrams in the flow diagrams and / or block diagrams can represent a means for performing the specified functions.

[0137] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0138] The memory can include non-persistent memory and / or persistent memory, such as flash memory, or other non-volatile memory, among others. The memory is an example of computer-readable media.

[0139] Computer-readable media includes permanent and non-permanent, movable and non-movable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer-readable media does not include transitory media such as modulated data signals and carriers.

[0140] It should also be noted that the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or apparatus that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0141] Those skilled in the art will appreciate that embodiments of the present specification can be provided as methods, systems or computer program products. Therefore, the present specification can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Moreover, the present specification can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0142] The present specification can be described in the general context of computer-executable instructions, such as program modules, executed by computers. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The present specification can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in both local and remote computer storage media including storage devices.

[0143] The various embodiments described in this specification are described using a numbering of embodiments approach: these are each individually integrated contributions pertaining to different aspects of the description. For each embodiment, the description focuses on the differences from the other embodiments. In particular, the description of the system embodiments is relatively brief, as the system embodiments are largely analogous to the method embodiments. The relevant parts of the description of the method embodiments are therefore referred to.

[0144] The above description is embodied in the form of embodiments only and is not intended to limit the present specification. The present specification can be variously changed and modified by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification should be included in the scope of the claims of the present specification.

Claims

1. A graph structure-aware graph data processing system, characterized in that, The graph data processing system comprises a first processor and a second processor; The first processor is configured to determine, for each node included in original graph data, whether a degree of the node exceeds a preset threshold, and if so, determine the node as a pivot node, and for each neighbor node of the pivot node, determine, through multiple rounds of node query, other nodes having a connection relationship with the neighbor node in the original graph data as associated nodes of the neighbor node, and perform block processing on the original graph data according to the neighbor node and the associated nodes of the neighbor node, to obtain a graph data block of the original graph data, and load the graph data block into a memory; The second processor is configured to obtain the graph data block from the memory, and for each node included in the graph data block, update a node feature representation of the node according to node feature representations of neighbor nodes of the node in the graph data block, to obtain an updated feature representation of the node, and perform update processing on the original graph data according to the updated feature representations of the node and other nodes.

2. The graph data processing system of claim 1, wherein, The first processor is configured to, for each neighbor node of the pivot node, take the neighbor node as a starting node, and determine associated nodes of the neighbor node through multiple rounds of node query; wherein For each round of node query, determine target nodes in the round of node query, determine whether there is an unvisited node in neighbor nodes of the target nodes, if so, take the unvisited node as an associated node of the starting node, set the unvisited node as a visited node, and take the unvisited node as a target node of a next round of node query, the target nodes being obtained by iteration of the starting node to a previous round; After determining that a preset first termination condition is met, obtain the associated nodes of the starting node.

3. The graph data processing system of claim 2, wherein, The first processor is configured to, for each target node in each round of node query, determine whether the target node is included in a preset global set of visited nodes, if not, determine that the target node is a visited neighbor node corresponding to the starting node, and add the target node to the global set of visited nodes, if so, determine that the starting node has no associated node, and remove a visited neighbor node corresponding to the starting node from the global set of visited nodes.

4. The graph data processing system of claim 1, wherein, The second processor comprises at least one processing unit; At least some of the processing units are configured to, for each node included in the graph data block, aggregate node feature representations of at least some neighbor nodes of the node in the graph data block, to obtain a sub-aggregated feature representation of the node; and Other processing units are configured to update the node feature representation of the node according to the sub-aggregated feature representations of the node, to obtain an updated feature representation of the node.

5. The graph data processing system of claim 4, wherein, The graph data processing system further comprises a task scheduler. The task scheduler is configured to generate a first data processing task for the graph data block, and distribute the first data processing task to the processing units according to the load values of the processing units, the first data processing task being configured to aggregate node feature representations of partial nodes; and The task scheduler is configured to generate a second data processing task for the graph data block, and distribute the second data processing task to the processing units according to the load values of the processing units, the second data processing task being configured to update a node feature representation of at least one node in the graph data block.

6. The graph data processing system of claim 5, wherein, The task scheduler is configured to, for each processing unit, determine whether the load value of the processing unit exceeds a preset first load threshold, and if so, determine, as candidate processing units, processing units adjacent to the processing unit in the processing units, determine, as a target processing unit, at least one candidate processing unit having the lowest load value among the candidate processing units, and distribute the first data processing task or the second data processing task being processed by the processing unit to the target processing unit.

7. The graph data processing system of claim 5, wherein, The task scheduler is configured to, for each processing unit among the processing units, determine whether a difference between the load value of the processing unit and the load values of other processing units exceeds a preset second load threshold, and if so, split the first data processing task or the second data processing task being processed by the processing unit to obtain sub-data processing tasks, and distribute the sub-data processing tasks to processing units having the lowest load values.

8. The graph data processing system of claim 1, wherein, The second processor is configured to, for each node included in the graph data block, determine an updated feature representation of the node through multiple rounds of iteration; wherein For each round of iteration, determine a node feature representation to be updated of the node, update the node feature representation to be updated according to an aggregated feature representation corresponding to the node determined in a previous round of iteration to obtain an updated feature representation corresponding to the node in the round of iteration, and take the updated feature representation corresponding to the node in the round of iteration as the node feature representation to be updated in a next round of iteration, the aggregated feature representation being configured to represent an aggregation result of neighbor nodes of the node in the graph data block, and the node feature representation to be updated being obtained by iterating a node feature representation of the node to the previous round; When it is determined that a preset second termination condition is met, the updated feature representation of the node is obtained.

9. A graph structure-aware graph data processing method, characterized by, The method is applied to a graph structure-aware graph data processing system, the graph structure-aware graph data processing system including a first processor and a second processor, and the method includes: The first processor is configured to, for each node included in original graph data, determine whether a degree of the node exceeds a preset threshold; If so, determine the node as a pivot node, and for each neighbor node of the pivot node, determine, through multiple rounds of node querying, other nodes having a connection relationship with the neighbor node in the original graph data as associated nodes of the neighbor node. According to the neighbor node and the associated node of the neighbor node, the original graph data is processed in blocks to obtain a graph data block of the original graph data, and the graph data block is loaded into a memory, so that the second processor updates a node feature representation of each node included in the graph data block according to the node feature representations of neighbor nodes of the node in the graph data block, to obtain an updated feature representation of the node, and updates the original graph data according to the updated feature representations of the node and other nodes.

10. The method of claim 9, wherein, For each neighbor node of the hub node, other nodes having a connection relationship with the neighbor node in the original graph data are determined as associated nodes of the neighbor node through multiple rounds of node queries, specifically including: For each neighbor node of the hub node, the neighbor node is taken as a starting node, and the associated nodes of the neighbor node are determined through multiple rounds of node queries; wherein, For each round of node query, each target node in the round of node query is determined, it is judged whether the target nodes have neighbor nodes, if yes, the target nodes are taken as associated nodes of the starting node, and neighbor nodes of the target nodes are taken as target nodes of a next round of node query, the target nodes being obtained by iterating the starting node to a previous round; After it is determined that a preset first termination condition is met, the associated nodes of the starting node are obtained.

11. The method of claim 10, wherein, It is judged whether the target nodes have neighbor nodes, specifically including: For each target node in each round of node query, it is judged whether the target node is included in a preset global visited node set; If yes, it is determined that the starting node has no associated node, and a visited neighbor node corresponding to the starting node is removed from the global visited node set; If no, it is determined that the target node is a visited neighbor node corresponding to the starting node, the target node is added to the global visited node set, and it is judged whether the target nodes have neighbor nodes.

12. The method of claim 9, wherein, The second processor includes at least one processing unit; According to the node feature representations of neighbor nodes of the node in the graph data block, the node feature representation of the node is updated to obtain an updated feature representation of the node, specifically including: Through at least part of the processing units, for each node included in the graph data block, node feature representations of at least part of neighbor nodes of the node in the graph data block are aggregated to obtain a sub-aggregated feature representation of the node; and Through other processing units, according to the sub-aggregated feature representations of the node, the node feature representation of the node is updated to obtain an updated feature representation of the node.

13. The method of claim 12, wherein, The graph data processing system further includes a task scheduler; Through at least part of the processing units, for each node included in the graph data block, node feature representations of at least part of neighbor nodes of the node in the graph data block are aggregated to obtain a sub-aggregated feature representation of the node, specifically including: generating, by the task scheduler, a first data processing task for the graph data block, and distributing the first data processing task to the processing units according to the load values of the processing units, so that the processing units aggregate, for each node in the graph data block, a node feature representation of at least part of neighbor nodes of the node in the graph data block, to obtain a sub-aggregated feature representation of the node; updating, by other processing units, the node feature representation of the node according to the sub-aggregated feature representations of the node, to obtain an updated feature representation of the node, specifically including: generating, by the task scheduler, a second data processing task for the graph data block, and distributing the second data processing task to the processing units according to the load values of the processing units, so that the processing units update the node feature representation of the node according to the sub-aggregated feature representations of the node, to obtain an updated feature representation of the node.

14. The method of claim 13, wherein, The method further includes: For each processing unit, determining, by the task scheduler, whether the load value of the processing unit exceeds a preset first load threshold, if so, determining, as candidate processing units, processing units adjacent to the processing unit in the processing units, and determining, as a target processing unit, at least one candidate processing unit with the lowest load value among the candidate processing units, and distributing the first data processing task or the second data processing task being processed by the processing unit to the target processing unit.

15. The method of claim 13, wherein, The method further includes: For each processing unit among the processing units, determining, by the task scheduler, whether a difference between the load value of the processing unit and the load values of other processing units exceeds a preset second load threshold, if so, splitting the first data processing task or the second data processing task being processed by the processing unit to obtain sub-data processing tasks, and distributing the sub-data processing tasks to a processing unit with the smallest load value among the processing units.

16. The method of claim 9, wherein, For each node in the graph data block, updating the node feature representation of the node according to the node feature representations of neighbor nodes of the node in the graph data block, to obtain an updated feature representation of the node, specifically including: For each node in the graph data block, determining, by multiple iterations, an updated feature representation of the node; wherein, For each iteration, determining a to-be-updated node feature representation of the node, updating the to-be-updated node feature representation according to an aggregated feature representation of the node corresponding to the last iteration, to obtain an updated feature representation of the node corresponding to the iteration, and taking the updated feature representation of the node corresponding to the iteration as a to-be-updated node feature representation in the next iteration, the aggregated feature representation being used to represent an aggregation result of neighbor nodes of the node in the graph data block, and the to-be-updated node feature representation being obtained by iterating the node feature representation of the node to the last iteration; When it is determined that a preset second termination condition is met, the updated feature representation of the node is obtained.

17. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is executed by a processor to implement the method in any one of claims 9-16.

18. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the method in any one of claims 9-16.

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