Junction field effect transistor preparation method and junction field effect transistor

Abstract

The present invention relates to a method for fabricating a junction field-effect transistor and a junction field-effect transistor. The method comprises: forming three sequentially arranged doped regions within a first semiconductor material layer, including a central first-type doped region and second-type doped regions on either side of the first-type doped region; the conductivity type of each of the three doped regions is opposite to that of the first semiconductor material layer, and the doping concentration of the second-type doped region is less than the doping concentration of the first-type doped region; forming a gate in the first-type doped region; and forming a source and drain in the second-type doped region. The junction field-effect transistor fabrication method and junction field-effect transistor provided by the present invention have a higher BV.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for preparing a junction field effect transistor and the junction field effect transistor. Background Art

[0002] Bipolar-CMOS-DMOS (BCD) is a key power integrated circuit manufacturing technology. It primarily integrates high-voltage power devices such as bipolar transistors (BNTs), complementary metal oxide semiconductors (CMOS), and double-diffused metal oxide semiconductor (DMOS) field-effect transistors (DMOS), along with various resistors, capacitors, and diodes, onto a single chip. The BCD process offers the advantage of combining three distinct manufacturing technologies on a single chip: bipolar transistors for high-precision analog signal processing, complementary metal oxide semiconductor (CMOS) transistors for digital control circuits, and DMOS transistors for power supplies and high-voltage switching devices. This integration offers numerous advantages, such as improved reliability, reduced electromagnetic interference (EMI), and reduced chip size. The 120V BCD process platform has been widely adopted in mobile devices, home appliances, displays, automobiles, data centers, and other fields.

[0003] Sometimes, Junction Field-Effect Transistor (JFET) is parasitically integrated in the BCD platform due to its following advantages:

[0004] 1.JFETs have very high input impedance, which allows for a high degree of isolation between the input and output circuits.

[0005] 2. JFET does not have the inherent noise of electron tubes and transistors.

[0006] 3. JFET has a negative temperature coefficient, which reduces the risk of thermal runaway.

[0007] 4. JFETs have very high power gain, which eliminates the need for a driver stage.

[0008] Existing JFET structures such as Figure 1As shown, it mainly consists of a P-type substrate 10, a P-type epitaxial layer 9, an N-type channel 8, a highly doped N-type region 5, drain 1 and source 3 electrodes at both ends of the N-type channel, a P-type region 7, a highly doped P-type region 6, an extraction electrode gate 2, and an insulating layer 4. This structure is simple, but the electric field distribution is uneven. When parasitically integrated on an existing 120V BCD platform, the breakdown voltage (BV) is insufficient, or the device size is increased to meet the target requirements due to the increased BV. Summary of the Invention

[0009] In view of this, embodiments of the present application provide a method for manufacturing a junction field effect transistor and a junction field effect transistor to solve at least one problem existing in the background technology.

[0010] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0011] In a first aspect, an embodiment of the present application provides a method for preparing a junction field effect transistor, the method comprising:

[0012] forming three sequentially arranged doped regions in the first semiconductor material layer, including a first-type doped region in the middle and second-type doped regions on either side of the first-type doped region; the conductivity type of the three doped regions is opposite to the conductivity type of the first semiconductor material layer, and the doping concentration of the second-type doped region is less than the doping concentration of the first-type doped region;

[0013] A gate is formed in the first type doping region; and a source and a drain are respectively formed in the second type doping region.

[0014] Optionally, the doping depth of the second type doping region is greater than the doping depth of the first type doping region; the doping depth is the distance from the bottom of the doping region to the top surface of the first semiconductor material layer.

[0015] Optionally, after forming three sequentially arranged doped regions in the first semiconductor material layer, the method includes:

[0016] A first insulating layer is formed on a portion of the upper surface of the second-type doping region where the drain is predetermined to be formed, and the first insulating layer is located between the drain and the gate.

[0017] Optionally, after forming the first insulating layer on a portion of the upper surface of the second-type doping region where the drain is to be formed, the method includes:

[0018] A first conductive material layer is formed, wherein one end of the first conductive material layer covers a portion of the first insulating layer, and the other end of the first conductive material layer extends toward the gate along a direction from the drain to the gate and contacts the first type doping region.

[0019] Optionally, the first conductive material layer includes a first part and a second part separated from each other, the first part is located above the first insulating layer, one end of the second part covers a partial area of the first insulating layer, and the other end extends toward the gate along the direction from the drain to the gate and contacts the first type doping region.

[0020] Optionally, the method further includes:

[0021] forming a second insulating layer, wherein the second insulating layer covers the first type doping region, the second type doping region, the first insulating layer and the first conductive material layer;

[0022] A second conductive material layer is formed on the surface of the second insulating layer and in a longitudinal direction corresponding to the first conductive material layer, where the longitudinal direction is the thickness direction of the first semiconductor material layer.

[0023] In a second aspect, an embodiment of the present application provides a junction field effect transistor, comprising:

[0024] a first semiconductor material layer;

[0025] a first-type doped region formed in the first semiconductor material layer, having a conductivity type opposite to that of the first semiconductor material layer;

[0026] a second type doped region formed in the first semiconductor material layer, one on each side of the first type doped region; the conductivity type of the second type doped region is the same as the conductivity type of the first type doped region; and the doping concentration of the second type doped region is less than the doping concentration of the first type doped region;

[0027] a gate formed in the first type doped region;

[0028] a source electrode formed in one of the second-type doping regions;

[0029] The drain is formed in another second-type doping region outside the source.

[0030] Optionally, the doping depth of the second type doping region is greater than the doping depth of the first type doping region; the doping depth is the distance from the bottom of the doping region to the top surface of the first semiconductor material layer.

[0031] Optionally, the junction field effect transistor further includes:

[0032] A first insulating layer is formed on a portion of the upper surface of the second-type doping region and is located between the drain and the gate.

[0033] Optionally, the junction field effect transistor further includes:

[0034] The first conductive material layer has one end covering a portion of the first insulating layer, and the other end extending toward the gate along a direction from the drain to the gate and contacting the first type doping region.

[0035] Optionally, the first conductive material layer includes a first part and a second part separated from each other, the first part is located above the first insulating layer, one end of the second part covers a partial area of the first insulating layer, and the other end extends toward the gate along the direction from the drain to the gate and contacts the first type doping region.

[0036] Optionally, the junction field effect transistor further includes:

[0037] a second insulating layer covering the first type doping region, the second type doping region, the first insulating layer and the first conductive material layer;

[0038] The second conductive material layer is formed on the surface of the second insulating layer and corresponds to the first conductive material layer in a longitudinal direction, where the longitudinal direction is the thickness direction of the first semiconductor material layer.

[0039] The present invention provides a method for fabricating a junction field-effect transistor and a junction field-effect transistor. The method comprises: forming three sequentially arranged doped regions within a first semiconductor material layer, including a first-type doped region in the middle and second-type doped regions on either side of the first-type doped region; the conductivity type of each of the three doped regions is opposite to the conductivity type of the first semiconductor material layer, and the doping concentration of the first-type doped region is greater than the doping concentration of the second-type doped region; forming a gate in the first-type doped region; and forming a source and a drain in the second-type doped region. The method comprises forming the first-type doped region in a region where the gate is to be formed, forming the second-type doped region in a region where the drain or source is to be formed, and setting the doping concentration of the first-type doped region to be greater than that of the second-type doped region. Thus, the first-type doped region can attract more electric field concentration, reducing the tendency of electric field concentration in the drain region to occur, making the electric field distribution more uniform, and improving the BV of the junction field-effect transistor without increasing the volume. Thus, the method for fabricating a junction field-effect transistor and the junction field-effect transistor provided by the present invention have a higher BV without increasing the volume.

[0040] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0042] Figure 1 is a schematic diagram of a junction field effect transistor in the prior art;

[0043] Figure 2 A schematic flow chart of a method for preparing a junction field effect transistor according to an embodiment of the present application;

[0044] Figure 3-Figure 7 Schematic diagram of the semiconductor structure in each process of the method for preparing a junction field effect transistor provided in an embodiment of the present application.

[0045] Description of reference numerals:

[0046] 31. First semiconductor material layer; 32. Substrate; 41. First type doped region; 42. Second type doped region; 51. Gate region; 52. Gate electrode; 53. Source region; 54. Source electrode; 55. Drain region; 56. Drain electrode; 57. Lightly doped region; 61. First insulating layer; 62. First conductive material layer; 70. Second insulating layer; 80. Second conductive material layer. DETAILED DESCRIPTION

[0047] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0048] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0049] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0050] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0051] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0052] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] In order to fully understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0054] The present invention provides a method for preparing a junction field effect transistor. Figure 2 A schematic diagram of a process for preparing a junction field effect transistor according to an embodiment of the present application is shown. Figure 3-Figure 7 Schematic diagram of the semiconductor structure of each process in the method for preparing a junction field effect transistor provided in the embodiment of the present application, combined with Figures 2 to 7 , the method comprising:

[0055] Step 201: forming three sequentially arranged doped regions in a first semiconductor material layer 31, including a first-type doped region 41 in the middle and second-type doped regions 42 on either side of the first-type doped region 41; the conductivity type of the three doped regions is opposite to the conductivity type of the first semiconductor material layer 31, and the doping concentration of the second-type doped region 42 is lower than the doping concentration of the first-type doped region 41;

[0056] Step 202 : forming a gate in the first-type doping region 41 ; and forming a source and a drain in the second-type doping region 42 .

[0057] The method for preparing a junction field effect transistor provided in the embodiment of the present application can be used for the preparation of a junction field effect transistor in a BCD platform, especially for a 120V BCD. The following mainly introduces the junction field effect transistor in the BCD platform as an example. It can be understood that the method for preparing a junction field effect transistor in the embodiment of the present application can also be used to prepare a junction field effect transistor alone, and can also be used to prepare other semiconductor devices. The method for preparing a junction field effect transistor in the embodiment of the present application is used to form a partial structure of a junction field effect transistor, so the accompanying drawings only show a partial structure, and other areas may be partially shown or not shown.

[0058] In the above step 201, see Figure 3 The first semiconductor material layer 31 may be an epitaxial layer (EPI) formed on the substrate 32. The first semiconductor material layer 31 has a conductivity type, which may be P-type or N-type. The conductivity type may be formed by doping the first semiconductor material layer 31 with P-type or N-type impurities.

[0059] See also Figure 4The doped region, generally also referred to as the well region, is doped with impurities of opposite conductivity type to the epitaxial layer on the basis of the epitaxial layer. For example, if the conductivity type of the epitaxial layer is P, N-type impurities are doped. Conversely, P-type impurities are doped. The doped region can be made into a mask through a photolithography process, and doping is performed in the area not blocked by the mask. Specifically, a mask material can be first deposited on the first semiconductor material layer 31, and then a preset formation position of the doped region can be defined in the mask material through a photolithography and etching process, thereby forming a patterned mask layer. This process is well known to those skilled in the art and will not be described in detail here.

[0060] The doping concentration of the second-type doping region 42 is lower than that of the first-type doping region 41. That is, the doping concentration of the first-type doping region 41 is higher. This makes the first-type doping region 41 more susceptible to electric field concentration, and therefore the gate region 51 more susceptible to electric field concentration. This reduces the tendency of electric field concentration in the drain region 55, making the electric field distribution more uniform and reducing the possibility of the drain region 55 becoming a weak area for voltage breakdown. This improves the BV of the junction field-effect transistor without increasing its volume.

[0061] The first type doping region 41 and the second type doping region 42 can be formed by either a diffusion process or an ion implantation process, which is not limited herein.

[0062] In the above step 202, forming a gate in the first type doping region 41 may include forming a gate region 51 and a gate electrode 52. This process is well known to people in this technical field and will not be repeated here. Similarly, forming a source and a drain in the second type doping region 42 respectively also includes forming a source region 53, a source electrode 54, a drain region 55 and a drain electrode 56.

[0063] It can be understood that the gate region 51 can be a heavily doped region having the same conductivity type as the first semiconductor material layer 31 (i.e., opposite to the first type doped region 41) and a doping concentration greater than that of the first semiconductor material layer 31. The source region 53 can be a heavily doped region having the same conductivity type as the first semiconductor material layer 31 (i.e., opposite to the second type doped region 42) and a doping concentration greater than that of the first semiconductor material layer 31. The drain region 55 can be a heavily doped region having the same conductivity type as the first semiconductor material layer 31 (i.e., opposite to the second type doped region 42) and a doping concentration greater than that of the first semiconductor material layer 31.

[0064] It can be understood that, as in the prior art, before forming the gate region 51, it is necessary to form a lightly doped region 57 in the first type doping region 41, which has the same conductivity type as the gate region 51 (i.e., the conductivity type is opposite to that of the first type doping region 41) but has a lower doping concentration than the gate region 51, and form the gate region 51 in the lightly doped region 57. Figure 5 .

[0065] In some embodiments, the doping depth of the second type doping region 42 is greater than the doping depth of the first type doping region 41 ; the doping depth is the distance from the bottom of the doping region to the top surface of the first semiconductor material layer 31 .

[0066] Since the doping depth of the second type doping region 42 is greater, that is, the doping depth of the doping region where the drain or source is located is greater. Therefore, compared with the first type doping region 41, that is, the doping region described by the gate, the voltage per unit length or unit area of the second type doping region 42 is smaller, which reduces the possibility of the drain region 55 becoming a weak area for voltage breakdown. The BV of the junction field effect transistor is improved without increasing the volume. Furthermore, since the doping depth of the first type doping region 41 is shallower than the doping depth of the second type doping region 42, the ions of the first type doping region 41 can be depleted faster and the pinch-off can be completed faster during the process of the gate performing pinch-off control. Therefore, setting the doping depth of the first type doping region 41 to be relatively shallow can optimize the control effect of the gate.

[0067] The bottom of the doping region refers to the bottom of the doping region in a longitudinal direction, where the longitudinal direction is the same as the height direction of the substrate.

[0068] In some embodiments, see Figure 4 After forming three sequentially arranged doping regions in the first semiconductor material layer 31, the method includes:

[0069] A first insulating layer 61 is formed on a portion of the upper surface of the second-type doping region 42 where the drain is to be formed. The first insulating layer 61 is located between the drain and the gate.

[0070] It can be understood that the first insulating layer 61 can increase the creepage distance between the drain and the gate, reduce the electric field strength per unit length or unit area in the drain region 55, and improve the BV of the junction field-effect transistor. Furthermore, the first insulating layer 61 can cover the entire upper surface of the second-type doped region 42 in a first direction. The first direction is parallel to the upper surface of the second-type doped region 42 and perpendicular to the direction from the gate to the source.

[0071] The first insulating layer 61 can be an oxide layer formed by an oxidation process, such as silicon oxide. The first insulating layer 61 can perform an oxidation process on the upper surface of the second type doping region 42 to oxidize a portion of the second type doping region 42 close to the upper surface. Since the volume will increase slightly after oxidation, the first insulating layer 61 will protrude from the second type doping region 42. In this way, when moving along the upper surface of the second type doping region 42, it is necessary to bypass the first insulating layer 61, which increases the creepage distance. The oxidation process can be formed by the local oxidation isolation of silicon (LOCOS) technology.

[0072] It is understood that the first insulating layer 61 can also be made by a process other than oxidation, such as deposition, oxidation followed by deposition, etc.

[0073] In some embodiments, see Figure 6 After forming the first insulating layer 61 on a portion of the upper surface of the second-type doping region 42 where the drain is to be formed, the method includes:

[0074] A first conductive material layer 62 is formed. One end of the first conductive material layer 62 covers a portion of the first insulating layer 61 , and the other end extends toward the gate along a direction from the drain to the gate and contacts the first type doping region.

[0075] It is understandable that after the first insulating layer 61 is provided, the electric field strength per unit length or per unit area in the drain region 55 is reduced. However, a local electric field concentration phenomenon will form on the surface of the first insulating layer 61, which may sometimes become a breakdown weak area. Therefore, a first conductive material layer 62 is provided on the basis of the first insulating layer 61 to attract the electric field and disperse the electric field strength on the surface of the first insulating layer 61. Furthermore, one end of the first conductive material layer 62 can cover the entire first insulating layer 61 in the first direction, and the other end can cover the entire upper surface of the second type doping region 42 and the upper surface of the first type doping region 41 in the first direction.

[0076] Furthermore, in subsequent etching processes, the first conductive material layer 62 can also prevent the etchant or other corrosive agents from thinning the first insulating layer 61 , thereby reducing weak points in the first insulating layer 61 .

[0077] The material of the first conductive material layer 62 can be polysilicon. Polysilicon can easily obtain good conductivity through doping and has good compatibility with semiconductor materials such as silicon and silicon carbide. The first conductive material layer 62 can be formed by a deposition process.

[0078] In some embodiments, see Figure 6 The first conductive material layer 62 includes a first part and a second part separated from each other, the first part is located above the first insulating layer 61, one end of the second part covers a partial area of the first insulating layer 61, and the other end extends toward the gate along the direction from the drain to the gate and contacts the first type doping region.

[0079] The separation here is a spatial separation that also serves as an insulating barrier. The separation of the first and second portions can better block the movement of the electric field between the gate and drain. This reduces the electric field in the drain region 55 and reduces the likelihood that the drain region 55 will become a vulnerable area to voltage breakdown.

[0080] The first conductive material layer 62 is divided into the first portion and the second portion by a photolithography process, which will not be described in detail here.

[0081] In some embodiments, see Figure 7 , the method further comprises:

[0082] forming a second insulating layer 70 , wherein the second insulating layer 70 covers the first type doping region 41 , the second type doping region 42 , the first insulating layer 61 and the first conductive material layer 62 ;

[0083] A second conductive material layer 80 is formed on the surface of the second insulating layer 70 and in a longitudinal direction corresponding to the first conductive material layer 62 , where the longitudinal direction is the thickness direction of the first semiconductor material layer 31 .

[0084] In this embodiment, the second insulating layer 70 may be an isolation layer for dielectric (ILD) for insulating the semiconductor device from the outside world. The electrode passes through the ILD to connect the external power supply to the semiconductor device.

[0085] Similar to the first conductive material layer 62 attracting the electric field of the first insulating layer 61 , the second conductive material layer 80 can also attract the electric fields of the first insulating layer 61 and the first conductive material layer 62 to make the electric field distribution more uniform.

[0086] The second conductive material layer 80 can be made of conductive metal materials such as aluminum and copper. It should be noted that for growth compatibility, the first conductive material layer 62 cannot be made of conductive metal materials such as aluminum and copper, and can generally only be made of polysilicon or similar materials.

[0087] The present application also provides a junction field effect transistor, such as Figure 7As shown, the junction field effect transistor includes a first semiconductor material layer 31, a first type doping region 41, a second type doping region 42, a gate, a source and a drain, wherein:

[0088] The first-type doping region 41 is formed in the first semiconductor material layer 31 and has a conductivity type opposite to that of the first semiconductor material layer 31 ;

[0089] The second-type doping region 42 is formed in the first semiconductor material layer 31, with one on each side of the first-type doping region 41; the conductivity type of the second-type doping region 42 is the same as the conductivity type of the first-type doping region 41; and the doping concentration of the second-type doping region 42 is lower than the doping concentration of the first-type doping region 41;

[0090] The gate is formed in the first type doping region 41;

[0091] The source is formed in one of the second-type doping regions 42 ;

[0092] The drain is formed in another second-type doping region 42 outside the source.

[0093] In this embodiment, see Figure 3 The first semiconductor material layer 31 may be an epitaxial layer (EPI) formed on the substrate 32. The first semiconductor material layer 31 has a conductivity type, which may be P-type or N-type. The conductivity type may be formed by doping the first semiconductor material layer 31 with P-type or N-type impurities.

[0094] See also Figure 4 The doped region, generally also referred to as the well region, is doped with impurities of opposite conductivity type to the epitaxial layer on the basis of the epitaxial layer. For example, if the conductivity type of the epitaxial layer is P, N-type impurities are doped. Conversely, P-type impurities are doped. The doped region can be made into a mask through a photolithography process, and doping is performed in the area not blocked by the mask. Specifically, a mask material can be first deposited on the first semiconductor material layer 31, and then a preset formation position of the doped region can be defined in the mask material through a photolithography and etching process, thereby forming a patterned mask layer. This process is well known to those skilled in the art and will not be described in detail here.

[0095] The doping concentration of the second-type doping region 42 is lower than that of the first-type doping region 41. That is, the doping concentration of the first-type doping region 41 is higher. This makes the first-type doping region 41 more susceptible to electric field concentration, and therefore the gate region 51 more susceptible to electric field concentration. This reduces the tendency of electric field concentration in the drain region 55, making the electric field distribution more uniform and reducing the possibility of the drain region 55 becoming a weak area for voltage breakdown. This improves the BV of the junction field-effect transistor without increasing its volume.

[0096] The first type doping region 41 and the second type doping region 42 can be formed by either a diffusion process or an ion implantation process, which is not limited herein.

[0097] In this embodiment, forming a gate in the first type doping region 41 may include forming a gate region 51 and a gate electrode 52. This process is well known to people in this technical field and will not be described here in detail. Similarly, forming a source and a drain in the second type doping region 42 also includes forming a source region 53, a source electrode 54, a drain region 55 and a drain electrode 56.

[0098] It can be understood that the gate region 51 can be a heavily doped region having the same conductivity type as the first semiconductor material layer 31 (i.e., opposite to the first type doped region 41) and a doping concentration greater than that of the first semiconductor material layer 31. The source region 53 can be a heavily doped region having the same conductivity type as the first semiconductor material layer 31 (i.e., opposite to the second type doped region 42) and a doping concentration greater than that of the first semiconductor material layer 31. The drain region 55 can be a heavily doped region having the same conductivity type as the first semiconductor material layer 31 (i.e., opposite to the second type doped region 42) and a doping concentration greater than that of the first semiconductor material layer 31.

[0099] It can be understood that, as in the prior art, before forming the gate region 51, it is necessary to form a lightly doped region 57 in the first type doping region 41, which has the same conductivity type as the gate region 51 (i.e., the conductivity type is opposite to that of the first type doping region 41) but has a lower doping concentration than the gate region 51, and form the gate region 51 in the lightly doped region 57. Figure 5 .

[0100] In some embodiments, the doping depth of the second type doping region 42 is greater than the doping depth of the first type doping region 41 ; the doping depth is the distance from the bottom of the doping region to the top surface of the first semiconductor material layer 31 .

[0101] Because the doping depth of the second-type doped region 42 is greater, that is, the doping depth of the doped region where the drain or source is located is greater, the voltage per unit length or per unit area of the second-type doped region 42 is lower than that of the first-type doped region 41, i.e., the doped region of the gate. This reduces the possibility that the drain region 55 will become a weak area for voltage breakdown. This improves the BV of the junction field-effect transistor without increasing the volume.

[0102] Furthermore, because the doping depth of the first-type doping region 41 is shallower than that of the second-type doping region 42, the ions in the first-type doping region 41 can be depleted more quickly during the gate pinch-off control process, completing the pinch-off process more quickly. Therefore, setting the doping depth of the first-type doping region 41 relatively shallow can optimize the gate control effect.

[0103] The bottom of the doping region refers to the bottom of the doping region in a longitudinal direction, where the longitudinal direction is the same as the height direction of the substrate.

[0104] In some embodiments, the junction field effect transistor further comprises:

[0105] The first insulating layer 61 is formed on a portion of the upper surface of the second-type doping region 42 and is located between the drain and the gate.

[0106] It can be understood that the first insulating layer 61 can increase the creepage distance between the drain and the gate, reduce the electric field strength per unit length or unit area in the drain region 55, and improve the BV of the junction field-effect transistor. Furthermore, the first insulating layer 61 can cover the entire upper surface of the second-type doped region 42 in a first direction. The first direction is parallel to the upper surface of the second-type doped region 42 and perpendicular to the direction from the gate to the source.

[0107] The first insulating layer 61 can be an oxide layer formed by an oxidation process, such as silicon oxide. The first insulating layer 61 can perform an oxidation process on the upper surface of the second type doping region 42 to oxidize a portion of the second type doping region 42 close to the upper surface. Since the volume will increase slightly after oxidation, the first insulating layer 61 will protrude from the second type doping region 42. In this way, when moving along the upper surface of the second type doping region 42, it is necessary to bypass the first insulating layer 61, which increases the creepage distance. The oxidation process can be formed by the local oxidation isolation of silicon (LOCOS) technology.

[0108] It is understood that the first insulating layer 61 can also be made by a process other than oxidation, such as deposition, oxidation followed by deposition, etc.

[0109] In some embodiments, the junction field effect transistor further comprises:

[0110] The first conductive material layer 62 has one end covering a portion of the first insulating layer 61 , and the other end extending toward the gate along a direction from the drain to the gate and contacting the first type doping region.

[0111] It can be understood that after the first insulating layer 61 is provided, the electric field strength per unit length or per unit area in the drain region 55 is reduced. However, on the surface of the first insulating layer 61, a local electric field concentration phenomenon will be formed, which may sometimes become a breakdown weak area. Therefore, a first conductive material layer 62 is provided on the basis of the first insulating layer 61 to attract the electric field and disperse the electric field strength on the surface of the first insulating layer 61. Furthermore, one end of the first conductive material layer 62 may cover the entire first insulating layer 61 in the first direction, and the other end may cover the entire upper surface of the second type doping region 42 and the upper surface of the first type doping region 41 in the first direction. Furthermore, in subsequent etching processes, the first conductive material layer 62 may also prevent the etchant or other corrosive agents from thinning the first insulating layer 61, thereby reducing the weak points generated in the first insulating layer 61.

[0112] The material of the first conductive material layer 62 can be polysilicon. Polysilicon can easily obtain good conductivity through doping and has good compatibility with semiconductor materials such as silicon and silicon carbide. The first conductive material layer 62 can be formed by a deposition process.

[0113] In some embodiments, the first conductive material layer 62 includes a first portion and a second portion separated from each other, the first portion is located above the first insulating layer 61, one end of the second portion covers a partial area of the first insulating layer 61, and the other end extends toward the gate along the direction from the drain to the gate and contacts the first type doping region.

[0114] The separation here is a spatial separation that also serves as an insulating barrier. The separation of the first and second portions can better block the movement of the electric field between the gate and drain. This reduces the electric field in the drain region 55 and reduces the likelihood that the drain region 55 will become a vulnerable area to voltage breakdown.

[0115] The first conductive material layer 62 is divided into the first portion and the second portion by a photolithography process, which will not be described in detail here.

[0116] In some embodiments, the junction field effect transistor further comprises:

[0117] a second insulating layer 70 covering the first type doping region 41 , the second type doping region 42 , the first insulating layer 61 and the first conductive material layer 62 ;

[0118] The second conductive material layer 80 is formed on the surface of the second insulating layer 70 and corresponds to the first conductive material layer 62 in the longitudinal direction. The longitudinal direction is the thickness direction of the first semiconductor material layer 31 .

[0119] In this embodiment, the second insulating layer 70 may be an isolation layer for dielectric (ILD) for insulating the semiconductor device from the outside world. The electrode passes through the ILD to connect the external power supply to the semiconductor device.

[0120] Similar to the first conductive material layer 62 attracting the electric field of the first insulating layer 61 , the second conductive material layer 80 can also attract the electric fields of the first insulating layer 61 and the first conductive material layer 62 to make the electric field distribution more uniform.

[0121] The second conductive material layer 80 can be made of conductive metal materials such as aluminum and copper. It should be noted that for growth compatibility, the first conductive material layer 62 cannot be made of conductive metal materials such as aluminum and copper, and can generally only be made of polysilicon or similar materials.

[0122] It should be noted that the embodiments of the junction field effect transistors provided in this application and the embodiments of the method for preparing the junction field effect transistors are of the same concept; the various technical features in the technical solutions described in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the combination of the various technical features of the junction field effect transistors provided in the embodiments of this application can already solve the technical problems to be solved by this application; therefore, the junction field effect transistors provided in the embodiments of this application are not limited by the method for preparing the junction field effect transistors provided in the embodiments of this application, and any junction field effect transistors prepared by the preparation method that can form the junction field effect transistor structure provided in the embodiments of this application are within the scope of protection of this application.

[0123] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations of the claims. Various modifications and variations may be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form additional embodiments of the present invention that may not be explicitly described. Therefore, the above embodiments merely illustrate several implementations of the present invention and do not limit the scope of protection of the patent of this invention.

Claims

1. A method for preparing a junction field effect transistor, characterized in that: The method comprises: forming three sequentially arranged doped regions in the first semiconductor material layer, including a first-type doped region in the middle and second-type doped regions on either side of the first-type doped region; the conductivity type of the three doped regions is opposite to the conductivity type of the first semiconductor material layer, and the doping concentration of the second-type doped region is less than the doping concentration of the first-type doped region; A gate is formed in the first type doping region; a source is formed in one of the second type doping regions, and a drain is formed in another second type doping region; the forming of the gate includes forming a gate region and a gate electrode, the forming of the source includes forming a source region and a source electrode, and the forming of the drain includes forming a drain region and a drain electrode.

2. The method for preparing a junction field effect transistor according to claim 1, wherein: The doping depth of the second type doping region is greater than the doping depth of the first type doping region; the doping depth is the distance from the bottom of the doping region to the top surface of the first semiconductor material layer.

3. The method for preparing a junction field effect transistor according to claim 1 or 2, wherein: After forming three sequentially arranged doped regions in the first semiconductor material layer, the method includes: A first insulating layer is formed on a portion of the upper surface of the second-type doping region where the drain is predetermined to be formed, and the first insulating layer is located between the drain and the gate.

4. The method for preparing a junction field effect transistor according to claim 3, wherein: After forming a first insulating layer on a portion of the upper surface of the second-type doping region where the drain is to be formed, the method includes: A first conductive material layer is formed, wherein one end of the first conductive material layer covers a portion of the first insulating layer, and the other end of the first conductive material layer extends toward the gate along a direction from the drain to the gate and contacts the first type doping region.

5. The method for preparing a junction field effect transistor according to claim 4, wherein: The first conductive material layer includes a first part and a second part separated from each other, the first part is located above the first insulating layer, one end of the second part covers a partial area of the first insulating layer, and the other end extends toward the gate along the direction from the drain to the gate and contacts the first type doping region.

6. The method for preparing a junction field effect transistor according to claim 5, wherein: The method further comprises: forming a second insulating layer, wherein the second insulating layer covers the first type doping region, the second type doping region, the first insulating layer and the first conductive material layer; A second conductive material layer is formed on the surface of the second insulating layer and in a longitudinal direction corresponding to the first conductive material layer, where the longitudinal direction is the thickness direction of the first semiconductor material layer.

7. A junction field effect transistor, characterized in that: include: a first semiconductor material layer; a first-type doped region formed in the first semiconductor material layer, having a conductivity type opposite to that of the first semiconductor material layer; a second type doped region formed in the first semiconductor material layer, one on each side of the first type doped region; the conductivity type of the second type doped region is the same as the conductivity type of the first type doped region; and the doping concentration of the second type doped region is less than the doping concentration of the first type doped region; a gate formed in the first-type doping region, the gate comprising a gate region and a gate electrode; a source electrode formed in one of the second-type doping regions, the source electrode comprising a source region and a source electrode; A drain is formed in another second-type doping region outside the source; the drain includes a drain region and a drain electrode.

8. The junction field effect transistor according to claim 7, wherein: The doping depth of the second type doping region is greater than the doping depth of the first type doping region; the doping depth is the distance from the bottom of the doping region to the top surface of the first semiconductor material layer.

9. The junction field effect transistor according to claim 7 or 8, characterized in that The junction field effect transistor further comprises: A first insulating layer is formed on a portion of the upper surface of the second-type doping region and is located between the drain and the gate.

10. The junction field effect transistor according to claim 9, wherein: The junction field effect transistor further comprises: The first conductive material layer has one end covering a portion of the first insulating layer, and the other end extending toward the gate along a direction from the drain to the gate and contacting the first type doping region.

11. The junction field effect transistor according to claim 10, wherein: The first conductive material layer includes a first part and a second part separated from each other, the first part is located above the first insulating layer, one end of the second part covers a partial area of the first insulating layer, and the other end extends toward the gate along the direction from the drain to the gate and contacts the first type doping region.

12. The junction field effect transistor according to claim 11, wherein: The junction field effect transistor further comprises: a second insulating layer covering the first type doping region, the second type doping region, the first insulating layer and the first conductive material layer; The second conductive material layer is formed on the surface of the second insulating layer and corresponds to the first conductive material layer in a longitudinal direction, where the longitudinal direction is the thickness direction of the first semiconductor material layer.

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