Hybrid wafer bonding structure and image sensor

Abstract

This invention provides a hybrid wafer bonding structure and an image sensor. The hybrid wafer bonding structure includes: a logic wafer; and a pixel wafer bonded to the logic wafer via the hybrid bonding structure. The pixel wafer includes an array of pixel units. The hybrid bonding structure includes auxiliary bonding pillars formed at the bonding interface, each auxiliary bonding pillar corresponding to one of the pixel units and located at the center of the pixel unit. This technical solution, by pre-setting the positions of the auxiliary bonding pillars on the surface of the pixel wafer, ensures that the placement of the auxiliary bonding pillars on each pixel unit is identical, reducing the impact of the placement of the auxiliary bonding pillars on the optical performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a hybrid wafer bonding structure and an image sensor. Background Technology

[0002] Stacked complementary metal-oxide-semiconductor (CMOS) image sensors are obtained by heterogeneously integrating a logic wafer and pixel wafers on the logic wafer. Compared with back-illuminated (BSI) image sensors, they have the following advantages: First, by separating the processing loop area from the pixel area, the pixel area can be made smaller, or more complex functions can be integrated in the same area; second, the pixel wafer process can be optimized independently, without being limited by the logic wafer process.

[0003] Currently, there are two main methods for heterogeneous integration: one is the Ultra-Thin Stacked CMOS Image Sensor (UTS CIS), which uses through-silicon vias (TSVs) for bonding. This method is technically challenging and has low product yield. The other is the Hybrid Bond Backside Illumination (HB BSI), which uses a hybrid bonding method. There is extensive mass production experience with heterogeneous integration of logic wafers and memory wafers using hybrid bonding, and the process is relatively mature. However, there is currently no mass production experience in China of integrating logic wafers and pixel wafers using hybrid bonding. Hybrid bonding processes require high wafer flatness, thus necessitating the addition of auxiliary bonding pillars (dummy pillars). Currently, the addition of auxiliary bonding pillars in hybrid bonding processes used to integrate logic wafers and memory wafers is highly random. However, randomly placed auxiliary bonding pillars can affect the optical performance of CMOS image sensor products.

[0004] Therefore, providing a placement method for auxiliary bonding posts that does not affect the optical performance of the device is a problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a hybrid wafer bonding structure and an image sensor, so as to achieve the placement of auxiliary bonding pillars without affecting the optical performance of the device.

[0006] To address the aforementioned problems, the present invention provides a hybrid wafer bonding structure, comprising: a logic wafer; and a pixel wafer bonded to the logic wafer via the hybrid bonding structure, wherein the pixel wafer comprises pixel units arranged in an array; the hybrid bonding structure comprises auxiliary bonding pillars formed at the bonding interface, each of the auxiliary bonding pillars being correspondingly disposed to one of the pixel units and located at the center of the pixel unit.

[0007] To address the aforementioned problems, the present invention also provides an image sensor, including a wafer bonding structure, wherein the wafer bonding structure employs the hybrid wafer bonding structure described in this invention.

[0008] The above technical solution, by setting the position and arrangement of auxiliary bonding pillars on the surface of the pixel wafer according to the arrangement of pixel units in the pixel wafer, ensures that the placement of auxiliary bonding pillars on each pixel unit is the same, and that each pixel unit in the pixel wafer is affected in the same way, thereby reducing the impact of the placement of auxiliary bonding pillars on the optical performance of the device. Attached Figure Description

[0009] Figure 1 The diagram shows the placement of the auxiliary bonding pillars in the first embodiment of the hybrid wafer bonding structure of the present invention.

[0010] Figure 2 The diagram shows the placement of the auxiliary bonding pillars in a second embodiment of the hybrid wafer bonding structure described in this invention.

[0011] Figure 3 The diagram shows the placement of the auxiliary bonding pillars in the third embodiment of the hybrid wafer bonding structure of the present invention.

[0012] Figure 4 This is a schematic diagram of an embodiment of the hybrid wafer bonding structure described in this invention.

[0013] Figure 5 The diagram shown is an architectural schematic of an embodiment of the image sensor described in this invention. Detailed Implementation

[0014] The specific embodiments of the hybrid wafer bonding structure and image sensor provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0015] To address the current lack of mass production experience in integrating logic wafers and pixel wafers using hybrid bonding in China, and the high randomness of auxiliary bonding pillar addition in current hybrid bonding processes for integrating logic and memory wafers, which can negatively impact the optical performance of CMOS image sensor products, this invention provides a hybrid wafer bonding structure that reduces the impact of auxiliary bonding pillar placement on device optical performance. The hybrid wafer bonding structure of this invention includes: a logic wafer; and a pixel wafer bonded to the logic wafer via the hybrid bonding structure. The pixel wafer includes an array of pixel units. The hybrid bonding structure includes auxiliary bonding pillars formed at the bonding interface, each auxiliary bonding pillar corresponding to a pixel unit and located at the center of the pixel unit.

[0016] The above technical solution, by setting the position and arrangement of auxiliary bonding pillars on the surface of the pixel wafer according to the arrangement of pixel units in the pixel wafer, ensures that the placement of auxiliary bonding pillars on each pixel unit is the same, and that each pixel unit in the pixel wafer is affected in the same way, thereby reducing the impact of the placement of auxiliary bonding pillars on the optical performance of the device.

[0017] Please see Figure 1 This is a schematic diagram showing the placement of auxiliary bonding pillars in the first embodiment of the hybrid wafer bonding structure described in this invention. Figure 1 As shown, in this embodiment, the pixel wafer includes an array of pixel units 11, and the hybrid bonding structure includes an auxiliary bonding post 12 located at the center of the pixel unit 11. Each pixel unit 11 includes a monochrome pixel, which is one of a blue pixel 111, a green pixel 112, or a red pixel 113. Every four monochrome pixels are arranged in a quadrilateral array in the order of blue pixel 111, green pixel 112, red pixel 113, and green pixel 112. That is, every four pixel units 11 arranged in a quadrilateral array form a Bayer filter. A Bayer filter is a mosaic color filter array (CFA) formed by arranging RGB color filters on a grid of a photoelectric sensor. The arrangement of the Bayer filter is 50% green, 25% red, and 25% blue; therefore, it is also called RGBG, GRGB, or RGGB.

[0018] In some embodiments, the size S12 of the auxiliary bonding post 12 is smaller than the size S10 of the monochrome pixel, and the distance P10 between the centers of two adjacent auxiliary bonding posts 12 is equal to the size S10 of the monochrome pixel. In this embodiment, the size S10 of the monochrome pixel is 1.22 micrometers, and the pixel unit includes one monochrome pixel; therefore, the size S11 of the pixel unit 11 is also 1.22 micrometers. The size S12 of the auxiliary bonding post 12 is less than 1.22 micrometers (for example, it can be 1 micrometer), and the distance P10 between the centers of two adjacent auxiliary bonding posts 12 is also 1.22 micrometers. By correspondingly placing each auxiliary bonding post 12 at the center of the pixel unit 11, the auxiliary bonding posts 12 are regularly placed above the pixel wafer, and each pixel unit in the pixel wafer is affected equally, thereby reducing the impact of the auxiliary bonding posts 12 on the optical performance of the device.

[0019] Please see Figure 2 This is a schematic diagram showing the placement of auxiliary bonding pillars in the second embodiment of the hybrid wafer bonding structure described in this invention. Figure 2 As shown, in this embodiment, the pixel wafer includes pixel units 21 arranged in an array, and the hybrid bonding structure includes an auxiliary bonding post 22 located at the center of the pixel unit 21. The pixel unit 21 includes four monochromatic pixels arranged in a quadrilateral array, and the four monochromatic pixels are, in order, a blue pixel 211, a green pixel 212, a red pixel 213, and a green pixel 214.

[0020] In some embodiments, the size S22 of the auxiliary bonding post 22 is larger than the size S20 of the monochrome pixel but less than twice the size S20, and the distance P20 between the centers of two adjacent auxiliary bonding posts 22 is twice the size S20 of the monochrome pixel. In this embodiment, the size S20 of the monochrome pixel is 1.22 micrometers, and the pixel unit 21 is composed of four monochrome pixels arranged in a quadrilateral, that is, two monochrome pixels on each side of the quadrilateral. Therefore, the size S21 of the pixel unit 21 is 2.44 micrometers. The size S22 of the auxiliary bonding post 22 can be, for example, 1.34 micrometers, and the distance P20 between the centers of two adjacent auxiliary bonding posts 22 is 2.44 micrometers. By correspondingly setting each auxiliary bonding post 22 at the center of the pixel unit 21, the auxiliary bonding posts 22 are regularly placed above the pixel wafer, and each pixel unit in the pixel wafer is affected equally, thereby reducing the impact of the auxiliary bonding posts 22 on the optical performance of the device.

[0021] Please see Figure 3 This is a schematic diagram showing the placement of auxiliary bonding pillars in the third embodiment of the hybrid wafer bonding structure described in this invention. Figure 3As shown, in this embodiment, the pixel wafer includes an array of pixel units 31, and the hybrid bonding structure includes an auxiliary bonding post 32 located at the center of the pixel unit 31. Each pixel unit 31 includes four monochromatic pixels of the same color arranged in a quadrilateral. The monochromatic pixels are one of a blue pixel 311, a green pixel 312, or a red pixel 313, and every four pixel units 31 are arranged in a quadrilateral array in the order of blue pixel 311, green pixel 312, red pixel 313, and green pixel 312. That is, every four pixel units 31 arranged in a quadrilateral array form a quad-bayer filter. The quad-bayer filter achieves hundreds of millions of pixels through a pixel binning method.

[0022] In some embodiments, the size S32 of the auxiliary bonding post 32 is larger than the size S30 of the monochrome pixel but less than twice the size S30 of the monochrome pixel, and the distance P30 between the centers of two adjacent auxiliary bonding posts 32 is twice the size S30 of the monochrome pixel. In this embodiment, the size S30 of the monochrome pixel is 1.22 micrometers, and the pixel unit 31 is composed of four monochrome pixels of the same color arranged in a quadrilateral, that is, there are two monochrome pixels of the same color on each side of the quadrilateral. Therefore, the size S31 of the pixel unit 31 is 2.44 micrometers. The size S32 of the auxiliary bonding post 32 can be, for example, 1.34 micrometers, and the distance P30 between the centers of two adjacent auxiliary bonding posts 32 is 2.44 micrometers. By correspondingly setting each auxiliary bonding post 32 at the center of the pixel unit 31, the auxiliary bonding posts 32 are regularly placed above the pixel wafer, and each pixel unit in the pixel wafer is affected equally, thereby reducing the impact of the auxiliary bonding posts 32 on the optical performance of the device.

[0023] Please see Figure 4 This is a schematic diagram of an embodiment of the hybrid wafer bonding structure described in this invention. Figure 4As shown, the hybrid wafer bonding structure includes a logic wafer 43 and a pixel wafer 44 bonded together by the hybrid bonding structure. The hybrid bonding structure also includes a transport bonding post 40, which further includes a hybrid bonding connection layer 41 formed at the bonding interface and a hybrid bonding transport layer 42 formed in the logic wafer 43 and the pixel wafer 44 respectively, wherein the hybrid bonding connection layer 41 and the hybrid bonding transport layer 42 are connected and bonded. In this embodiment, the hybrid bonding transport layer 42 includes a first hybrid bonding transport layer 421 formed in the pixel wafer 44 and a second hybrid bonding transport layer 422 formed in the logic wafer 43. The hybrid bonding connection layer 41 further includes a first hybrid bonding connection layer 411 bonded to the first hybrid bonding transport layer 421 and a second hybrid bonding connection layer 412 bonded to the second hybrid bonding transport layer 422.

[0024] In the transport bonding post 40, the hybrid bonding connection layer 41 is electrically connected to the hybrid bonding transport layer 42. Correspondingly, the hybrid bonding connection layer 41 in the bonding interface that is not bonded to the hybrid bonding transport layer 42 is the auxiliary bonding post 49. That is, the auxiliary bonding post 49 serves as an auxiliary bonding function and does not have an electrical connection function.

[0025] In some embodiments, the distance P40 between the center of the transfer bonding post 40 and the center of the adjacent auxiliary bonding post 49 is equal to the distance P41 between the centers of the two adjacent auxiliary bonding posts 49, so as to further simplify the manufacturing process of the hybrid bonding structure.

[0026] Based on the same inventive concept, the present invention also provides an image sensor.

[0027] Please see Figure 5 This is a schematic diagram of the image sensor architecture according to an embodiment of the present invention. Figure 5 As shown, the image sensor 100 includes a wafer bonding structure 101; wherein the wafer bonding structure 101 adopts the present invention. Figures 1-4 The hybrid wafer bonding structure shown is described in detail above and will not be repeated here.

[0028] The above technical solution, by setting the position and arrangement of auxiliary bonding pillars on the surface of the pixel wafer according to the arrangement of pixel units in the pixel wafer, ensures that the placement of auxiliary bonding pillars on each pixel unit is the same, and that each pixel unit in the pixel wafer is affected in the same way, thereby reducing the impact of the placement of auxiliary bonding pillars on the optical performance of the device.

[0029] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0030] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0031] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0032] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A hybrid wafer bonding structure, characterized in that, Comprising: a logic wafer; a pixel a pixel wafer bonded with the logic wafer through a hybrid bonding structure, the pixel wafer comprising an array of pixel units; the hybrid bonding structure comprising auxiliary bonding columns formed at a bonding interface, each of the auxiliary bonding columns being arranged corresponding to one of the pixel units and located at a center position of the pixel unit, and the auxiliary bonding columns on each of the pixel units being arranged in the same manner, and the auxiliary bonding columns being used for auxiliary bonding without the function of electrical connection; the pixel unit comprising one monochromatic pixel, the monochromatic pixel being one of a red light pixel, a blue light pixel, or a green light pixel, the size of the auxiliary bonding column being smaller than the size of the monochromatic pixel, and the distance between the centers of two adjacent auxiliary bonding columns being equal to the size of the monochromatic pixel; or, the pixel unit comprising four monochromatic pixels arranged in a quadrilateral array, the size of the auxiliary bonding column being greater than the size of the monochromatic pixel and smaller than twice the size of the monochromatic pixel, and the distance between the centers of two adjacent auxiliary bonding columns being twice the size of the monochromatic pixel.

2. The hybrid wafer bonding structure of claim 1, wherein, the pixel unit comprising one monochromatic pixel, the monochromatic pixel being one of a red light pixel, a blue light pixel, or a green light pixel, and every four of the monochromatic pixels being arranged in a quadrilateral array in the order of a blue light pixel, a green light pixel, a red light pixel, and a green light pixel.

3. The hybrid wafer bonding structure of claim 1, wherein, the pixel unit comprising four monochromatic pixels arranged in a quadrilateral array, and the four monochromatic pixels being a blue light pixel, a green light pixel, a red light pixel, and a green light pixel in sequence.

4. The hybrid wafer bonding structure of claim 1, wherein, the pixel unit comprising four monochromatic pixels arranged in a quadrilateral array, the monochromatic pixel being one of a red light pixel, a blue light pixel, or a green light pixel, and every four of the pixel units being arranged in a quadrilateral array in the order of a blue light pixel, a green light pixel, a red light pixel, and a green light pixel.

5. The hybrid wafer bonding structure of claim 1, wherein, the hybrid wafer bonding structure further comprising a transmission bonding column, the transmission bonding column comprising a hybrid bonding connection layer formed at a bonding interface and a hybrid bonding transmission layer formed in the logic wafer and the pixel wafer respectively, the hybrid bonding connection layer and the hybrid bonding transmission layer being connected and bonded.

6. The hybrid wafer bonding structure of claim 5, wherein, the distance between the transmission bonding column and the center of an adjacent auxiliary bonding column being equal to the distance between the centers of two adjacent auxiliary bonding columns.

7. An image sensor, characterized by, comprising a wafer bonding structure, the wafer bonding structure adopting the hybrid wafer bonding structure according to any one of claims 1-6.

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