LED passivation layer, preparation method and LED chip

Abstract

The application provides an LED passivation layer, a preparation method and an LED chip. The first passivation sublayer and the second passivation sublayer with a meandering shape are deposited on the surface of an LED epitaxial wafer. If the chip is damaged in the cutting process, the passivation layer cracks at the junction with the chip. Since the first passivation sublayer and the second passivation sublayer are meandering structures, the interface path can be effectively increased, the distance of the moisture invading the chip along the interface is increased, the moisture corrosion problem of the chip is improved, and the service life of the chip is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LED, in particular to an LED passivation layer, a preparation method and an LED chip. BACKGROUND

[0002] Light emitting diode (LED) is a kind of semiconductor electronic component that can emit light, which attracts more and more researchers due to its small size, high brightness and low energy consumption.

[0003] It should be noted that although the light efficiency of LED is important, its reliability also needs to be guaranteed. Specifically, temperature and humidity are two important factors affecting the reliability of LED. With the passage of time, the chip will absorb moisture, which will cause phenomena such as epitaxial corrosion, ITO corrosion and metal migration, thereby leading to chip dead light, electric leakage and other failures.

[0004] Among them, moisture absorption failure is an important problem affecting the reliability of LED. In order to avoid the phenomena such as reduction of service life, reduction of light emitting efficiency and red shift of light emitting color of LED due to moisture absorption, a passivation layer is usually covered in the manufacturing process of LED. The passivation layer can protect the electrode and the side wall, has good moisture resistance and corrosion resistance, and it can be understood that the damage will inevitably affect the reliability of LED. However, damage to the passivation layer will inevitably occur during the cutting process, including breakage of the passivation layer. In addition, during a long period of use, moisture will penetrate along the interface between the passivation layer and the chip, eventually causing chip moisture corrosion. SUMMARY

[0005] Therefore, the purpose of the present application is to provide an LED passivation layer, a preparation method and an LED chip, which can solve the problem that the passivation layer is damaged during the cutting process, and moisture penetrates along the interface between the passivation layer and the chip, eventually causing chip moisture corrosion.

[0006] According to one of the embodiments of the present application, the LED passivation layer is deposited on the surface of an epitaxial wafer, and the LED passivation layer comprises at least a first passivation sublayer and a second passivation sublayer deposited on the first passivation sublayer, wherein the surfaces of the first passivation sublayer and the second passivation sublayer are both in a zigzag shape.

[0007] Further, the surface shape of the first passivation sublayer is the same as that of the second passivation sublayer.

[0008] Further, the first passivation sublayer is a TiO2 layer, and the second passivation sublayer is SiO2.

[0009] Further, the thickness of the first passivation sublayer is 20-30 nm.

[0010] Further, the second passivation sub-layer has a thickness of 75-100 nm.

[0011] Further, the epitaxial wafer comprises a substrate and sequentially deposited on the substrate are an N-type layer, an active layer, a P-type layer, a current blocking layer, a transparent conductive film layer and a metal electrode.

[0012] The first passivation sub-layer is deposited on the N-type layer, and the second passivation sub-layer is also disposed on the active layer, the P-type layer, the transparent conductive film layer and the metal electrode.

[0013] Further, the transparent conductive film layer comprises one or more of ITO, IZO and ZnO materials.

[0014] According to one of the embodiments of the present application, a preparation method of an LED passivation layer is provided for preparing the above-mentioned LED passivation layer deposited on the surface of an epitaxial wafer, and the method comprises:

[0015] depositing a first passivation sub-layer on the surface of the epitaxial wafer, and etching the first passivation sub-layer in the cutting groove of the epitaxial wafer to obtain a first passivation sub-layer with a surface zigzag pattern;

[0016] depositing a second passivation sub-layer on the epitaxial wafer and the etched first passivation sub-layer.

[0017] Further, the step of depositing a first passivation sub-layer on the surface of the epitaxial wafer and etching the first passivation sub-layer in the cutting groove of the epitaxial wafer to obtain an etched first passivation sub-layer comprises the following steps:

[0018] providing a substrate required for growth;

[0019] sequentially depositing on the substrate an N-type layer, an active layer and a P-type layer;

[0020] etching from the P-type layer to the substrate direction by using ICP etching technology to expose the N-type layer;

[0021] using PECVD equipment to evaporate silicon oxide, and using photolithography etching technology to etch the silicon oxide to obtain a current blocking layer deposited only on the P-type layer;

[0022] using electron beam evaporation technology to evaporate a transparent conductive film layer as a whole and performing RTA annealing;

[0023] using electron beam evaporation technology to prepare a metal electrode on the transparent conductive film layer to obtain the epitaxial wafer.

[0024] According to one of the embodiments of the present application, the LED chip comprises the LED passivation layer.

[0025] Compared with the prior art, by depositing the first passivation sub-layer and the second passivation sub-layer with the meandering shape on the surface of the LED epitaxial wafer, if the chip is damaged in the cutting process, that is, the passivation layer cracks at the junction with the chip, since the first passivation sub-layer and the second passivation sub-layer are meandering structures, the interface path can be effectively increased, the distance of the moisture invading the chip along the interface is increased, and thus the problem of moisture corrosion of the chip is improved, and the service life of the chip is increased. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 A structure diagram of the LED passivation layer according to the embodiment of the present application is provided;

[0027] Figure 2 A preparation method of the LED passivation layer according to the embodiment of the present application is provided;

[0028] Figure 3 An LED chip comprising the LED passivation layer according to the embodiment 2 is provided;

[0029] Figure 4 An LED chip comprising the LED passivation layer according to the embodiment 3 is provided. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. Several embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can be an intervening element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be an intervening element. The terms "vertical", "horizontal", "left", "right", and similar expressions used herein are for illustrative purposes only.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] Reference will now be made to Figure 1A structure diagram of an LED passivation layer disclosed in the embodiment of the present application, wherein the epitaxial wafer can be a GaN epitaxial wafer, the LED passivation layer 8 is deposited on the surface of the GaN epitaxial wafer, and the LED passivation layer 8 at least comprises a first passivation sub-layer 81 and a second passivation sub-layer 82 deposited on the first passivation sub-layer 81, wherein the surface of the first passivation sub-layer 81 and the surface of the second passivation sub-layer 82 are both in a zigzag shape, and the surface shape of the first passivation sub-layer 81 is the same as the surface shape of the second passivation sub-layer 82. Since the surface of the first passivation sub-layer 81 and the surface of the second passivation sub-layer 82 are both in a zigzag shape, the interface path can be increased, the distance of the moisture invading into the chip along the interface can be increased, and thus the service life of the chip is increased.

[0034] It should be noted that the LED passivation layer 8 needs to be deposited on the GaN epitaxial wafer so as to protect the whole chip. Specifically, the GaN epitaxial wafer comprises a substrate 1, an N-doped GaN layer 2, an active layer 3, a P-doped GaN layer 4, a current blocking layer 5, an ITO transparent conductive film layer 6 and a metal electrode 7 deposited in sequence. It can be understood that, after the above-mentioned parts are prepared, the first passivation sub-layer 81 and the second passivation sub-layer 82 are deposited on the GaN epitaxial wafer in sequence. Before the current blocking layer 5, the ITO transparent conductive film layer 6 and the metal electrode 7 are prepared, the existing N-doped GaN layer 2, the active layer 3 and the P-doped GaN layer 4 need to be etched first. Specifically, the P-doped GaN layer 4 is etched towards the substrate 1 until the N-doped GaN layer 2 is exposed. The etching depth is 0.9 μm to 1.1 μm until the N-doped GaN layer 2 is exposed. For example, the etching depth of the N-doped GaN layer 2 is 0.92 μm, 0.94 μm, 1 μm, 1.4 μm or 1.8 μm, etc., but is not limited thereto.

[0035] It can be understood that, when the N-doped GaN layer 2 is exposed by etching, the whole will present a groove, i.e. a cutting path. The first passivation sub-layer 81 and the second passivation sub-layer 82 in a zigzag shape are deposited on the cutting path. Except for the cutting path, the second passivation sub-layer 82 is attached to the active layer 3, the P-doped GaN layer 4, the ITO transparent conductive film layer 6 and the metal electrode 7 without a zigzag structure. Since the chip cutting is mainly for the cutting path, the damage is mainly from the damage of the cutting path, and the rest will not cause the problem of reducing the moisture resistance of the chip. Therefore, only the passivation layer on the cutting path is improved.

[0036] From the cross section of the LED passivation layer 8, the first passivation sub-layer 81 and the second passivation sub-layer 82 can be continuous rectangles, triangles, wavy shapes and the like, but are not limited thereto. It should be noted that if one rectangle, one triangle or one wavy shape is one period, at least two periods need to be provided, that is, the cross section of the LED passivation layer 8 is composed of at least two rectangles, two triangles or two wavy shapes. It can be understood that when the chip group needs to be cut, the laser cutting equipment will be aligned with the middle region of the cutting path to cut the chip group into two symmetrical parts. At this time, the cross section of the LED passivation layer 8 of each chip at least includes one rectangle, one triangle or one wavy shape. Compared with the traditional straight interface, it has a longer path, which can prevent moisture from invading to a certain extent. It can be understood that the more dense the tortuosity of the surface of the first passivation sub-layer 81 and the second passivation sub-layer 82, the longer the interface path, and the better the effect of preventing moisture from invading. That is, the more the number of periods of the shapes of the cross section of the first passivation sub-layer 81 and the second passivation sub-layer 82, such as rectangles, triangles and wavy shapes, the better the effect.

[0037] Further, in view of the cracking caused by the release of interface stress caused by the breakage of the passivation layer during chip cutting, the embodiments of the present application use a different material isolation method to release stress to achieve the effect of inhibiting cracking. Specifically, the first passivation sub-layer 81 is a TiO2 layer, and the second passivation sub-layer 82 is SiO2. It can be understood that conventionally, the SiO2 passivation layer is directly deposited on the N-type doped GaN layer 2. When cutting, the breakage of the SiO2 passivation layer releases residual stress at the breakage boundary, causing the SiO2 passivation layer to crack at the junction with the chip. However, by using the first passivation sub-layer 81 as a TiO2 layer and the second passivation sub-layer 82 as SiO2, two materials with similar materials release stress during cutting, and cracking problems are improved.

[0038] In addition, the current blocking layer 5 in the GaN epitaxial wafer is a silicon oxide layer, and the thickness of the current blocking layer 5 is 250 nm to 350 nm, for example, the thickness of the current blocking layer 5 is 280 nm, 300 nm, 320 nm, 340 nm, etc., but is not limited to this; the thickness of the ITO transparent conductive film layer 6 is 50 nm to 70 nm, for example, the thickness of the ITO transparent conductive film layer 6 is 52 nm, 54 nm, 60 nm, 62 nm, or 66 nm, etc., but is not limited to this; the metal electrode 7 is one or more of Cr / Al / Ti / Pt / Au / Ti; the thickness of the first passivation sub-layer 81 is 20 nm to 30 nm, for example, the thickness of the first passivation sub-layer 81 is 22 nm, 24 nm, 25 nm, 26 nm, or 28 nm, etc., but is not limited to this; the thickness of the second passivation sub-layer 82 is 75 nm to 100 nm, for example, the thickness of the second passivation sub-layer 82 is 76 nm, 78 nm, 80 nm, 82 nm, or 100 nm, etc., but is not limited to this.

[0039] Correspondingly, with reference to Figure 2 The embodiment of the present application further discloses a preparation method of the LED passivation layer, which is used for preparing the above-mentioned LED passivation layer, and is deposited on the surface of the GaN epitaxial wafer, and specifically comprises the following steps:

[0040] S100: depositing a first passivation sub-layer on the surface of the GaN epitaxial wafer, and etching the first passivation sub-layer in the cutting groove of the GaN epitaxial wafer to obtain a first passivation sub-layer with a surface fold.

[0041] It should be noted that before the first passivation sub-layer is prepared, the GaN epitaxial wafer needs to be prepared, and the specific process of preparing the GaN epitaxial wafer is as follows: providing a substrate required for growth, the substrate can be a sapphire substrate, sequentially depositing an N-type doped GaN layer, an active layer and a P-type doped GaN layer on the sapphire substrate, at this time, a GaN epitaxial wafer to be processed is obtained, further, an ICP (Inductively Couple Plasma) etching technology is used to etch the GaN epitaxial wafer to be processed from the P-type doped GaN layer to the substrate direction, so that the N-type doped GaN layer is exposed, that is, the cutting groove, wherein the N-type doped GaN layer is etched to a preset depth, and is used for depositing the passivation layer on the N-type doped GaN layer.

[0042] Further, a PECVD (Plasma Enhanced Chemical Vapor Deposition) device is used to evaporate silicon oxide as a whole on the basis of etching the cutting groove, and a photolithography etching technology is used to etch the silicon oxide to obtain a current blocking layer deposited only on the P-type doped GaN layer.

[0043] Further, the ITO transparent conductive film layer is deposited by electron beam evaporation technology, and rapid thermal annealing (RTA) annealing is performed, wherein the RTA annealing is performed at 500-600°C for 10-20 min.

[0044] Specifically, after the RTA annealing, a metal electrode is prepared on the ITO transparent conductive film layer by electron beam evaporation technology to obtain a GaN epitaxial wafer, wherein the metal electrode is one or more of Cr / Al / Ti / Pt / Au / Ti, and after the preparation of the metal electrode, a first passivation sublayer is deposited on the surface of the GaN epitaxial wafer by using a PECVD device, and after the deposition, the first passivation sublayer in the cutting path is etched into a zigzag shape by using photolithography and ICP etching technology. It should be noted that the process of etching the first passivation sublayer into a zigzag shape can be as follows: first, a flat first passivation sublayer is deposited on the surface of the GaN epitaxial wafer by using a PECVD device, then the surface of the GaN epitaxial wafer is uniformly coated with a photoresist, and then the photoresist is exposed to light by using a mask (the mask is a template for patterning the deposited first passivation sublayer, i.e., the TiO2 layer, and has transparent and non-transparent parts, and the transparent part can form a pattern after exposure), and then the photoresist is developed after exposure, and then the developed photoresist is sent to ICP etching, and then the photoresist is removed by using a photoresist remover after ICP etching, thereby completing the preparation of the first passivation sublayer in the cutting path in a zigzag shape. It should be noted that the above-mentioned uniform coating, exposure and development are collectively referred to as yellow light processing, that is, the photoresist to be removed and retained is treated by using an exposure machine and a mask, and for example, the photoresist exposed to light is easily removed by a developing solution, and the patterned photoresist remaining after exposure protects the TiO2 at the bottom, and in the etching process, the TiO2 without photoresist protection is etched, and the TiO2 with photoresist protection is retained, and finally the required first passivation sublayer is formed in the cutting path.

[0045] S200: depositing a second passivation sublayer on the GaN epitaxial wafer and the etched first passivation sublayer.

[0046] The second passivation sublayer, i.e., the SiO2 layer, is deposited on the surface of the chip by using a PECVD device, and since the first passivation sublayer has been prepared into a zigzag shape, the second passivation sublayer maintains the same shape as the first passivation sublayer when deposited on the first passivation sublayer, and in addition, the metal electrode is exposed by using photolithography and etching technology.

[0047] The present application is further described below with reference to specific embodiments:

[0048] Embodiment 1

[0049] Embodiment 1 provides an LED passivation layer, which is specifically described inFigure 1 The LED chip comprising the LED passivation layer 8 comprises a substrate 1, and sequentially arranged on the substrate 1 are an N-doped GaN layer 2, an active layer 3, a P-doped GaN layer 4, a current blocking layer 5, an ITO transparent conductive film layer 6, and a metal electrode 7.

[0050] The substrate 1 is a sapphire substrate, the current blocking layer 5 is a silicon oxide layer, and the metal electrode 7 is an Al material. In this embodiment, the cross-sectional profile shape of the first passivation sub-layer 81 and the second passivation sub-layer 82 is a plurality of rectangles, and there are 8 continuous rectangles. The thickness of the first passivation sub-layer 81 is 25 nm, and the thickness of the second passivation sub-layer 82 is 80 nm.

[0051] The preparation method of the LED passivation layer 8 in this embodiment is specifically as follows:

[0052] (1) A PECVD device is used to evaporate the first passivation sub-layer 81 on the surface of a GaN epitaxial wafer. After the evaporation is completed, the first passivation sub-layer 81 in the cutting channel is etched to have a cross-sectional profile shape of a rectangle through photolithography and ICP etching technology. It should be noted that the process of etching the first passivation sub-layer 81 to have a rectangular shape can be specifically as follows. First, a PECVD device is used to evaporate a flat first passivation sub-layer 81 on the surface of a GaN epitaxial wafer. After that, the surface of the entire GaN epitaxial wafer is uniformly coated with a photoresist. After the photoresist is uniformly coated, a rectangular array mask plate (the mask plate is a template for patterning the evaporated first passivation sub-layer 81, i.e., the TiO2 layer, and has transparent and non-transparent parts) is used for exposure processing. After exposure, development is performed. After development, ICP etching is performed. After ICP etching, a photoresist removing solution is used to remove the photoresist. In this way, the first passivation sub-layer 81 in the cutting channel is prepared to have a cross-sectional profile shape of a rectangle. In addition, in some other embodiments of the present application, the first passivation sub-layer 81 can also be etched to have a cross-sectional profile shape of a rectangle by using an imprint method.

[0053] (2) The second passivation sub-layer 82 is deposited on the GaN epitaxial wafer and the etched first passivation sub-layer 81.

[0054] Embodiment 2

[0055] This embodiment 2 provides an LED passivation layer. As shown in Figure 3 , the LED chip comprising the LED passivation layer 8 comprises a substrate 1, and sequentially arranged on the substrate 1 are an N-doped GaN layer 2, an active layer 3, a P-doped GaN layer 4, a current blocking layer 5, an ITO transparent conductive film layer 6, and a metal electrode 7.

[0056] The substrate 1 is a sapphire substrate, the current blocking layer 5 is a silicon oxide layer, and the metal electrode 7 is Al material. In the embodiment, the cross-sectional profile shape of the first passivation sub-layer 81 and the second passivation sub-layer 82 is a plurality of triangles, and there are eight continuous triangles. The thickness of the first passivation sub-layer 81 is 25 nm, and the thickness of the second passivation sub-layer 82 is 80 nm.

[0057] The preparation method of the LED passivation layer 8 in the embodiment is specifically as follows:

[0058] (1) The first passivation sub-layer 81 is deposited on the surface of the GaN epitaxial wafer by using a PECVD device. After the deposition is completed, the first passivation sub-layer 81 in the cutting channel is etched to have a triangular cross-sectional profile shape by using photoetching and ICP etching technology. It should be noted that the process of etching the first passivation sub-layer 81 to have a rectangular shape can be specifically as follows. First, a flat first passivation sub-layer 81 is deposited on the surface of the GaN epitaxial wafer by using a PECVD device. Then, the surface of the GaN epitaxial wafer is uniformly coated with a photoresist. After the photoresist is uniformly coated, a triangular array mask plate (the mask plate is a template for patterning the deposited first passivation sub-layer 81, i.e., the TiO2 layer, and has transparent and non-transparent parts) is used for exposure processing. After the exposure, development is performed. After the development, the ICP etching is performed. After the ICP etching, the photoresist is removed by using a photoresist remover. In this way, the first passivation sub-layer 81 in the cutting channel is prepared to have a triangular cross-sectional profile shape. In addition, in some other embodiments of the present application, the first passivation sub-layer 81 can also be etched to have a triangular cross-sectional profile shape by using an imprint method.

[0059] (2) The second passivation sub-layer 82 is deposited on the GaN epitaxial wafer and the etched first passivation sub-layer 81.

[0060] Embodiment 3

[0061] The embodiment 3 provides an LED passivation layer. As shown in Figure 4 The embodiment 3 provides an LED passivation layer. As shown in

[0062] The substrate 1 is a sapphire substrate, the current blocking layer 5 is a silicon oxide layer, and the metal electrode 7 is Al material. In the embodiment, the cross-sectional profile shape of the first passivation sub-layer 81 and the second passivation sub-layer 82 is a plurality of triangles, and there are eight continuous triangles. The thickness of the first passivation sub-layer 81 is 25 nm, and the thickness of the second passivation sub-layer 82 is 80 nm.

[0063] The preparation method of the LED passivation layer 8 in the embodiment is specifically as follows:

[0064] (1) using a PECVD device to evaporate a first passivation sub-layer 81 on the surface of a GaN epitaxial wafer, after evaporation, the first passivation sub-layer 81 in the cutting channel is etched to have a cross-sectional profile in a wave shape by using photoetching and ICP etching technology, it should be noted that the process of etching the first passivation sub-layer 81 to have a rectangular shape can be that first, using a PECVD device to evaporate a flat first passivation sub-layer 81 on the surface of a GaN epitaxial wafer, then uniformly glue the surface of the entire GaN epitaxial wafer, after uniform gluing, using a wave-shaped mask (the mask is a template for patterning the evaporated first passivation sub-layer 81, i.e., the TiO2 layer, which has light-transmitting and non-light-transmitting parts, and the light-transmitting irradiation part can finally form a pattern) for exposure processing, after exposure, development, after development, ICP etching, and then removing the photoresist with a glue remover, the preparation of the first passivation sub-layer 81 with a cross-sectional profile in a wave shape in the cutting channel is completed. In addition, in some other embodiments of the present application, the first passivation sub-layer 81 can also be etched to have a cross-sectional profile in a wave shape by using an imprint method.

[0065] (2) depositing a second passivation sub-layer 82 on the GaN epitaxial wafer and the etched first passivation sub-layer 81.

[0066] Embodiment 4

[0067] The present embodiment also provides an LED passivation layer, which is different from the embodiment 1 in that the cross-sectional profile of the first passivation sub-layer and the second passivation sub-layer is a plurality of rectangles, and there are 6 continuous rectangles.

[0068] Embodiment 5

[0069] The present embodiment also provides an LED passivation layer, which is different from the embodiment 1 in that the cross-sectional profile of the first passivation sub-layer and the second passivation sub-layer is a plurality of rectangles, and there are 4 continuous rectangles.

[0070] Embodiment 6

[0071] The present embodiment also provides an LED passivation layer, which is different from the embodiment 1 in that the thickness of the first passivation sub-layer is 35 nm, and the thickness of the second passivation sub-layer is 80 nm.

[0072] Embodiment 7

[0073] The present embodiment also provides an LED passivation layer, which is different from the embodiment 1 in that the thickness of the first passivation sub-layer is 50 nm, and the thickness of the second passivation sub-layer is 80 nm.

[0074] Embodiment 8

[0075] The embodiment also provides an LED passivation layer, which is different from the embodiment 1 in that the thickness of the first passivation sub-layer is 25 nm and the thickness of the second passivation sub-layer is 100 nm.

[0076] Comparative example 1

[0077] The comparative example provides an LED passivation layer, which is different from the embodiment 1 in that the surfaces of the first passivation sub-layer and the second passivation sub-layer are parallel to the surface of the N-doped GaN layer.

[0078] Comparative example 2

[0079] The comparative example provides an LED passivation layer, which is different from the embodiment 1 in that the first passivation sub-layer is not contained in the passivation layer, and only the second passivation sub-layer is deposited on the N-doped GaN layer, and the surface of the second passivation sub-layer is parallel to the surface of the N-doped GaN layer.

[0080] The LED chips obtained in the embodiment 1-8 and the comparative examples 1-2 are each taken 200 pcs for reliability test, and specifically, the high-temperature and high-humidity test conditions are: temperature 95 ℃, humidity 90%, test current 225 mA, and aging time 2000 h.

[0081] The specific results are as follows:

[0082]

[0083] As shown in the table, the LED chip prepared by the method in the embodiment of the application can effectively improve the problem of chip moisture corrosion and increase the service life of the chip, wherein the yield of the LED chip prepared in the embodiment 3 is best, which is 95.5%, and the yields of the LED chips prepared in other embodiments of the application are all above 80%, which are better than the LED chip prepared in the comparative example, i.e., the LED chip prepared in the traditional way.

[0084] In summary, the LED passivation layer, the preparation method and the LED chip in the embodiment of the application can effectively increase the interface path and the distance of moisture invading the chip along the interface by depositing the first passivation sub-layer and the second passivation sub-layer with the zigzag shape on the surface of the LED epitaxial wafer, so as to improve the problem of chip moisture corrosion and increase the service life of the chip.

[0085] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. An LED passivation layer, said LED passivation layer being deposited on the surface of an epitaxial wafer, characterized in that, The LED passivation layer includes at least a first passivation sublayer and a second passivation sublayer deposited on the first passivation sublayer, wherein the surfaces of the first passivation sublayer and the second passivation sublayer are both tortuous. The surface shape of the first passivation sublayer is the same as the surface shape of the second passivation sublayer; The first passivation sublayer is a TiO2 layer, and the second passivation sublayer is a SiO2 layer. 2； The thickness of the first passivation sublayer is 20nm~30nm; The thickness of the second passivation sublayer is 75nm~100nm; The epitaxial wafer includes a substrate and an N-type layer, an active layer, a P-type layer, a current blocking layer, a transparent conductive film layer, and a metal electrode sequentially deposited on the substrate. The first passivation sublayer is deposited on the N-type layer, and the second passivation sublayer is also deposited on the active layer, the P-type layer, the transparent conductive film layer, and the metal electrode.

2. The LED passivation layer according to claim 1, characterized in that, The transparent conductive film layer includes one or more of ITO, IZO, and ZnO materials.

3. A method for preparing an LED passivation layer, characterized in that, The method for preparing the LED passivation layer according to any one of claims 1-2, wherein the LED passivation layer is deposited on the surface of an epitaxial wafer, comprises: A first passivation sublayer is deposited on the surface of the epitaxial wafer, and the first passivation sublayer is etched in the dicing channel of the epitaxial wafer to obtain a first passivation sublayer with a tortuous surface. A second passivation sublayer is deposited on the epitaxial wafer and the etched first passivation sublayer.

4. The method for preparing the LED passivation layer according to claim 3, characterized in that, Before the step of depositing a first passivation sublayer on the surface of the epitaxial wafer and etching the first passivation sublayer in the dicing channel of the epitaxial wafer to obtain the etched first passivation sublayer, the following steps are included: Provide a substrate required for growth; An N-type layer, an active layer, and a P-type layer are sequentially deposited on the substrate; ICP etching technology is used to etch from the P-type layer toward the substrate to expose the N-type layer; Silicon oxide is deposited by vapor deposition using PECVD equipment and etched by photolithography to obtain a current blocking layer deposited only on the P-type layer. A transparent conductive film layer is deposited integrally using electron beam evaporation technology and then subjected to RTA annealing. Metal electrodes are fabricated on the transparent conductive film layer using electron beam evaporation technology to obtain the epitaxial wafer.

5. An LED chip, characterized in that, Includes the LED passivation layer as described in any one of claims 1-2.

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