A valley current limit generation circuit for ACOT controlled Buck converter

Abstract

The present invention belongs to the field of integrated circuit technology and power electronics, and specifically relates to a valley current limit generation circuit for an ACOT controlled Buck converter, including an error amplifier, a positive valley current generation circuit, a negative valley current generation circuit, and a current differential valley limit comparison circuit. The in-phase terminal of the error amplifier is connected to the Buck internal reference voltage V ref , inverting terminal feedback voltage V FB The output terminal is connected to the positive valley current generating circuit and the negative valley current generating circuit, which generate positive valley current and negative valley current respectively. The current differential valley limit comparison circuit obtains the valley current limit that switches smoothly at zero value by taking the difference between the positive valley current and the negative valley current, and outputs the inductor current I L The comparison result with the valley current limit controls the power down tube to be turned off. The Buck converter of the present invention can not only be in a discontinuous conduction state under light load to obtain high efficiency, but also allow inductor reverse flow to be in a continuous conduction state under light load to maintain the characteristic of low output ripple.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit technology and power electronics, and specifically relates to a valley current limit generating circuit for an adaptive constant on-time (ACOT) controlled Buck converter. Background Art

[0002] The DC-DC Buck converter chip has good efficiency in the full load range and is small in size. It is the most common chip in various electronic systems at present. For example, servers, communication base stations, mobile phones, etc. will integrate various power chips for different purposes. At present, power chips are developing in the direction of low power consumption, high efficiency, small size, high power density, and faster transient response. Fast transient response means that the power supply voltage can recover quickly when the load jumps. The COT-controlled Buck converter has been widely studied and applied in academia and industry due to its advantages such as fast transient response and simple control structure. The current mode Buck converter using COT control generates an upper tube shutdown signal, that is, a lower tube conduction signal, by fixing the conduction time, and then compares the inductor current with the valley current limit to generate a lower tube shutdown signal, that is, an upper tube conduction signal, so as to achieve the purpose of adjusting the output voltage. The COT-controlled current mode Buck converter can remain stable even when the duty cycle is greater than 50%, which can avoid subharmonic oscillation of peak current mode control and does not require the design of a slope compensation circuit; when lightly loaded, the COT-controlled current mode Buck converter can be divided into two working states according to whether the inductor reverse flow is allowed. When the inductor reverse flow is not allowed, the light load is in discontinuous conduction mode (DCM), the frequency is reduced, and high conversion efficiency can be achieved; when the inductor reverse flow is allowed, the light load is in continuous conduction mode (CCM), the frequency remains unchanged, and low ripple can be achieved, but the efficiency is very low. In order to solve the electromagnetic compatibility problem of COT control, ACOT is often used, and its conduction time changes with the input and output to maintain a constant frequency. For the ACOT-controlled current mode Buck converter with light load support inductor reverse flow option, while maintaining low output ripple performance, a valley current limit with smooth positive and negative switching needs to be generated. Summary of the invention

[0003] The purpose of the present invention is to propose a valley current limit generating circuit for an ACOT-controlled Buck converter that is suitable for light load support inductor reverse flow options, which can provide a positive valley current limit for heavy loads and a negative valley current limit for light loads. Thus, the Buck converter has low ripple performance and fast load transient response over the entire load range. Compared to the traditional ACOT-controlled Buck converter, the ACOT-controlled Buck converter using the present invention can not only be in a discontinuous conduction state at light loads to obtain high efficiency, but also provide an option to allow inductor reverse flow, so that it is in a continuous conduction state at light loads, maintaining the characteristics of low output ripple.

[0004] To achieve the above-mentioned purpose, the technical solution of the present invention is: a valley current limit generating circuit for an ACOT-controlled Buck converter suitable for light-load supporting inductor reverse current option, comprising an error amplifier EA, a positive valley current generating circuit, a negative valley current generating circuit, and a current differential valley limit comparison circuit. The positive valley current generating circuit and the negative valley current generating circuit output a current controlled by the error amplifier EA. When the load is heavy, the positive valley current generating circuit works, and the output current of the negative valley current generating circuit is zero; when the load is light, the negative valley current generating circuit works, and the output current of the positive valley current generating circuit is zero. The current differential valley limit comparison circuit takes the difference between the positive valley current and the negative valley current to obtain a valley current limit that switches smoothly at zero value, and outputs the inductor current I L and the comparison result of the valley current limit.

[0005] Figure 1 The error amplifier EA is connected to the Buck internal reference voltage V ref , the feedback voltage V of the Buck chip is connected in reverse phase FB , the output terminal is connected to the positive valley current generating circuit and the negative valley current generating circuit. Figure 5 In the simulation shown, the error amplifier EA is connected to the EA output in the inverting terminal and the test signal V in the same phase terminal. P The output terminal is connected to the positive valley current generating circuit and the negative valley current generating circuit. The output of the positive valley current generating circuit and the negative valley current generating circuit is connected to the current differential valley limit comparison circuit. The output CO of the current differential valley limit comparison circuit is connected to Figure 2 Logic and driver modules. Figure 2The Buck converter of the present invention is applied. The adaptive timing module and the present invention are both connected to the logic and driving module, and the logic and driving module is connected to the gate of the power lower tube NLD1 and the power upper tube NLD2. The source of the power lower tube NLD1 is grounded, and the drain of the power upper tube NLD2 is connected to the power supply. The drain of the power lower tube NLD1 is connected to the source of the power upper tube NLD2, and the node is called the SW node. One end of the first inductor L1 is connected to the SW point, and the other end is connected to the second capacitor C2. One end of the second capacitor C2 is connected to the second resistor R2, and the other end of the second capacitor C2 is grounded. The other end of the second resistor R2 is connected to the third resistor R3, and the other end of the third resistor R3 is grounded. The node where the second resistor R2 and the third resistor R3 are connected is connected to the inverting end of the error amplifier EA of the present invention.

[0006] The positive valley current generating circuit includes a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first resistor R1, and a first current source I1; the negative valley current generating circuit includes a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a second current source I2, a third current source I3, and a first capacitor C1;

[0007] The gate of the first NMOS tube MN1 is connected to the output end of the error amplifier EA, the source of the first NMOS tube MN1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is grounded, the drain of the first NMOS tube MN1 is connected to one end of the first current source I1 and the gate of the second PMOS tube MP2; the other end of the first current source I1 is connected to the power supply; the gate of the first PMOS tube MP1 is connected to the gate of the sixth PMOS tube MP6, the source of the first PMOS tube MP1 is connected to the power supply, and the drain of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2; the source of the second PMOS tube MP2 is connected to the power supply, and the drain of the second PMOS tube MP2 is connected to the source of the first NMOS tube MN1; the gate of the third PMOS tube MP3 is connected to the gate of the second PMOS tube MP2, and the source of the third PMOS tube MP3 is connected to the power supply;

[0008] The gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3, the source of the fourth PMOS tube MP4 is connected to the power supply, the drain of the fourth PMOS tube MP4 is connected to one end of the second current source I2, one end of the first capacitor C1 and the gate of the third NMOS tube MN3; the other end of the second current source I2 and the other end of the first capacitor C1 are grounded; the gate of the second NMOS tube MN2 is connected to the source of the fifth NMOS tube MN5, the source of the second NMOS tube MN2 is grounded, and the drain of the second NMOS tube MN2 is connected to the source of the fourth NMOS tube MN4; the source of the third NMOS tube MN3 is grounded, and the drain of the third NMOS tube MN3 is connected to the source of the fifth NMOS tube MN5; the gate and drain of the fourth NMOS tube MN4 are short-circuited; the fourth NMOS tube MN5 The drain of N4 is connected to one end of the third current source I3, and the other end of the third current source I3 is connected to the power supply; the gate of the fifth NMOS tube MN5 is connected to the gate of the fourth NMOS tube MN4, and the drain of the fifth NMOS tube MN5 is connected to the drain of the sixth PMOS tube MP6; the source of the fifth PMOS tube MP5 is connected to the power supply, and the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6; the source of the sixth PMOS tube MP6 is connected to the power supply; the second current source I2, the first capacitor C1 and the third NMOS tube MN3 constitute a high-side clamp outputted by the error amplifier EA; the third current source I3, the second NMOS tube MN2, the fourth NMOS tube MN4, the fifth NMOS tube MN5 and the sixth PMOS tube MP6 constitute a low-side clamp outputted by the error amplifier EA.

[0009] The gate of the sixth NMOS tube MN6 of the current differential valley limit comparison circuit is connected to the gate drive signal LS of the power down tube NLD1, the drain of the sixth NMOS tube MN6 is connected to the positive input terminal of the comparator COMP and the drain of the fifth PMOS tube, and the source of the sixth NMOS tube MN6 is grounded. The gate of the seventh NMOS tube MN7 is connected to the gate drive signal LS of the power down tube NLD1, the drain of the seventh NMOS tube MN7 is connected to the drain SW of the power down tube NLD1, and the source of the seventh NMOS tube MN7 is connected to the negative input terminal of the comparator COMP and the drain of the third PMOS tube. The output CO of the comparator is connected to Figure 2 Logic and driver modules.

[0010] The beneficial effect of the present invention is that the present invention can provide a valley current limit for an ACOT-controlled Buck converter that supports an inductor reverse flow option at light load, provide a positive valley current limit at heavy load, and provide a negative valley current limit at light load. Compared with the traditional ACOT-controlled Buck converter, the ACOT-controlled Buck converter using the present invention can not only be in a discontinuous conduction state at light load to obtain high efficiency, but also provide an option to allow inductor reverse flow, sacrificing efficiency in exchange for low ripple performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a diagram of the valley current limit generation circuit architecture proposed by the present invention;

[0012] Figure 2 The ACOT controlled Buck converter architecture diagram of the present invention is applied;

[0013] Figure 3 This is a schematic diagram of the positive and negative valley current generating circuit proposed by the present invention;

[0014] Figure 4 This is a schematic diagram of a current differential valley limit comparison circuit proposed by the present invention;

[0015] Figure 5 The positive and negative valley current generation circuit simulation waveform proposed by the present invention;

[0016] Figure 6 The ACOT controlled Buck converter load change simulation waveform is applied to the present invention. DETAILED DESCRIPTION

[0017] The embodiments of the present invention are described in detail with reference to the accompanying drawings. The valley current limit generating circuit of the ACOT controlled Buck converter with light load supporting inductive reverse current option proposed by the present invention can provide a positive valley current limit for the Buck chip under heavy load and a negative valley current limit for the Buck chip under light load.

[0018] Figure 3 In the positive and negative valley current generating circuit, the output V of the error amplifier EA is C It has both high-side and low-side clamps. C When the high limit is exceeded, the gate-source voltage of the first NMOS tube MN1 increases, but because it conducts a fixed current I1, the drain-source voltage of the first NMOS tube MN1 decreases, causing the gate potential of the fourth PMOS tube MP4 to decrease, and the drain potential of the fourth PMOS tube MP4 to increase, turning on the third NMOS tube MN3, pulling down V C Implements high-side clamping of the error amplifier EA output. V C When the voltage is less than the lower limit, the gate-source voltage of the second NMOS tube MN2 decreases, the drain-source voltage of the second NMOS tube MN2 increases, the gate voltage of the fourth NMOS tube MN4 with the gate and drain shorted increases, resulting in the gate voltage of the fifth NMOS tube MN5 increasing, the gate-source voltage of the fifth NMOS tube MN5 increases, and a large current flows through the fifth NMOS tube MN5 into the output of the error amplifier EA to the ground, limiting V C The minimum value of , realizes the low-side clamping of the error amplifier EA output.

[0019] For ease of explanation Figure 3 Zhongzheng valley current I P1 and negative valley current IP2 How is it produced? First, Figure 4 This figure describes in detail the positive valley current I P1 and negative valley current I P2 How to make a difference and determine the valley current limit. The function of the valley current limit is to compare the inductor current with the valley current limit to generate a signal to turn off the lower tube and turn on the upper tube. Figure 4 The current differential valley limit comparison circuit principle is that the positive valley current I is controlled by the error amplifier EA. P1 and negative valley current I P2 The inductor current I flows through the two mirror transistors of the power lower tube NLD1, namely the seventh NMOS tube MN7 and the sixth NMOS tube MN6, generating a voltage drop. When the power lower tube NLD1 is turned on, the inductor current I L Linearly decreases, SW voltage increases, and the voltage at the negative input of the comparator increases. When the voltage at the negative terminal of the comparator exceeds the voltage at the positive terminal, the comparator output becomes 0, and the inductor current I L The valley current limit is triggered, the lower power tube NLD1 is turned off, and the upper power tube NLD2 is turned on to enter the next cycle.

[0020] According to V + =V-calculated valley current limit I LS_LIMIT

[0021]

[0022] Where R ON,MN6 is the on-resistance of the mirror tube MN6, R ON,MN7 is the on-resistance of the mirror tube MN7, R ON,LS is the on-resistance of the power tube NLD1.

[0023] Back to Figure 3 , when the load is heavy, the first NMOS tube MN1 is turned on, otherwise the positive valley current I P1 is zero and cannot provide the required valley current limit I LS_LIMIT At this time, the third PMOS tube MP3 outputs a positive valley current I P1 , this current is related to the error amplifier EA output V C is positively correlated, so the heavier the load, the LS_LIMIT The larger the error amplifier EA output V C At the same time, current flows into the resistor R1 through the second PMOS tube MP2 to raise the source voltage of the first NMOS tube MN1, thereby raising the output voltage V of the error amplifier EA. C, forcing the second NMOS tube MN2 to work in the linear region, the drain-source voltage of the second NMOS tube MN2 is low, and the gate voltage of the fourth NMOS tube MN4 with the gate-drain short-circuited is very low, resulting in the gate-source voltage of the fifth NMOS tube MN5 being less than the threshold voltage, and the fifth NMOS tube MN5 is turned off, and the negative valley current I P2 is zero.

[0024] At this time, the valley current limit I LS_LIMIT for

[0025]

[0026] The output of the error amplifier EA is V C As the load decreases, the valley current limit I LS_LIMIT When the load drops to zero, if the load continues to decrease, the Buck converter output increases and the feedback voltage V FB Increase, V C The drain-source voltage of the second NMOS tube MN2 increases, and the gate voltage of the fourth NMOS tube MN4 with the gate and drain shorted increases, causing the fifth NMOS tube MN5 to turn on. The current flows through the fifth NMOS tube MN5 into the output of the error amplifier EA to the ground. The current is copied by the current mirror composed of the fifth PMOS tube MP5 and the sixth PMOS tube MP6 to obtain a negative valley current I P2 , this current is related to the error amplifier EA output V C The width-to-length ratio of the first PMOS tube MP1 is much greater than that of the sixth PMOS tube MP6, so that a large current flows into the drain of the first NMOS tube MN1 through the first PMOS tube MP1, raising the gate voltage of the third PMOS tube MP3, turning off the third PMOS tube MP3, and the positive valley current I P1 The function of the first PMOS tube MP1 is to P2 When the positive valley current I P1 Set to zero to achieve smooth switching between positive and negative valley current limits.

[0027] At this time, the valley current limit I LS_LIMIT for

[0028]

[0029] Figure 5 This is the simulation waveform for verifying the function of the positive and negative valley current generating circuit proposed by the present invention. In order to facilitate the verification of the error amplifier EA output V C High and low side clamping and positive and negative valley current limit I P1 and I P2 ,according to Figure 3The dotted line shows the connection method, which connects the error amplifier EA into a unit gain negative feedback form, and scans the voltage V of the in-phase terminal of the error amplifier EA from 0V to 2.5V DC. P The results show that the error amplifier EA outputs V C The effective range is 0.6V to 1.9V, the low side clamp is 0.6V, and the high side clamp is 1.9V. C Within the effective range, V C Greater than 0.7V, I P2 is zero, I P1 With V C Positive correlation; V C Less than 0.7V, I P1 is zero, I P2 With V C Negatively correlated. C Reduce, I P2 When generated P1 It is exactly zero, achieving smooth switching between positive and negative valley current limits.

[0030] Figure 6 The simulation waveform of the load change of the ACOT controlled Buck converter using the present invention. The load current changes slowly from 0A to 0.6A in the time period from 2.6ms to 3.6ms. The simulation results show that the output V C The load current changes slowly from 0.62V to 1.64V. The valley value of the inductor current changes slowly from -0.05A to 0.55A, and the valley current smoothly passes through zero at 2.675ms. During the load current slow change process, the output voltage of the Buck converter is stable at 5V.

[0031] The present invention can provide a valley current limit with positive and negative smooth switching for an ACOT-controlled Buck converter supporting an inductor reverse flow option, so that the valley current can smoothly pass zero during load changes. The Buck converter using the present invention can not only be in a discontinuous conduction state under light load to obtain high efficiency, but also allow inductor reverse flow to be in a continuous conduction state under light load, thereby maintaining the characteristic of low output ripple.

Claims

1. A valley current limit generating circuit for an ACOT controlled Buck converter, characterized in that: It includes an error amplifier EA, a positive valley current generating circuit, a negative valley current generating circuit and a current differential valley limit comparison circuit; The error amplifier EA is connected to the Buck internal reference voltage in the same phase. V ref , the feedback voltage of the inverting terminal Buck chip V FB , the output end is connected to the input end of the positive valley current generating circuit and the input end of the negative valley current generating circuit; the output end of the positive valley current generating circuit and the output end of the negative valley current generating circuit are connected to the input end of the current differential valley limit comparison circuit; the output end of the current differential valley limit comparison circuit is connected to the logic and driving module of the Buck converter; The positive valley current generating circuit includes a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a first resistor R 1. First current source I 1; The negative valley current generating circuit includes a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a second current source I 2. The third current source I 3 and the first capacitor C 1; The gate of the first NMOS transistor MN1 is connected to the output end of the error amplifier EA, and the source of the first NMOS transistor MN1 is connected to the first resistor R 1, the first resistor R The other end of 1 is grounded, and the drain of the first NMOS tube MN1 is connected to the first current source I 1 and the gate of the second PMOS tube MP2; the first current source I 1 is connected to the power supply; the gate of the first PMOS tube MP1 is connected to the gate of the sixth PMOS tube MP6, the source of the first PMOS tube MP1 is connected to the power supply, and the drain of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2; the source of the second PMOS tube MP2 is connected to the power supply, and the drain of the second PMOS tube MP2 is connected to the source of the first NMOS tube MN1; the gate of the third PMOS tube MP3 is connected to the gate of the second PMOS tube MP2, and the source of the third PMOS tube MP3 is connected to the power supply; The gate of the fourth PMOS tube MP4 is connected to the gate of the third PMOS tube MP3, the source of the fourth PMOS tube MP4 is connected to the power supply, and the drain of the fourth PMOS tube MP4 is connected to the second current source I 2, the first capacitor C 1 and the gate of the third NMOS tube MN3; the second current source I 2 and the other end of the first capacitor C The other end of 1 is grounded; the gate of the second NMOS tube MN2 is connected to the source of the fifth NMOS tube MN5, the source of the second NMOS tube MN2 is grounded, and the drain of the second NMOS tube MN2 is connected to the source of the fourth NMOS tube MN4; the source of the third NMOS tube MN3 is grounded, and the drain of the third NMOS tube MN3 is connected to the source of the fifth NMOS tube MN5; the gate and drain of the fourth NMOS tube MN4 are short-circuited; the drain of the fourth NMOS tube MN4 is connected to the third current source I 3, the third current source I The other end of 3 is connected to the power supply; the gate of the fifth NMOS tube MN5 is connected to the gate of the fourth NMOS tube MN4, the drain of the fifth NMOS tube MN5 is connected to the drain of the sixth PMOS tube MP6; the source of the fifth PMOS tube MP5 is connected to the power supply, the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6; the source of the sixth PMOS tube MP6 is connected to the power supply; the second current source I 2. The first capacitor C 1 and the third NMOS tube MN3 form a high-side clamp of the error amplifier EA output; the third current source I 3. The second NMOS transistor MN2, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5 and the sixth PMOS transistor MP6 form a low-side clamp outputted by the error amplifier EA; The current differential valley limit comparison circuit includes a sixth NMOS tube, a seventh NMOS tube and a comparator COMP; the gate of the sixth NMOS tube MN6 is connected to the gate drive signal of the Buck power down tube, the drain of the sixth NMOS tube MN6 is connected to the positive input terminal of the comparator COMP and the drain of the fifth PMOS tube, and the source of the sixth NMOS tube MN6 is grounded; the gate of the seventh NMOS tube MN7 is connected to the gate drive signal of the Buck power down tube, the drain of the seventh NMOS tube MN7 is connected to the drain of the Buck power down tube NLD1, and the source of the seventh NMOS tube MN7 is connected to the negative input terminal of the comparator COMP and the drain of the third PMOS tube; the output terminal of the comparator is connected to the Buck logic and drive module.

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