A circuit for compensating analog front-end parasitic capacitance using successive approximation

Abstract

The present invention belongs to the field of analog integrated circuit technology, and particularly relates to a circuit for compensating for analog front-end parasitic capacitance using a successive approximation method, which can be applied to quantizing sensor signals and collecting bioelectric signals. The present invention adopts a fully differential structure, a successive approximation control logic module, and an N-bit binary positive feedback capacitor array C. PF In a successive approximation manner, according to the stability of the analog front-end circuit, adjust the connected C PF The capacitance value quickly compensates the parasitic capacitance of the analog front end to the ground. When the correction signal is applied to the analog front end circuit, due to the positive feedback capacitor C PF The Maitreya effect, the analog front-end circuit is connected to the positive feedback capacitor C PF The capacitance value of the input node determines whether the input node is stable or unstable; thus, by detecting the stability of the analog front-end circuit, it is determined whether the connected positive feedback capacitor is appropriate. The present invention can compensate for the parasitic capacitance of the input node over a large range, quickly, and with high precision, thereby significantly improving the input impedance of the acquisition circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and in particular relates to a circuit for compensating for analog front-end parasitic capacitance using a successive approximation method, which can be applied to the acquisition of quantized sensor signals and bioelectric signals. Background Art

[0002] Biopotential signals are characterized by small amplitude and low frequency. Therefore, biopotential signal acquisition circuits require the analog front-end to have sufficiently high input impedance to ensure sufficient signal strength for subsequent circuit amplification and processing. High input impedance also improves the acquisition circuit's common-mode rejection ratio, enhancing its ability to suppress interference. However, the analog front-end input nodes contain numerous parasitic capacitances to ground, significantly reducing the input impedance of the analog front-end circuit, making it difficult for the acquisition circuit to effectively extract biopotential signals.

[0003] To address the issue of reduced input impedance in analog front-ends due to parasitic capacitance, some literature has proposed a method that uses a positive feedback loop to compensate for some of the parasitic capacitance to ground. This method effectively addresses the impedance reduction caused by input capacitance, but because the input node also contains other capacitance to ground, including ESD parasitic capacitance to ground and PAD capacitance to ground, this method can only increase the input impedance several times. Based on the method of using a positive feedback loop to compensate for some of the parasitic capacitance to ground, some literature has proposed making the positive feedback capacitor into a capacitor array. By detecting the stability of the analog front-end circuit, a counter is used to compensate for the analog front-end input capacitance. However, the convergence time of the method of making the positive feedback capacitor into a capacitor array increases with the number of bits in the capacitor array, and the compensation accuracy of the input capacitance is relatively limited. Summary of the Invention

[0004] In response to the above-mentioned problems or shortcomings, in order to compensate for the parasitic capacitance of the analog front end and improve the input impedance of the bioelectric signal acquisition circuit, the present invention provides a circuit for compensating the parasitic capacitance of the analog front end by successive approximation, which can compensate the parasitic capacitance of the input node over a large range and quickly, thereby greatly improving the input impedance of the acquisition circuit.

[0005] A circuit for compensating the parasitic capacitance of an analog front end in a successive approximation manner is a fully differential structure, comprising a correction signal generating module 100, a correction capacitor C CAL 、 Input parasitic capacitance to ground (C PAD , C BUF , C ESD , C P ), input capacitor C IN , Fully differential op amp 102, Negative feedback capacitor C FB , DC bias resistor R FB , positive feedback capacitor C PFand successive approximation control logic module 101, as shown in the attached Figure 1 shown.

[0006] The correction signal generating module 100 generates a correction signal V CAL And output to the correction capacitor C CAL The lower plate.

[0007] The correction capacitor C CAL Including correction capacitor C CAL1 and correction capacitor C CAL2 , correction capacitor C CAL1 The upper plate is connected to one end of the switch S1, and the correction capacitor C CAL2 The upper plate is connected to one end of switch S2.

[0008] The other end of switch S1 is connected to the input parasitic capacitance C ESD1 and C P1 The upper plate, input capacitor C IN1 The lower plate and the positive feedback capacitor C PF2 The other end of switch S1 is also connected to the input parasitic capacitance C to ground through switch S3. PAD1 with C BUF1 The upper plate.

[0009] The other end of switch S2 is connected to the input parasitic capacitance C ESD2 and C P2 The upper plate, input capacitor C IN2 The lower plate and the positive feedback capacitor C PF1 The other end of switch S2 is also connected to the input parasitic capacitance C to ground through switch S4. PAD2 with C BUF2 The upper plate.

[0010] Input parasitic C PAD 、C BUF 、C ESD and C P The lower plates are connected to ground potential.

[0011] The input capacitor C IN Including C IN1 and C IN2 ; C IN1 The upper plate is connected to the negative input terminal of the fully differential operational amplifier 102 and the negative feedback capacitor C FB1 The upper plate and the DC bias resistor R FB1 Input terminal; C IN2 The upper plate is connected to the positive input terminal of the fully differential operational amplifier 102 and the negative feedback capacitor C FB2 The upper plate and the DC bias resistor R FB2 The input terminal.

[0012] The negative output terminal of the fully differential operational amplifier 102 is connected to the negative feedback capacitor C FB2 The lower plate, DC bias resistor R FB2 The output terminal, positive feedback capacitor C PF2 The positive output terminal of the fully differential operational amplifier 102 is connected to the negative feedback capacitor C FB1 The lower plate, DC bias resistor R FB1 The output terminal, positive feedback capacitor C PF1 and the negative input terminal of the successive approximation control logic module 101.

[0013] The output terminals of the successive approximation control logic module 101 are connected to the positive feedback capacitor array C PF control terminal.

[0014] The positive feedback capacitor C PF Including C PF1 and C PF2 , are all the same N-bit binary positive feedback capacitor arrays, and their unit capacitance is C U For an N-bit binary positive feedback capacitor array C PF Yes (as attached) Figure 2 As shown): by the binary capacitor C PF 1 to C PF_N And one-to-one corresponding control switches Q1 to QN, each corresponding control signal is Q_1 to Q_N, C PF_N The capacitance value is 2 N-1 C U , that is, C PF_N-1 twice; the lowest capacitance C PF_1 Connected to the control switch Q_1, the second lowest capacitor C PF_2 Connected to the control switch Q_2, and so on; capacitor C PF_1 to C PF_N The upper plates are connected together as a positive feedback capacitor C PF The input terminal, capacitor C PF_1 to C PF_N The lower plate of the analog front-end circuit is connected to the control switches Q1 to QN one by one, and the other ends of all the control switches Q1 to QN are connected together; the control signals Q_1 to Q_N are divided into two signals: logic high and logic low. When the control signal is logic high, the corresponding control switch is closed, so that the positive feedback capacitor C in the analog front-end circuit is connected. PF Capacitance value changes.

[0015] The entire analog front-end circuit is divided into working mode and compensation mode. When switches S1 and S2 are closed and S3 and S4 are disconnected, the circuit is in compensation mode and begins to perform successive approximation compensation on the parasitic capacitance of the op amp input node. After compensation, switches S3 and S4 are closed and S1 and S2 are disconnected, and the circuit switches to working mode.

[0016] The above circuit for compensating the parasitic capacitance of the analog front end in a successive approximation manner quickly compensates the parasitic capacitance of the analog front end to ground according to the stability of the analog front end circuit. Figure 3 As shown in the figure, when the correction signal is applied to the analog front-end circuit, due to the positive feedback capacitor C PF The Maitreya effect, the analog front-end circuit is connected to the positive feedback capacitor C PF The capacitance value determines whether the circuit is stable or unstable; thus, by testing the stability of the analog front-end circuit, the appropriateness of the connected positive feedback capacitor can be determined. When the analog front-end circuit is in a stable state (marked as 0), the output signal decreases as the input correction signal decreases. When the analog front-end circuit is in an unstable state (marked as 1), the output signal remains unchanged as the input correction signal decreases.

[0017] After determining the stability of the analog front-end circuit, the positive feedback capacitor C PF For an N-bit binary positive feedback capacitor array, it only takes 2N-3 clock cycles at most to complete the quantization and compensation of the input node's capacitance to ground. The maximum quantization range is as follows:

[0018] C MAX =(G-1)×(2 N C U -1)

[0019] Where G is the input capacitance C IN With the negative feedback capacitor C FB ratio.

[0020] The quantization method of the analog front-end circuit for successive approximation compensation of parasitic capacitance comprises the following steps:

[0021] Step 1: Set the N-bit binary positive feedback capacitor array C PF The lowest capacitance C in PF_1 and the second lowest capacitor C PF_2 The analog front-end circuit is connected by controlling switches Q1 and Q2, and the correction capacitor C CAL The lower plate applies the correction signal V generated by the correction signal generating module 100 CAL , observe the stability of the circuit.

[0022] Step 2: Check the stability of the analog front-end circuit. If the status is 0, it means the circuit is in a stable state. Then, the capacitor C PF_3 By controlling the switch Q3 to access the analog front-end circuit, a forward search is performed and the correction signal V is applied again. CAL , observe the stability of the analog front-end circuit:

[0023] If the state of the analog front-end circuit is still 0, the positive feedback capacitor C in the analog front-end circuit is connected one by one through the corresponding control switch from low to high. PF The total value increases until C is connected PF_M The analog front-end circuit state is 1, the circuit is in an unstable state, the forward search ends, 2≤M≤N. Note that the positive feedback capacitor array is not necessarily all connected to the analog front-end circuit. When the analog circuit state is reversed, the capacitor C PF_M It is no longer connected to the circuit.

[0024] Step 3: When the analog front-end circuit switches the control switch QM, the circuit state changes from 0 to 1. At this time, the reverse search is turned on, that is, the control switch QM state remains unchanged, and the capacitor C PF_M-1 By controlling the switch QM-1 to be disconnected, the correction signal V CAL , monitor the stability of the analog front-end circuit:

[0025] If the circuit state is 1, the capacitor C PF_M-2 By controlling the switch QM-2 to be disconnected, the correction signal VCAL is applied to monitor the stability of the analog front-end circuit; if the circuit state is 0, the capacitor C PF_M-2 By controlling the switch QM-2 to disconnect, the capacitor C PF_M-1 Connect to the analog front-end circuit through the control switch QM-1. If the circuit state is 1, the capacitors are disconnected from the circuit one by one through the corresponding control switch from high to low; if the circuit state is 0, the current capacitor is disconnected through the control switch and the next capacitor is connected until the lowest positive feedback capacitor C PF_1 Disconnect from the circuit.

[0026] To summarize, the present invention addresses the problem of insufficient input impedance of traditional fixed or counter-type bioelectric signal acquisition circuits, and provides a circuit with a fully differential structure that compensates for the parasitic capacitance of the analog front end by successive approximation. This circuit can compensate for the parasitic capacitance of the input node over a large range, quickly, and with high precision, thereby significantly improving the input impedance of the acquisition circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A circuit diagram of the present invention;

[0028] Figure 2 Schematic diagram of the circuit structure of the N-bit binary positive feedback capacitor array of the present invention;

[0029] Figure 3 This is a schematic diagram of the stability state detection principle of the analog front-end circuit in the present invention;

[0030] Figure 4 Schematic diagram of the control switch timing of the N-bit binary positive feedback capacitor array according to an embodiment. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0032] like Figure 4 FIG2 is a schematic diagram of the control switch timing of the N-bit binary positive feedback capacitor array of the present invention. The method of compensating the parasitic capacitance of the analog front end by successive approximation method includes the following steps:

[0033] Step 1: Replace the lowest bit capacitor C in the N-bit binary positive feedback capacitor array. PF_1 and the second lowest capacitor C PF_2 The analog front-end circuit is connected by controlling switches Q1 and Q2, and the correction capacitor C CAL The lower plate applies the correction signal V generated by the correction signal generating module 100 CAL , observe the stability of the circuit.

[0034] Step 2: Check the stability of the analog front-end circuit. If the state is 0, it means the circuit is in a stable state. Then, the positive feedback capacitor C PF_3 By controlling the switch Q3 to access the analog front-end circuit, a forward search is performed and the correction signal V is applied again. CAL , observe the system stability.

[0035] At this time, the analog front-end circuit state is 0, then the positive feedback capacitor C PF_4 The analog front-end circuit is connected by controlling the switch Q4, and the correction signal V is applied again. CAL , observe the system stability. Connect the positive feedback capacitors to the circuit one by one from low to high through the corresponding control switches until the highest positive feedback capacitor C PF_N Connect to the analog front-end circuit through the control switch QN and apply the correction signal V CAL After that, the state of the analog front-end circuit changes from 0 to 1, the circuit is in an unstable state, and the forward search ends.

[0036] Step 3: When the highest positive feedback capacitor C PF_N After the analog front-end circuit is connected through the control switch QN, the state of the analog front-end circuit changes from 0 to 1. At this time, the reverse search is turned on, that is, the state of the control switch QN remains unchanged, and the positive feedback capacitor C PF_N-1 By controlling the switch QN-1 to be disconnected, the correction signal V CAL, monitor the stable state of the analog front-end circuit. At this time, the circuit state is 0, then the positive feedback capacitor C PF_N-2 By controlling the switch QN-2 to disconnect, the positive feedback capacitor C PF_M-1 Connect to the analog front-end circuit through the control switch QN-1. Apply the correction signal V CAL , monitor the stability of the analog front-end circuit. If the circuit status is all 1, the positive feedback capacitors are disconnected from the circuit one by one through the corresponding control switches from high to low until the lowest positive feedback capacitor C PF_1 In this embodiment, when M=N, the circuit realizes stable state switching, and the circuit of the present invention must satisfy the existence of M.

[0037] From the above embodiments, it can be seen that the present invention adopts a fully differential structure, a successive approximation control logic module, and an N-bit binary positive feedback capacitor array C PF In a successive approximation manner, according to the stability of the analog front-end circuit, adjust the connected C PF The capacitance value quickly compensates the parasitic capacitance of the analog front end to the ground. When the correction signal is applied to the analog front end circuit, due to the positive feedback capacitor C PF The Maitreya effect, the analog front-end circuit is connected to the positive feedback capacitor C PF The capacitance value of the input node determines whether the input node is stable or unstable; thus, by detecting the stability of the analog front-end circuit, it is determined whether the connected positive feedback capacitor is appropriate. The present invention can compensate for the parasitic capacitance of the input node over a large range, quickly, and with high precision, thereby significantly improving the input impedance of the acquisition circuit.

Claims

1. A circuit for compensating for parasitic capacitance of an analog front-end using successive approximation method, characterized in that: It is a fully differential structure, including a correction signal generating module 100, a correction capacitor C CAL , input parasitic capacitance to ground, input capacitance C IN , Fully differential op amp 102, Negative feedback capacitor C FB , DC bias resistor R FB , positive feedback capacitor C PF and successive approximation control logic module 101; wherein the input parasitic capacitance to ground includes C PAD , C BUF , C ESD and C P ; The correction signal generating module 100 generates a correction signal V CAL , and output to the correction capacitor C CAL The lower plate; The correction capacitor C CAL Including correction capacitor C CAL1 and correction capacitor C CAL2 , correction capacitor C CAL1 The upper plate is connected to one end of the switch S1, and the correction capacitor C CAL2 The upper plate is connected to one end of the switch S2; The other end of switch S1 is connected to the input parasitic capacitance C ESD1 and C P1 The upper plate, input capacitor C IN1 The lower plate and the positive feedback capacitor C PF2 The other end of switch S1 is also connected to the input parasitic capacitance C to ground through switch S3. PAD1 with C BUF1 The upper plate; The other end of switch S2 is connected to the input parasitic capacitance C ESD2 and C P2 The upper plate, input capacitor C IN2 The lower plate and the positive feedback capacitor C PF1 The other end of switch S2 is also connected to the input parasitic capacitance C to ground through switch S4. PAD2 with C BUF2 The upper plate; Input to ground parasitic capacitance C PAD 、C BUF 、C ESD and C P The lower plates are connected to ground potential; The input capacitor C IN Including C IN1 and C IN2 ; C IN1 The upper plate is connected to the negative input terminal of the fully differential operational amplifier 102 and the negative feedback capacitor C FB1 The upper plate and the DC bias resistor R FB1 Input terminal; C IN2 The upper plate is connected to the positive input terminal of the fully differential operational amplifier 102 and the negative feedback capacitor C FB2 The upper plate and the DC bias resistor R FB2 The input terminal; The negative output terminal of the fully differential operational amplifier 102 is connected to the negative feedback capacitor C FB2 The lower plate, DC bias resistor R FB2 The output terminal, positive feedback capacitor C PF2 The positive output terminal of the fully differential operational amplifier 102 is connected to the negative feedback capacitor C FB1 The lower plate, DC bias resistor R FB1 The output terminal, positive feedback capacitor C PF1 and the negative input terminal of the successive approximation control logic module 101; The output terminals of the successive approximation control logic module 101 are connected to the positive feedback capacitor array C PF The control terminal; The positive feedback capacitor C PF Including C PF1 and C PF2 , are all the same N-bit binary positive feedback capacitor arrays, and their unit capacitance is C U ; For an N-bit binary positive feedback capacitor array C PF There is: binary capacitance C PF_1 to C PF_N And one-to-one corresponding control switches Q1 to QN, each corresponding control signal is Q_1 to Q_N, C PF_N The capacitance value is 2 N-1 C U , that is, C PF_N-1 twice; the lowest capacitance C PF_1 Connected to the control switch Q_1, the second lowest capacitor C PF_2 Connected to the control switch Q_2, and so on; capacitor C PF_1 to C PF_N The upper plates are connected together as a positive feedback capacitor C PF The input terminal, capacitor C PF_1 to C PF_N The lower plate of the analog front-end circuit is connected to the control switches Q1 to QN one by one, and the other ends of all the control switches Q1 to QN are connected together; the control signals Q_1 to Q_N are divided into two signals: logic high and logic low. When the control signal is logic high, the corresponding control switch is closed, so that the positive feedback capacitor C in the analog front-end circuit is connected. PF Capacitance value changes; The entire analog front-end circuit is divided into working mode and compensation mode. When switches S1 and S2 are closed and S3 and S4 are disconnected, the circuit is in compensation mode and begins to perform successive approximation compensation on the parasitic capacitance of the op amp input node. After compensation is completed, switches S3 and S4 are closed and S1 and S2 are disconnected, and the circuit switches to working mode. When the correction signal is applied to the analog front-end circuit, due to the positive feedback capacitor C PF The Maitreya effect, the analog front-end circuit is connected to the positive feedback capacitor C PF The capacitance value determines whether it is in a stable or unstable state; when the analog front-end circuit is in a stable state, the output signal decreases as the input correction signal decreases; when the analog front-end circuit is in an unstable state, the output signal remains unchanged when the input correction signal decreases.

2. The circuit for compensating analog front-end parasitic capacitance using successive approximation method according to claim 1, wherein: The specific quantification method includes the following steps: Step 1: Set the N-bit binary positive feedback capacitor array C PF The lowest capacitance C in PF_1 and the second lowest capacitor C PF_2 The analog front-end circuit is connected by controlling switches Q1 and Q2, and the correction capacitor C CAL The lower plate applies the correction signal V generated by the correction signal generating module 100 CAL , observe the stability of the circuit; Step 2: Check the stability of the analog front-end circuit. If the status is 0, it means the circuit is in a stable state. Then, the capacitor C PF_3 By controlling the switch Q3 to access the analog front-end circuit, a forward search is performed and the correction signal V is applied again. CAL , observe the stability of the analog front-end circuit: If the state of the analog front-end circuit is still 0, the positive feedback capacitor C in the analog front-end circuit is connected one by one through the corresponding control switch from low to high. PF The total value increases until C is connected PF_M The analog front-end circuit state is 1, the circuit is in an unstable state, the forward search ends, 2≤M≤N; when the analog front-end circuit state is reversed, the capacitor C PF_M It is no longer connected to the circuit; Step 3: When the analog front-end circuit switches the control switch QM, the circuit state changes from 0 to 1. At this time, the reverse search is turned on, that is, the control switch QM state remains unchanged, and the capacitor C PF_M-1 By controlling the switch QM-1 to be disconnected, the correction signal V CAL , monitor the stability of the analog front-end circuit: If the circuit state is 1, the capacitor C PF_M-2 By controlling the switch QM-2 to be disconnected, the correction signal VCAL is applied to monitor the stability of the analog front-end circuit; if the circuit state is 0, the capacitor C PF_M-2 By controlling the switch QM-2 to disconnect, the capacitor C PF_M-1 Connect to the analog front-end circuit through the control switch QM-1; if the circuit state is 1, the capacitors are disconnected from the circuit one by one through the corresponding control switch from high to low; if the circuit state is 0, the current capacitor is disconnected through the control switch and the next capacitor is connected until the lowest capacitor C PF_1 Disconnect from the circuit.

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