Electroluminescent display

Abstract

Disclosed is an electroluminescent display comprising: a pixel; a low resistance line located at one side of the pixel and having a connection portion; an insulating layer on the low resistance line; a low resistance connection terminal located on the insulating layer and connected to the connection portion; a passivation layer on the low resistance connection terminal; a planarization layer on the passivation layer; a cathode contact hole exposing a portion of the low resistance connection terminal. The low resistance line comprises an opening region overlapping with a middle portion of the low resistance connection terminal at the connection portion. The low resistance connection terminal is connected to a first side and a second side of the low resistance line. The cathode is connected to the low resistance connection terminal via the cathode contact hole.

Description

Technical Field

[0001] This disclosure relates to an electroluminescent display. In particular, this disclosure relates to an electroluminescent display that exhibits improved image quality stability by eliminating or blocking lateral leakage current between adjacent pixels. Furthermore, this disclosure relates to an electroluminescent display that exhibits improved image quality stability by reducing the resistance of the cathode employing auxiliary cathode lines. Background Technology

[0002] Recently, various types of displays have been developed, such as cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma display panels (PDPs), and electroluminescent displays. These various types of displays are used to display image data of various products, such as computers, mobile phones, bank deposit and withdrawal machines (ATMs), and vehicle navigation systems, according to their unique characteristics and purposes.

[0003] In particular, organic light-emitting diode (OLED) displays, as self-emissive displays, possess excellent optical performance, such as wide viewing angles and high color reproduction, and their applications are gradually expanding, making them a key component in high-quality image display devices. Due to these advantages, they are attracting attention as the most suitable display devices for achieving ultra-high resolution displays exceeding 4K. As resolution increases, the size of the light-emitting area within a pixel also becomes smaller. To maximize the size of the light-emitting area, a top-emitting structure is employed.

[0004] In top-emitting displays, which are advantageous for ultra-high resolution, transparent conductive materials are used for the cathode. Because transparent conductive materials have a higher sheet resistance than metallic materials, maintaining a constant cathode voltage can be difficult when implementing large-area display devices. Therefore, in large-area electroluminescent displays with top-emitting characteristics, structures for connecting to signal lines with low resistance may be needed to reduce the sheet resistance of the cathode.

[0005] When achieving ultra-high resolution structures, the size of the components used to connect to low-resistance lines also becomes smaller. As a result, the connection between the components and the low-resistance lines may not be properly established. When this connection defect occurs, a structure is needed that can repair the low-resistance lines, thus enabling a proper connection to them. Summary of the Invention

[0006] To address the aforementioned problems, the present disclosure aims to provide an electroluminescent display with a large area, ultra-high resolution, and excellent image quality. Another object of the present disclosure is to provide an electroluminescent display in which the cathode voltage can be kept constant in a top-emitting display suitable for achieving an ultra-high resolution structure. Yet another object of the present disclosure is to provide an electroluminescent display having a structure that repairs connection defects when the cathode and low-resistivity lines are connected at ultra-high resolution density.

[0007] To achieve the above-mentioned objectives of this disclosure, the electroluminescent display according to this disclosure includes: a pixel on a substrate, the pixel including an anode, a light-emitting layer, and a cathode; a low-resistivity line located on one side of the pixel, the low-resistivity line having a connecting portion; an insulating layer on the low-resistivity line; a low-resistivity connection terminal on the insulating layer, the low-resistivity connection terminal being connected to the connecting portion of the low-resistivity line; a passivation layer on the low-resistivity connection terminal; a planarization layer on the passivation layer; a cathode contact hole exposing a portion of the low-resistivity connection terminal; and wherein the low-resistivity line includes an opening region between a first side and a second side of the low-resistivity line, the opening region overlapping with a middle portion of the low-resistivity connection terminal at the connecting portion, wherein the low-resistivity connection terminal is connected to the first side and the second side of the low-resistivity line, and wherein the cathode is connected to the portion of the low-resistivity connection terminal exposed via the cathode contact hole.

[0008] In one embodiment, the electroluminescent display includes: a low-resistance line on a substrate; a low-resistance connection terminal connected to the low-resistance line; a pixel including an anode, a light-emitting layer, and a cathode, wherein the anode does not overlap with the low-resistance line; a passivation layer on the low-resistance connection terminal; a planarization layer on the passivation layer; and a contact hole passing through a portion of the passivation layer and a portion of the planarization layer overlapping with the low-resistance connection terminal, wherein a portion of the light-emitting layer is disposed in the contact hole such that the portion of the light-emitting layer is located between a first portion of the low-resistance connection terminal and a portion of the cathode disposed in the contact hole, and a second portion of the low-resistance connection terminal penetrates the portion of the light-emitting layer and connects to the portion of the cathode disposed in the contact hole.

[0009] The electroluminescent display according to this disclosure provides a top-emitting electroluminescent display capable of maximizing the aperture ratio of the light-emitting area to the pixel area to achieve ultra-high resolution. In particular, when realizing a large-area electroluminescent display with a long diagonal length, this disclosure provides a top-emitting electroluminescent display having a structure for connecting low-resistivity lines to the cathode to maintain a constant resistance of the cathode film over the entire surface area. This disclosure can provide excellent and stable image quality by maintaining a constant cathode voltage in a large-area electroluminescent display. Even when achieving ultra-high resolution, connection defects may occur due to narrower pixel spacing and a smaller connection area between the low-resistivity lines and the cathode, the top-emitting electroluminescent display according to this disclosure can have a repair structure capable of recovering from these connection defects. Therefore, the electroluminescent display according to this disclosure can provide uniform image quality in both ultra-high resolution and large-area electroluminescent displays. Attached Figure Description

[0010] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated into and constituting a part of this application, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0011] Figure 1 This is a plan view illustrating a schematic structure of an electroluminescent display according to one embodiment of the present disclosure.

[0012] Figure 2 This is a circuit diagram illustrating the structure of a pixel included in an electroluminescent display according to one embodiment of the present disclosure.

[0013] Figure 3 This illustrates one embodiment of the present disclosure, such as... Figure 1 A magnified planar view of the structure between two adjacent pixels arranged as shown.

[0014] Figure 4 It is along Figure 3 The cross-sectional view along the cutting line I-I' is used to illustrate an electroluminescent display according to a first embodiment of the present disclosure.

[0015] Figure 5 It is shown Figure 4 An enlarged cross-sectional view of the circular portion "N" of the structure of the connector in the electroluminescent display according to the first embodiment of the present disclosure.

[0016] Figure 6 This is an enlarged cross-sectional view showing the structure of the connection portion in an electroluminescent display according to a second embodiment of the present disclosure.

[0017] Figure 7AThis is an enlarged cross-sectional view showing a contact failure occurring at the connection portion of an electroluminescent display according to the second embodiment of the present disclosure.

[0018] Figure 7B This is an enlarged cross-sectional view after a contact fault at the connection portion of the electroluminescent display according to the second embodiment of this disclosure has been resolved.

[0019] Figure 8 This is an enlarged cross-sectional view showing the structure of the connection portion in an electroluminescent display according to a third embodiment of the present disclosure.

[0020] Figure 9A This is an enlarged cross-sectional view showing a contact failure occurring at the connection portion of an electroluminescent display according to the third embodiment of this disclosure.

[0021] Figure 9B This is an enlarged cross-sectional view after a contact fault at the connection portion of the electroluminescent display according to the third embodiment of this disclosure has been resolved.

[0022] Figure 10 This is an enlarged cross-sectional view showing the structure of the connection portion in an electroluminescent display according to the fourth embodiment of the present disclosure.

[0023] Figure 11A This is an enlarged cross-sectional view showing a contact failure occurring at the connection portion of an electroluminescent display according to the fourth embodiment of the present disclosure.

[0024] Figure 11B This is an enlarged cross-sectional view after restoring a contact fault at the connection portion of the electroluminescent display according to the fourth embodiment of this disclosure.

[0025] Figure 12 This is a plan view showing the structure of an electroluminescent display according to the fifth embodiment of the present disclosure. Detailed Implementation

[0026] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following description of embodiments with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete, to assist those skilled in the art in fully understanding its scope. Furthermore, the scope of protection of this disclosure is defined by the claims and their equivalents.

[0027] The shapes, dimensions, scales, angles, quantities, etc., shown in the drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the details shown. Unless otherwise stated, the same reference numerals denote the same elements throughout the specification. In the following description, detailed descriptions of known functions or configurations may be omitted where such detailed descriptions might unnecessarily obscure important points of this disclosure.

[0028] Exemplary embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in all the drawings to denote the same or similar parts. It should be noted in the specification that the same reference numerals used to denote the same elements in other drawings are used for elements wherever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are not related to the basic configuration of this disclosure will be omitted. The terminology described in the specification should be understood as follows.

[0029] In this specification, where terms such as “comprising,” “having,” “including,” etc., are used, one or more other elements may be added unless terms such as “only” are used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0030] When constructing an element, the element is interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided.

[0031] In the description of various embodiments of this disclosure, when describing positional relationships, for example, when using terms such as "on," "above," "below," "over," "below," "beside," "next to," etc., to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless more restrictive terms such as "close," "direct," or "near" are used. For example, when an element or layer is disposed "on" another element or layer, a third layer or element may be inserted therein. Furthermore, if a first element is described as disposed "on" a second element, it does not necessarily mean that the first element is disposed above the second element in the drawing. The upper and lower parts of an object can change depending on the orientation of the object. Therefore, when a first element is described as disposed "on" a second element, depending on the orientation of the object, the first element may be disposed "below" or "above" the second element in the drawing or in the actual configuration.

[0032] When describing temporal relationships, discontinuous situations may be included when describing chronological order as such as "after", "following", "next", or "before", unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0033] It should be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms, as they are not used to define a particular order. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0034] In describing the various elements in this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish one element from another and not to define a particular nature, order, sequence, or number of elements. Where an element is described as “linked,” “connected,” or “joined” to another element, that element may be directly or indirectly connected to that other element, unless otherwise stated. It should be understood that one or more additional elements may be “inserted” between two elements described as “linked,” “connected,” or “joined” to each other.

[0035] It should be understood that the term "at least one" should be interpreted as including any and all combinations of one or more of the associated listed items. For example, "at least one of the first element, the second element, and the third element" means all combinations of the three listed elements, combinations of any two of the three elements, and each individual element (the first element, the second element, and the third element).

[0036] Features of the various embodiments of this disclosure may be partially or entirely linked or combined with each other, and may be interoperable with each other differently and technically driven, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0037] In the following, examples of display devices according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals are used in all the drawings to denote the same or similar parts. Since the scale of each element shown in the drawings may differ from the actual scale for ease of description, the present disclosure is not limited to the scales shown in the drawings.

[0038] This disclosure will be explained below with reference to the accompanying drawings. Figure 1 This is a plan view illustrating a schematic structure of an electroluminescent display according to one embodiment of the present disclosure. Figure 1In the diagram, the X-axis represents the direction parallel to the scan lines, the Y-axis represents the direction of the data lines, and the Z-axis represents the height direction of the display device according to one embodiment.

[0039] refer to Figure 1 The electroluminescent display includes a substrate 110, a gating (or scanning) driver 200, a data pad portion 300, a source driver IC (integrated circuit) 410, a flexible film 430, a circuit board 450, and a timing controller 500.

[0040] The substrate 110 may include an electrically insulating material or a flexible material. The substrate 110 may be made of glass, metal, or plastic, but is not limited to these. When the electroluminescent display is a flexible display, the substrate 110 may be made of a flexible material such as plastic. For example, the substrate 110 may include a transparent polyimide material.

[0041] The substrate 110 may include a display area AA and a non-display area NDA. The display area AA, which serves as the area for representing a video image, may be defined as, but is not limited to, the majority of the central area of ​​the substrate 110. Within the display area AA, multiple scan lines (or gate lines), multiple data lines, and multiple pixels P may be formed or disposed. Each pixel may include multiple sub-pixels SP. Each sub-pixel includes both scan lines and data lines. For example, one of the pixels P may include three or four sub-pixels SP.

[0042] The non-display area NDA, which is a region that does not display video images, can be defined in the peripheral area of ​​the substrate 110 surrounding all or part of the display area AA. A gating driver 200 and a data pad portion 300 can be formed or disposed in the non-display area NDA.

[0043] The gating driver 200 can provide a scanning (or gating) signal to the scan line according to the gating control signal received from the timing controller 500. The gating driver 200 can be formed as a GIP (in-panel gating driver) type at a non-display area NDA on either side of the display area AA on the substrate 110. GIP type means that the gating driver 200 is formed directly on the substrate 110.

[0044] The data pad portion 300 can provide data signals to the data lines based on data control signals received from the timing controller 500. The data pad portion 300 can be fabricated as a driver chip and mounted on the flexible film 430. Furthermore, the flexible film 430 can be attached as a TAB (with auto-bonding) type to the non-display area NDA on either side of the display area AA on the substrate 110.

[0045] The source driver IC 410 can receive digital video data and source control signals from the timing controller 500. The source driver IC 410 can convert the digital video data into analog data voltages based on the source control signals and then supply them to the data lines. When the source driver IC 410 is manufactured as a chip, it can be mounted on the flexible film 430 as a COF (chip-on-film) or COP (chip-on-plastic) type.

[0046] The flexible film 430 may include multiple first connection lines connecting the data pad portion 300 to the source driver IC 410, and multiple second connection lines connecting the data pad portion 300 to the circuit board 450. The flexible film 430 may be attached to the data pad portion 300 using an anisotropic conductive film, so that the data pad portion 300 can be connected to the first connection lines of the flexible film 430.

[0047] The circuit board 450 can be connected to the flexible film 430. The circuit board 450 may include multiple circuits implemented as driver chips. For example, the circuit board 450 may be a printed circuit board or a flexible printed circuit board.

[0048] The timing controller 500 can receive digital video data and timing signals from an external system board via cables from the circuit board 450. The timing controller 500 can generate gating control signals for controlling the operating timing of the gating driver 200 and source control signals for controlling the source driver IC 410 based on the timing signals. The timing controller 500 can provide gating control signals to the gating driver 200 and source control signals to the source driver IC 410. Depending on the product type, the timing controller 500 and the source driver IC 410 can be integrated into a single chip and mounted on the substrate 110.

[0049] refer to Figure 1 The planar structure of the pixel array P shown in this disclosure allows the electroluminescent display to have multiple pixels P arranged in a matrix. Each pixel P may include multiple subpixels SP (e.g., four subpixels). For example, one pixel P may include a red subpixel SPR, a green subpixel SPG, a blue subpixel SPB, and a white subpixel SPW. However, it is not limited to this; one pixel P may include three or five subpixels SP. The subpixels SP may be arranged at a predetermined distance (or gap) from each other. Furthermore, the pixels P may be arranged at a predetermined distance (or gap) from each other. Figure 1 An exemplary array is shown, in which the pixel gap between pixels P can be wider than the subpixel gap between subpixels SP. In another example, all subpixels SP can be arranged with subpixel gaps, without distinguishing between pixel gaps and subpixel gaps.

[0050] Figure 2This is a circuit diagram illustrating the structure of a sub-pixel included in an electroluminescent display according to one embodiment of the present disclosure. Figure 3 This illustrates one embodiment according to the present disclosure, such as... Figure 1 A magnified planar view of the structure between two adjacent pixels arranged as shown. Figure 4 It is along Figure 3 The cross-sectional view along cutting line I-I' is used to illustrate an electroluminescent display according to one embodiment of the present disclosure.

[0051] Reference Figures 2 to 3 A sub-pixel SP of a light-emitting display can be defined by a scan line SL, a data line DL, and a drive current line VDD. A sub-pixel SP of a light-emitting display may include a switching thin-film transistor ST, a driving thin-film transistor DT, a light-emitting diode OLE, and a storage capacitor Cst. The drive current line VDD can be provided with a high-level voltage for driving the light-emitting diode OLE.

[0052] A switching thin-film transistor (TFT) ST and a driving thin-film transistor (DT) can be formed on a substrate SUB. For example, the switching TFT ST can be located at the intersection of a scan line SL and a data line DL. The switching TFT ST may include a switching gate SG, a switching source SS, and a switching drain SD. The switching gate SG can be connected to the scan line SL. The switching source SS can be connected to the data line DL, and the switching drain SD can be connected to the driving TFT DT. By providing a data signal to the driving TFT DT, the switching TFT ST can select the pixel to be driven.

[0053] The driving thin-film transistor (DT) functions as a driver for the light-emitting diode (OLE) of the selected pixel via a switching thin-film transistor (ST). The driving DT includes a driving gate (DG), a driving source (DS), and a driving drain (DD). The driving gate (DG) can be connected to the switching drain (SD) of the switching DT. For example, the driving gate (DG) can be connected to the switching drain (SD) via a drain contact hole (DH) that penetrates the gate insulating layer (GI). The driving source (DS) can be connected to the driving current line (VDD), and the driving drain (DD) can be connected to the anode (ANO) of the OLE. A storage capacitor (Cst) can be disposed between the driving gate (DG) of the driving DT and the anode (ANO) of the OLE.

[0054] The driving thin-film transistor DT can be positioned between the driving current line VDD and the light-emitting diode OLE. The driving thin-film transistor DT can control the amount of current flowing from the driving current line VDD to the light-emitting diode OLE based on the voltage level of the driving gate DG of the switching drain SD connected to the switching thin-film transistor ST.

[0055] An OLE (Optical Light Emitting Diode) may include an anode (ANO), an emissive layer (EL), and a cathode (CAT). The OLE emits light according to the amount of current controlled by a driving thin-film transistor (DT). In other words, the OLE can be driven by the voltage difference between a low-level voltage and a high-level voltage controlled by the DT. The anode (ANO) of the OLE can be connected to the driving drain electrode (DD) of the DT, and the cathode (CAT) can be connected to a low-level voltage line (Vss) that provides a low-level potential voltage. That is, the OLE can be driven by a high-level voltage controlled by the DT and a low-level voltage provided from the low-level voltage line (Vss).

[0056] Reference Figure 3 and Figure 4 The cross-sectional structure of a display according to one embodiment of the present disclosure will be described. A low-resistivity line LL may be disposed on a substrate 110. The low-resistivity line LL may be disposed parallel to a data line DL between two adjacent pixels P1 and P2. In some cases, a low-resistivity line LL may be disposed in every two or three pixel columns. In one embodiment, a connection portion J may be defined at a portion of the low-resistivity line LL connected to the cathode CAT. The detailed structure of the connection portion J will be described later. The low-resistivity line LL may be connected to a low-power line VSS. In some cases, the low-resistivity line LL may be configured as a low-power line VSS. Furthermore, even if not shown in the figures, a light-shielding layer may be further included, formed on the same layer as the low-resistivity line LL but separate from it and disposed below semiconductor layers SA and DA. A buffer layer BUF may be deposited on the low-resistivity line LL.

[0057] Semiconductor layers SA and DA can be formed on the buffer layer BUF. The semiconductor layers include the switching semiconductor layer SA of the switching thin-film transistor ST and the driving semiconductor layer DA of the driving thin-film transistor DT. The gate insulating layer GI can be stacked on the semiconductor layers SA and DA, covering the entire surface of the substrate 110.

[0058] Gates SG and DG, overlapping with scan lines SL and semiconductor layers SA and DA, can be formed on gate insulating layer GI. The gates include the switching gate SG of switching thin-film transistor ST and the driving gate DG of driving thin-film transistor DT. Intermediate insulating layer ILD can be stacked on scan lines SL and gates SG and DG, covering the entire surface of substrate 110.

[0059] Sources SS and DS, drains SD and DD, low-resistance connection terminal LLP, data line DL, and drive current line VDD can be disposed on the intermediate insulating layer ILD. The sources include the switching source SS of the switching thin-film transistor ST and the driving source DS of the driving thin-film transistor DT. The drains include the switching drain SD of the switching thin-film transistor ST and the driving drain DD of the driving thin-film transistor DT. Each source SS and DS can be connected to one side (e.g., the first side) of the semiconductor layers SA and DA via contact holes penetrating the intermediate insulating layer ILD and the gate insulating layer GI, respectively. Each drain SD and DD can be connected to the other side (e.g., the second side) of the semiconductor layers SA and DA via contact holes penetrating the intermediate insulating layer ILD and the gate insulating layer GI, respectively.

[0060] The switching source SS can branch from the data line DL. The switching drain SD can be connected to the driving gate DG of the driving thin-film transistor DT. The driving source DS can branch from the driving current line VDD. The low-resistance connection terminal LLP can overlap with the low-resistance line LL at the connection portion J defined on the low-resistance line LL. The low-resistance connection terminal LLP can be connected to the low-resistance line LL via a contact hole. The low-resistance connection terminal LLP can be connected to the cathode CAT of the light-emitting diode OLE. The connection structure between the low-resistance connection terminal LLP and the cathode CAT is described below.

[0061] A passivation layer PAS can be deposited on the surface of a substrate 110 having thin-film transistors ST and DT and low-resistance interconnect terminals LLP. The passivation layer PAS can be made of an inorganic material such as silicon oxide or silicon nitride. A planarization layer PL can be deposited on the passivation layer PAS. The planarization layer PL can be a layer used to planarize the surface of the substrate 110 on which the thin-film transistors ST and DT are formed, and it may not be a uniform (or flat) surface. To ensure uniform height differences, the planarization layer PL can be formed of an organic material. Pixel contact holes PH can be formed at the passivation layer PAS and the planarization layer PL to expose a portion of the drive drain DD of the driving thin-film transistor DT.

[0062] The anode (ANO) is formed on the top surface of the planarization layer PL. The anode ANO can be connected to the drive drain (DD) of the driving thin-film transistor (DT) via the pixel contact hole (PH). The anode ANO can have different structures depending on the light-emitting type of the light-emitting diode (OLE). For a bottom-emitting type where light is emitted in the direction of the substrate 110, the anode ANO can be formed of a transparent conductive material. For example, for the bottom-emitting type, the anode ANO can be made of an oxide conductive material, such as indium tin oxide (or ITO) or indium zinc oxide (or IZO). For another example where light is emitted in the direction opposite to the substrate 110, the anode ANO can be made of a metallic material with excellent light transmittance. Here, the description can focus on the top-emitting type.

[0063] A dam BA can be formed on the anode ANO. The dam BA can cover the peripheral area of ​​the anode ANO and expose most of the central area of ​​the anode ANO. The central area of ​​the anode ANO exposed by the dam BA can be defined as the light-emitting area.

[0064] An emitting layer EL is deposited on the anode ANO. The emitting layer EL can be deposited on both the anode ANO and the embankment BA, covering the entire surface of the display area AA of the substrate 110. For example, the emitting layer EL may include two or more stacked emitting portions for emitting white light. More specifically, the emitting layer EL may include a first emitting layer providing a first color of light and a second emitting layer providing a second color of light, for emitting white light by combining the first color light and the second color light.

[0065] In another example, the emitting layer (EL) may include any one of a blue emitting layer, a green emitting layer, and a red emitting layer to provide a light color corresponding to the color assigned at the pixel. Furthermore, the light-emitting diode (OLE) may also include functional layers to enhance the luminous efficiency and / or lifetime of the EL.

[0066] The cathode CAT can be disposed on the light-emitting layer EL. Cathode CATs can be stacked on the light-emitting layer EL, with their surfaces in contact with each other. The cathode CAT can be formed as a sheet element over the entire area of ​​the substrate 110 to provide common connection to the entire light-emitting layer EL disposed at all pixels. In the case of a bottom-emitting type, the cathode CAT can comprise a metallic material with excellent light reflectivity. For example, the cathode CAT can comprise at least one of silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba). In the case of a top-emitting type, the cathode CAT can be made of a transparent conductive material. For example, the cathode CAT can be made of a metal oxide material including indium tin oxide or indium zinc oxide. The following description will focus on the top-emitting type.

[0067] Furthermore, the electroluminescent display according to this disclosure may include a cathode contact hole CON for connecting a cathode CAT to a low-resistance connection terminal LLP. The cathode contact hole CON may be provided at the connection portion J. Therefore, a plurality of cathode contact holes CON may be arranged at regular intervals along the low-resistance line LL. The cathode contact hole CON can be formed by penetrating the passivation layer PAS and the planarization layer PL covering the low-resistance connection terminal LLP. In the following, some embodiments based on various structures of the cathode contact hole will be described.

[0068] <First Implementation Method>

[0069] Reference Figure 4 and Figure 5The first embodiment of this disclosure will be described below. Figure 5 It is shown Figure 4 An enlarged cross-sectional view of the circular portion "N" of the structure of the connector in the electroluminescent display according to the first embodiment of the present disclosure.

[0070] Referring to the cross-sectional structure of the connection portion J, a low-resistance line LL is disposed on the substrate 110. The low-resistance line LL may have an opening region OH formed at the connection portion J. The opening region OH may be an opening hole for directly irradiating the low-resistance connection terminal LLP disposed thereon with a laser. The opening region OH may have various shapes and structures. Detailed descriptions will follow.

[0071] The buffer layer BUF can be formed on the low-resistance line LL. The gate insulating layer GI is deposited on the buffer layer BUF, and the intermediate insulating layer ILD is deposited on the gate insulating layer GI. The stacked layer consisting of the buffer layer BUF, the gate insulating layer GI, and the intermediate insulating layer ILD can be called an insulating layer.

[0072] Low-resistance connection terminals LLP are formed on the insulating layer, specifically on the intermediate insulating layer ILD. The low-resistance connection terminals LLP can be made of the same material as the source (SS) and drain (DS) and drain (SD) of the thin-film transistors ST and DT, and disposed on the same layer. The low-resistance connection terminals LLP can be connected to the low-resistance line LL via contact holes formed in the insulating layer comprising the buffer layer BUF, the gate insulating layer GI, and the intermediate insulating layer ILD.

[0073] The low-resistance connection terminal LLP can have a polygonal or circular shape corresponding to the size of the connection portion J. In one embodiment, the low-resistance connection terminal LLP can have a region size larger than the opening region OH, and a shape for completely covering (e.g., overlapping) the opening region OH. Therefore, in a cross-sectional view, one end (e.g., the first end) of the low-resistance connection terminal LLP can have a bridge shape that connects the low-resistance connection terminal LLP to one side of the low-resistance line LL, and the other end (e.g., the second end) of the low-resistance connection terminal LLP can be connected to the other side of the low-resistance line LL. The middle portion of the low-resistance connection terminal LLP between the ends can be exposed when viewed from the direction in which the opening region OH of the low-resistance line LL is provided on the substrate 110.

[0074] A passivation layer PAS and a planarization layer PL are stacked sequentially on a low-resistance connection terminal LLP. Specifically, the passivation layer PAS and the planarization layer PL may have a cathode contact hole CON for exposing the middle portion of the low-resistance connection terminal LLP.

[0075] An anode (ANO) is formed on the planarization layer PL, and a dam (BA) is formed on the anode (ANO). A light-emitting layer (EL) is deposited on the anode (ANO) and the dam (BA), and a cathode (CAT) is deposited on the light-emitting layer (EL). Therefore, at the cathode contact hole (CON), the light-emitting layer (EL) and the cathode (CAT) are sequentially deposited on the exposed portion of the low-resistance connection terminal (LLP).

[0076] The connecting portion J can be used to physically and electrically connect the low-resistance connection terminal LLP and the cathode CAT. At the cathode contact hole CON, the light-emitting layer EL is inserted between the low-resistance connection terminal LLP and the cathode CAT, so the low-resistance connection terminal LLP and the cathode CAT are not connected to each other. To connect the low-resistance connection terminal LLP and the cathode CAT, a laser can be irradiated from the outside of the substrate 110 through the opening region OH formed at the low-resistance line LL towards the low-resistance connection terminal LLP. As a result, the low-resistance connection terminal LLP may be melted by the thermal energy of the laser, diffused upwards through the light-emitting layer EL, and then the low-resistance connection terminal LLP connects to the cathode CAT.

[0077] When irradiating the low-resistance connector (LLP) and cathode (CAT) with a laser, the laser can be irradiated from outside the cathode CAT. In the case of top-emitting type, since the cathode CAT is made of a transparent conductive material, the heat energy of the laser can be transferred to the LLP through the cathode CAT. Before reaching the LLP, the heat energy can first be transferred to the emissive layer (EL). In this case, a large amount of heat energy may be transferred to the EL before the LLP melts, which may adversely affect the EL of adjacent pixels.

[0078] Therefore, in one embodiment of the top-emitting electroluminescent display according to the present disclosure, heat energy is first transferred to the low-resistivity connection terminal LLP by irradiating a laser from the direction of the substrate 110. Furthermore, the top-emitting electroluminescent display may include a repair element for connecting defective pixels to normal pixels. In this case, in one embodiment, the laser is irradiated from the direction of the substrate 110 during the laser repair process. Therefore, in the top-emitting electroluminescent display according to the present disclosure, the laser process for connecting the low-resistivity connection terminal LLP and the cathode CAT can be performed simultaneously with the repair process.

[0079] The electroluminescent display according to the first embodiment of this disclosure can have a top-emitting type, wherein the cathode CAT is formed of a transparent conductive material. The top-emitting type allows for maximizing the size of the light-emitting diodes in the pixel region, and therefore has the advantage of providing high brightness even for small-sized pixels. Furthermore, since the thin-film resistance of the cathode CAT can be reduced by the low-resistance line LL, this disclosure provides excellent display quality even when realizing a large-area electroluminescent display. In particular, since the laser directly irradiates the low-resistance connection terminal LLP via the opening region OH formed in the low-resistance line LL, the low-resistance connection terminal LLP and the cathode CAT can be connected using a laser with a relatively low energy wavelength band of 266 nm. Figure 5 As shown, as a result of applying this layer, a portion of the light-emitting layer EL is disposed in the cathode contact hole CON, such that this portion of the light-emitting layer EL lies between the first portion of the low-resistance connection terminal LLP and a portion of the cathode CAT disposed in the cathode contact hole CON. Furthermore, the second portion of the low-resistance connection terminal LLP penetrates the portion of the light-emitting layer EL and connects to the portion of the cathode CAT disposed in the cathode contact hole CON.

[0080] <Second Implementation Method>

[0081] In the first embodiment, by irradiating a laser at the low-resistance connection terminal LLP exposed by the cathode contact hole CON provided at all connection portions J in the electroluminescent display, the cathode CAT can be connected to the low-resistance line LL. In the second embodiment, referring to... Figure 6 The structure of the cathode contact hole CON can be configured to connect the cathode CAT to the low-resistance connection terminal LLP without irradiating the laser. Figure 6 This is an enlarged cross-sectional view showing the structure of the connecting portion in an electroluminescent display according to the second embodiment of this disclosure. Here, since the cross-sectional structure of the other parts besides the connecting portion J is similar to... Figure 4 The cross-sectional structures are the same, so in Figure 6 The entire cross-sectional view is not shown.

[0082] Referring to the cross-sectional view of the connection portion J, a low-resistance line LL is disposed on the substrate 110. The low-resistance line LL has an opening region OH formed at the connection portion J. The opening region OH can be an opening hole for directly irradiating a laser into the low-resistance connection terminal LLP disposed on the low-resistance line LL.

[0083] An insulating layer is deposited on the low-resistance line LL. The insulating layer may include a buffer layer BUF, a gate insulating layer GI, and an intermediate insulating layer ILD, which are sequentially stacked on the substrate 110. A low-resistance connection terminal LLP is disposed on the insulating layer. The low-resistance connection terminal LLP can be connected to the low-resistance line LL via a contact hole formed in the insulating layer.

[0084] In one embodiment, the low-resistance connection terminal LLP may have a region size larger than the opening region OH, and a shape for completely covering (e.g., overlapping) the opening region OH. Therefore, in a cross-sectional view, one end (e.g., a first end) of the low-resistance connection terminal LLP may have a bridge shape connecting the low-resistance connection terminal LLP to one side of the low-resistance line LL, and the other end (e.g., a second end) of the low-resistance connection terminal LLP may connect to the other side of the low-resistance line LL. The middle portion of the low-resistance connection terminal LLP between its ends may be exposed when viewed from the direction in which the opening region OH of the low-resistance line LL is positioned on the substrate 110.

[0085] A passivation layer PAS and a planarization layer PL are stacked sequentially on a low-resistance connection terminal LLP. Specifically, the passivation layer PAS and the planarization layer PL may have a cathode contact hole CON for exposing the middle portion of the low-resistance connection terminal LLP.

[0086] Specifically, the cathode contact hole CON can have a structure in which the passivation layer PAS can have an undercut region UC formed by over-etching the passivation layer PAS relative to the planarization layer PL. For example, the cathode contact hole CON can have a second width W2 formed at the passivation layer PAS and a first width W1 formed at the planarization layer PL, wherein the first width W1 is narrower than the second width W2.

[0087] At the connection portion J, the light-emitting layer EL is deposited on the low-resistance connection terminal LLP exposed by the cathode contact hole CON. However, due to the structure of the undercut region UC, the light-emitting layer EL can be deposited on some portions of the exposed portion of the low-resistance connection terminal LLP, which is the second width W2 formed at the planarization layer PL, but it can be left undeposited on the undercut region UC.

[0088] However, since the cathode CAT is made of inorganic materials, it can be deposited on the light-emitting layer EL and the undercut region UC. That is, the cathode CAT can have a structure in which the cathode CAT is directly connected to the low-resistance connection terminal LLP at the cathode contact hole CON formed at the connection portion J in the undercut region UC.

[0089] In the second embodiment, due to the undercut region UC formed at the cathode contact hole CON, the cathode CAT can be physically and electrically connected to the low-resistance connection terminal LLP without laser processing. However, by utilizing the ultra-high resolution density structure, the pixel size can be made smaller, and the spacing between two adjacent pixels can be made narrower, thereby allowing the size of the cathode contact hole CON to be made smaller. In this case, the undercut region UC can also have a smaller size. Therefore, as... Figure 7A As shown, an luminescent layer EL can be deposited on the undercut region UC. Figure 7A This is an enlarged cross-sectional view showing a contact failure occurring at the connection portion of an electroluminescent display according to the second embodiment of the present disclosure.

[0090] As a result, the cathode CAT may not need to be connected to the low-resistance connection terminal LLP. Even if the cathode CAT is connected to the low-resistance connection terminal LLP, the connection area may be very small, thus potential contact failures may occur. To prevent contact failures, such as... Figure 7B As shown, further laser processing can be performed to connect the cathode CAT to the low-resistance connection terminal LLP where contact failure has occurred. Figure 7B This is an enlarged cross-sectional view after a contact fault at the connection portion of the electroluminescent display according to the second embodiment of this disclosure has been resolved.

[0091] Specifically, in one embodiment of the top-emitting electroluminescent display according to this disclosure, in order to connect the low-resistance connection terminal LLP and the cathode CAT, heat energy is first transferred to the low-resistance connection terminal LLP by irradiating a laser from the direction of the substrate 110. Additionally, in one embodiment where the repair element further includes a function in the top-emitting electroluminescent display for bypassing (or connecting) a defective pixel to a normal pixel, a laser is irradiated from the direction of the substrate 110 during the repair process. Therefore, in one embodiment of the top-emitting electroluminescent display according to this disclosure, the laser process for connecting the low-resistance connection terminal LLP to the cathode CAT can be performed simultaneously with the repair process.

[0092] In the second embodiment, which differs from the first embodiment, laser irradiation is not performed at all connection points J, but rather selectively at the connection points J where connection failures occur. Laser irradiation is intended to apply heat energy to specific areas, and therefore, the concentration of high heat energy can lead to undesirable defects. Therefore, it is desirable to minimize the use of lasers in various processes.

[0093] The electroluminescent display according to the second embodiment of this disclosure can have the characteristics of a top-emitting type, wherein the cathode CAT is formed of a transparent conductive material. The top-emitting type allows for maximizing the size of the light-emitting diodes in the pixel region, and therefore has the advantage of providing high brightness even for small-sized pixels. Specifically, since the laser directly irradiates the low-resistance connection terminals from the direction of the substrate, connection faults can be recovered by using a low-energy laser. Contact defects at the connection points can also be detected and repaired during the repair process performed in the video quality inspection after the electroluminescent display is manufactured, thereby shortening the overall manufacturing time and reducing damage caused by laser irradiation.

[0094] <Third Implementation Method>

[0095] In the following text, see references Figure 8 , Figure 9A and Figure 9B The following describes an electroluminescent display according to a third embodiment of the present disclosure. Figure 8 This is an enlarged cross-sectional view showing the structure of the connection portion in an electroluminescent display according to a third embodiment of the present disclosure. Figure 9A This is an enlarged cross-sectional view showing a contact failure occurring at the connection portion of an electroluminescent display according to the third embodiment of this disclosure. Figure 9B This is an enlarged cross-sectional view after a contact fault has been repaired at the connection portion of the electroluminescent display according to the third embodiment of this disclosure. Here, due to the cross-sectional structure of the parts other than the connection portion J, and... Figure 8 The cross-sectional structures are the same, so in Figure 9A and Figure 9B The entire cross-sectional view is not shown.

[0096] Referring to the cross-sectional view of the connection portion J, a low-resistance line LL is disposed on the substrate 110. The low-resistance line LL has an opening region OH formed at the connection portion J. The opening region OH can be an opening hole for directly irradiating a laser into the low-resistance connection terminal LLP disposed on the low-resistance line LL.

[0097] An insulating layer is deposited on the low-resistance line LL. The insulating layer may include a buffer layer BUF, a gate insulating layer GI, and an intermediate insulating layer ILD, which are sequentially stacked on the substrate 110. A low-resistance connection terminal LLP is disposed on the insulating layer. The low-resistance connection terminal LLP can be connected to the low-resistance line LL via a contact hole formed in the insulating layer.

[0098] In one embodiment, the low-resistance connection terminal LLP may have a region size larger than the opening region OH and a shape for completely covering the opening region OH. Therefore, in a cross-sectional view, one end of the low-resistance connection terminal LLP (e.g., a first end) may have a bridge shape connecting the low-resistance connection terminal LLP to one side of the low-resistance line LL, and the other end of the low-resistance connection terminal LLP (e.g., a second end) may connect to the other side of the low-resistance line LL. The middle portion of the low-resistance connection terminal LLP between its ends may be exposed when viewed from the direction in which the opening region OH of the low-resistance line LL is positioned on the substrate 110.

[0099] A passivation layer PAS and a planarization layer PL are stacked sequentially on a low-resistance connection terminal LLP. In particular, the passivation layer PAS and the planarization layer PL may have a cathode contact hole CON that exposes the low-resistance connection terminal LLP.

[0100] Specifically, the cathode contact hole CON can have a structure for exposing the periphery of the low-resistance connection terminal LLP. The central portion of the low-resistance connection terminal LLP can be covered by a passivation layer PAS and a planarization layer PL stacked thereon. Furthermore, the passivation layer PAS covering the central portion can have a first width L1, and the planarization layer PL can have a second width L2. In one embodiment, the first width L1 can be narrower than the second width L2. This shape can be obtained by over-etching the passivation layer PAS relative to the planarization layer PL. As a result, an undercut region UC can be formed under the planarization layer PL.

[0101] Subsequently, when depositing the light-emitting layer EL, the light-emitting layer EL can be deposited on the circumference of the low-resistivity connection terminal LLP exposed from the planarization layer PL. On the other hand, the light-emitting layer EL may not be deposited at the undercut region UC, so some portions of the low-resistivity connection terminal LLP can be exposed from the light-emitting layer EL.

[0102] In this configuration, when depositing the cathode CAT, the cathode CAT can be stacked on the upper surface of the light-emitting layer EL and the undercut region UC. As a result, at the undercut region UC, the cathode CAT can be physically and electrically connected to the low-resistance connection terminal LLP. The cathode CAT, made of a transparent conductive material with a higher sheet resistance than metallic materials, can be electrically connected to the low-resistance line LL via the low-resistance connection terminal LLP. Therefore, the sheet resistance of the cathode CAT can be reduced.

[0103] In the third embodiment, the undercut region UC can be formed by using a stacked structure of a passivation layer PAS and a planarization layer PL at the middle portion of the low-resistance connection terminal LLP at the cathode contact hole CON. This structure can be more complex than the structure of the undercut region UC according to the second embodiment. However, for cases where the cathode contact hole CON is formed in a narrow space with an ultra-high resolution structure, the exposed area of ​​the low-resistance connection terminal LLP in the undercut region UC can be maximized.

[0104] Furthermore, due to the undercut region UC formed at the cathode contact hole CON, the cathode CAT can be connected to the low-resistance connection terminal LLP without laser processing. A third embodiment can provide a structure in which connectivity can be ensured even when the size of the cathode contact hole CON decreases with the reduction of pixel size and the distance between pixels decreases with the realization of an ultra-high resolution electroluminescent display. Even when the low-resistance connection terminal LLP and the cathode CAT are connected in the undercut region UC, issues such as… Figure 9A The contact failure is shown. Figure 9A This is an enlarged cross-sectional view showing a case where contact failure occurs at the connection portion according to the third embodiment.

[0105] As a result, the cathode (CAT) and the low-resistance connection terminal (LLP) may not make contact with each other, or even if they do, contact defects may occur with only a small contact area. To prevent contact failure, such as... Figure 9B As shown, further laser processing can be performed to connect the cathode CAT to the low-resistance connection terminal LLP where contact failure has occurred. Figure 9B This is an enlarged cross-sectional view after the contact fault at the connection portion of the electroluminescent display according to the third embodiment has been repaired.

[0106] Specifically, in the top-emitting electroluminescent display according to the third embodiment, in one embodiment for connecting the low-resistance connection terminal LLP and the cathode CAT, heat energy is first transferred to the low-resistance connection terminal LLP by irradiating a laser from the direction of the substrate 110. Furthermore, in a case where the repair element further includes a function in the top-emitting electroluminescent display for bypassing (or connecting) a defective pixel to a normal pixel, in one embodiment, a laser is irradiated from the direction of the substrate 110 during the repair process. Therefore, in the top-emitting electroluminescent display according to this disclosure, in one embodiment, the laser process for connecting the low-resistance connection terminal LLP to the cathode CAT can be performed simultaneously with the repair process.

[0107] In the third embodiment, which differs from the first embodiment, laser irradiation is not performed at all connection points J, but rather selectively at the connection points J where connection failures occur. Laser irradiation is intended to apply heat energy to specific areas, and therefore, the concentration of high heat energy can lead to undesirable defects. Therefore, it is desirable to minimize the use of lasers in various processes.

[0108] The electroluminescent display according to the third embodiment of this disclosure can have the characteristics of a top-emitting type, wherein the cathode CAT is formed of a transparent conductive material. The top-emitting type allows for maximizing the size of the light-emitting diodes in the pixel region, and therefore has the advantage of providing high brightness even for small-sized pixels. Specifically, since the laser directly irradiates the low-resistance connection terminals from the direction of the substrate, connection faults can be recovered by using a low-energy laser. Contact defects at the connection points can also be detected and repaired during the repair process performed during video quality inspection after the complete manufacturing of the electroluminescent display, thereby reducing the overall manufacturing time and minimizing damage caused by laser irradiation.

[0109] <Fourth Implementation Method>

[0110] In the following text, see references Figure 10 , Figure 11A and Figure 11B The following describes an electroluminescent display according to a fourth embodiment of the present disclosure. Figure 10This is an enlarged cross-sectional view showing the structure of the connection portion in an electroluminescent display according to the fourth embodiment of the present disclosure. Figure 11A This is an enlarged cross-sectional view showing a contact failure occurring at the connection portion of an electroluminescent display according to the fourth embodiment of the present disclosure. Figure 11B This is an enlarged cross-sectional view after a contact fault has been repaired at the connection portion of the electroluminescent display according to the fourth embodiment of this disclosure. Here, due to the different cross-sectional structures of the portions other than connection portion J... Figure 10 The cross-sectional structures are the same, so in Figure 11A and Figure 11B The entire cross-sectional view is not shown.

[0111] The structure of the connection portion in the electroluminescent display according to the fourth embodiment can be very similar to that of the third embodiment. The difference may be that the auxiliary electrode AU may be further included between the passivation layer PAS and the planarization layer PL around the low-resistance connection terminal LLP.

[0112] Referring to the cross-sectional view of the connection portion J, a low-resistance line LL is disposed on the substrate 110. The low-resistance line LL has an opening region OH formed at the connection portion J. An insulating layer is deposited on the low-resistance line LL. The insulating layer may include a buffer layer BUF, a gate insulating layer GI, and an intermediate insulating layer ILD sequentially stacked on the substrate 110.

[0113] A low-resistance connection terminal LLP is disposed on an insulating layer. In one embodiment, the low-resistance connection terminal LLP may have a region size larger than the opening region OH and a shape for completely covering the opening region OH. Therefore, in a cross-sectional view, one end (e.g., a first end) of the low-resistance connection terminal LLP may have a bridge shape that connects the low-resistance connection terminal LLP to one side of the low-resistance line LL, and the other end (e.g., a second end) of the low-resistance connection terminal LLP may be connected to the other side of the low-resistance line LL. When viewed in the direction of the substrate 110, the middle portion of the low-resistance connection terminal LLP may be exposed through the opening region OH of the low-resistance line LL.

[0114] A passivation layer PAS and a planarization layer PL are stacked sequentially on a low-resistance connection terminal LLP. Specifically, the passivation layer PAS and the planarization layer PL may have a cathode contact hole CON exposing the low-resistance connection terminal LLP. The cathode contact hole CON may have a structure for exposing the periphery of the low-resistance connection terminal LLP.

[0115] For example, the middle portion of the low-resistance connection terminal LLP can be covered by a passivation layer PAS and a planarization layer PL stacked thereon. Furthermore, the passivation layer PAS covering the middle portion can have a first width L1, and the planarization layer PL can have a second width L2. In one embodiment, the first width L1 can be narrower than the second width L2. This shape can be obtained by over-etching the passivation layer PAS relative to the planarization layer PL. As a result, an undercut region UC can be formed under the planarization layer PL.

[0116] Furthermore, the auxiliary electrode AU can be formed between the passivation layer PAS and the planarization layer PL, having a shape surrounding the periphery of the low-resistance connection terminal LLP. In one embodiment, the auxiliary electrode AU can have a structure in which the planarization layer PL is wider than the passivation layer PAS so as to be exposed by the planarization layer PL.

[0117] Subsequently, when depositing the light-emitting layer EL, the light-emitting layer EL can be deposited on the circumference of the low-resistivity connection terminal LLP exposed from the planarization layer PL. On the other hand, the light-emitting layer EL may not be deposited at the undercut region UC, so some portions of the low-resistivity connection terminal LLP can be exposed from the light-emitting layer EL.

[0118] In this configuration, when depositing the cathode CAT, the cathode CAT can be stacked on the upper surface of the light-emitting layer EL and the undercut region UC. As a result, at the undercut region UC, the cathode CAT can be physically and electrically connected to the low-resistance connection terminal LLP. The cathode CAT, made of a transparent conductive material with a higher sheet resistance than metallic materials, can be electrically connected to the low-resistance line LL via the low-resistance connection terminal LLP. Therefore, the sheet resistance of the cathode CAT can be reduced.

[0119] According to the fourth embodiment, due to the undercut region UC formed at the cathode contact hole CON, the cathode CAT can be connected to the low-resistance connection terminal LLP without laser processing. In the fourth embodiment, even when the low-resistance connection terminal LLP and the cathode CAT are connected within the undercut region UC, the following may occur: Figure 11A The contact failure is shown.

[0120] As a result, the cathode (CAT) and the low-resistance connection terminal (LLP) may not make contact with each other, or even if they do, there may be contact defects with a very small contact area. To prevent contact failure, such as... Figure 11B As shown, further laser processing can be performed to connect the cathode CAT to the low-resistance connection terminal LLP where contact failure has occurred.

[0121] In the fourth embodiment, when the thermal energy of the laser directly irradiating the low-resistance connection terminal LLP through the opening region OH melts the low-resistance connection terminal LLP, the low-resistance connection terminal LLP can be connected to the cathode CAT through the light-emitting layer EL. Specifically, the molten low-resistance connection terminal LLP can be connected to the cathode CAT together with the auxiliary electrode AU disposed around the low-resistance connection terminal LLP. Therefore, the connection between the molten low-resistance connection terminal LLP and the cathode CAT can be achieved more reliably and firmly.

[0122] In the top-emitting electroluminescent display according to the fourth embodiment, in one embodiment for connecting the low-resistance connection terminal LLP, the auxiliary electrode AU, and the cathode CAT, heat energy is first transferred to the low-resistance connection terminal LLP by irradiating a laser from the direction of the substrate 110. Furthermore, in a case where the repair element further includes a function in the top-emitting electroluminescent display for bypassing defective pixels to normal pixels, in one embodiment, a laser is irradiated from the direction of the substrate 110 during the repair process. Therefore, in the top-emitting electroluminescent display according to the fourth embodiment, in one embodiment, the laser process for connecting the low-resistance connection terminal LLP, the auxiliary electrode AU, and the cathode CAT can be performed simultaneously with the repair process.

[0123] In the fourth embodiment, which differs from the first embodiment, laser irradiation is not performed at all connection points J, but rather selectively at the connection points J where connection failures occur. Irradiating with a laser applies heat energy to a specific area, and therefore, undesirable defects may occur due to the concentration of high heat energy. Therefore, it is desirable to minimize the use of lasers in various processes.

[0124] The electroluminescent display according to the fourth embodiment of this disclosure can have the characteristics of a top-emitting type, wherein the cathode CAT is formed of a transparent conductive material. The top-emitting type allows for maximizing the size of the light-emitting diodes in the pixel region, and therefore has the advantage of providing high brightness even for small-sized pixels. Specifically, since the laser directly irradiates the low-resistance connection terminals from the direction of the substrate, connection faults can be recovered by using a low-energy laser. Contact defects at the connection points can also be detected and repaired during the repair process performed during video quality inspection after the electroluminescent display is manufactured, thereby shortening the overall manufacturing time and reducing damage caused by laser irradiation. By further providing an auxiliary electrode AU, the fusion (or melting) connection between the low-resistance connection terminals LLP and the cathode CAT can be achieved more reliably through a laser process.

[0125] <Fifth Implementation Method>

[0126] In the following text, refer to Figure 12 The following describes an electroluminescent display according to a fifth embodiment of the present disclosure. Figure 12 This is a plan view showing the structure of an electroluminescent display according to the fifth embodiment of the present disclosure.

[0127] Figure 12 The electroluminescent display shown illustrates a case of very high pixel density. For example, in a large-area top-emitting electroluminescent display achieving an ultra-high resolution of 200 DPI (dots per inch) or greater, all sub-pixels SPR, SPG, SPB, and SPW set in the display area AA can be uniformly spaced. In this case, compared to… Figure 1 Unlike other structures, the spacing between pixels P can be set to be equal to the spacing between subpixels SP, rather than wider. With this structure, because the spacing between subpixels SP is very narrow, it may be difficult to form a cathode contact hole CON on one side of a subpixel SP.

[0128] For ultra-high resolution structures, such as Figure 12 As shown, the cathode contact hole CON can be set at the intersection region K, where four adjacent pixels P meet. For example, the cathode contact hole CON can be set at the intersection region K of the white sub-pixel SPW of the first pixel P1, the red sub-pixel SPR of the second pixel P2, the white sub-pixel SPW of the third pixel P3, and the red sub-pixel SPR of the fourth pixel P4. To set the cathode contact hole CON, the intersection region K with a square shape can be set by partially removing the intersection portion of every four sub-pixels.

[0129] Then, by patterning the planarization layer PL and the passivation layer PAS, a cathode contact hole CON exposing the low-resistance connection terminal LLP under the planarization layer PL and the passivation layer PAS can be formed at the intersection region K with a square shape. Here, the cathode contact hole CON can have any of the structures according to the first to fourth embodiments.

[0130] The features, structures, effects, etc., described in the above exemplary embodiments of this disclosure are included in at least one exemplary embodiment of this disclosure, and are not necessarily limited to one exemplary embodiment. Furthermore, the features, structures, effects, etc., explained in at least one example embodiment can be implemented by those skilled in the art in combination or modification with respect to other example embodiments. Therefore, such combinations and variations should be interpreted as being included within the scope of this disclosure.

[0131] It will be apparent to those skilled in the art that various substitutions, modifications, and variations are possible within the scope of this disclosure without departing from its spirit and scope. Therefore, embodiments of this disclosure are intended to cover various substitutions, modifications, and variations of this disclosure, provided they fall within the scope of the appended claims and their equivalents. These and other changes can be made to the embodiments based on the foregoing detailed description. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific exemplary embodiments disclosed in the specification and claims, but should be construed as encompassing all possible embodiments and the full scope of equivalents granted by such claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An electroluminescent display, the electroluminescent display comprising: substrate; A pixel, located on the substrate, includes an anode, a light-emitting layer, and a cathode; A low-resistivity line, the low-resistivity line being located on one side of the pixel, the low-resistivity line having a connecting portion; An insulating layer located on a low-resistance line; A low-resistance connection terminal is located on the insulating layer and is connected to the connection portion of the low-resistance wire; A passivation layer is located on the low-resistance connection terminal; A planarization layer, wherein the planarization layer is located on the passivation layer; A cathode contact hole that exposes a portion of the low-resistance connection terminal. The low-resistance wire includes an opening region between a first side and a second side of the low-resistance wire, and this opening region overlaps with the middle portion of the low-resistance connection terminal at the connection portion. The low-resistance connection terminal is connected to the first side and the second side of the low-resistance line. Wherein, the portion of the cathode exposed through the cathode contact hole is connected to the low-resistance connection terminal, and The low-resistance connection terminal connects the low-resistance line to the cathode at the opening region.

2. The electroluminescent display according to claim 1, wherein, The cathode contact hole penetrates the passivation layer and the planarization layer to expose a portion of the low-resistance connection terminal. The low-resistance connection terminal penetrates the light-emitting layer and connects to the cathode at the cathode contact hole.

3. The electroluminescent display according to claim 1, wherein, The cathode contact hole includes: A first contact hole is located in the planarization layer and has a first width; A second contact hole is located within the passivation layer, and the second contact hole has a second width greater than the first width. The light-emitting layer is deposited on the middle portion of the low-resistance connection terminal exposed through the second contact hole having the second width, and The cathode is disposed in the first contact hole having the first width and is connected to the periphery of the low-resistance connection terminal exposed through the second contact hole having the second width.

4. The electroluminescent display according to claim 1, wherein, The cathode contact hole includes a first pattern and a second pattern that overlap with the middle portion of the low-resistance connection terminal, and The first width of the first pattern is narrower than the second width of the second pattern, so as to form an undercut region below the planarization layer.

5. The electroluminescent display according to claim 4, wherein, The connecting portion includes a first connecting portion and a second connecting portion separated from the first connecting portion. Wherein, at the first connection portion, the cathode is connected to the low-resistance connection terminal exposed at the undercut region.

6. The electroluminescent display according to claim 5, wherein, At the second connection portion, the light-emitting layer is located on the low-resistance connection terminal exposed from the cathode contact hole, and the cathode is located on the light-emitting layer such that the cathode is farther from the low-resistance connection terminal than the light-emitting layer, and the low-resistance connection terminal is connected to the cathode at the second connection portion by melting to penetrate the light-emitting layer.

7. The electroluminescent display according to claim 6, further comprising: An auxiliary electrode is located between the passivation layer and the planarization layer, and surrounds the low-resistance connection terminal. In the second connection portion, the low-resistance connection terminal is connected to the auxiliary electrode and the cathode by melting to penetrate the light-emitting layer.

8. The electroluminescent display according to claim 1, wherein, The opening region has a width narrower than the width of the low-resistance line, and the opening region includes a polygonal shape, a circular shape, or an elliptical shape.

9. The electroluminescent display according to claim 1, wherein, The width of the low-resistance connection terminal is wider than the width of the low-resistance line, and the low-resistance connection terminal completely overlaps with the opening area.

10. The electroluminescent display according to claim 1, further comprising: A buffer layer that covers the low-resistivity line on the substrate; as well as A thin-film transistor, wherein the thin-film transistor is disposed between the buffer layer and the passivation layer, The low-resistance connection terminal penetrates the insulating layer and is connected to the low-resistance line.

11. The electroluminescent display according to claim 10, wherein, The thin-film transistor includes: A semiconductor layer, wherein the semiconductor layer is located on the buffer layer; A gate insulating layer, wherein the gate insulating layer is located on the semiconductor layer; A gate, wherein the gate overlaps the semiconductor layer on a gate insulating layer; An intermediate insulating layer is located on the gate; Source electrode, the source electrode being connected to a first side of the semiconductor layer on the intermediate insulating layer; and The drain electrode is connected to the second side of the semiconductor layer on the intermediate insulating layer. In this configuration, a portion of the low-resistance connection terminal is on the same layer as the source and the drain, and the low-resistance connection terminal penetrates the buffer layer, the gate insulating layer, and the intermediate insulating layer to connect to the low-resistance line.

12. The electroluminescent display according to claim 1, wherein, The connection portion includes a plurality of the connection portions arranged at predetermined intervals along the low-resistance line.

13. The electroluminescent display according to claim 1, wherein, The pixels include multiple pixels arranged in a matrix with multiple rows and multiple columns. Wherein, at least one pixel among the plurality of pixels includes: Red sub-pixel; Green sub-pixel; Blue sub-pixel; and White sub-pixel.

14. The electroluminescent display according to claim 13, wherein, The connecting portion is disposed at the intersection of four pixels among the plurality of pixels, and the four pixels are adjacent to each other.

15. The electroluminescent display according to claim 13, wherein, The low-resistance lines are set one after another for every predetermined number of columns in a plurality of columns.

16. An electroluminescent display, the electroluminescent display comprising: substrate; Low-resistance line, the low-resistance line being located on the substrate; A low-resistance connection terminal, wherein the low-resistance connection terminal is connected to the low-resistance line; A pixel, wherein the pixel includes an anode, a light-emitting layer, and a cathode, and the anode does not overlap with the low-resistivity line; A passivation layer is located on the low-resistance connection terminal; A planarization layer, wherein the planarization layer is located on the passivation layer; as well as A contact hole that passes through a portion of the passivation layer and a portion of the planarization layer that overlaps with the low-resistance connection terminal. A portion of the light-emitting layer is disposed in the contact hole, such that the portion of the light-emitting layer is located between the first portion of the low-resistance connection terminal and the portion of the cathode disposed in the contact hole, and the second portion of the low-resistance connection terminal penetrates the portion of the light-emitting layer and connects to the portion of the cathode disposed in the contact hole. The low-resistance line includes an opening region between a first side and a second side of the low-resistance line, and the laser is applied to the opening region.

17. The electroluminescent display according to claim 16, wherein, The second portion of the low-resistance connection terminal, which is connected to the cathode and disposed in the contact hole, is formed by laser.

18. The electroluminescent display according to claim 16, further comprising: An auxiliary electrode is located between the passivation layer and the planarization layer, and surrounds the low-resistance connection terminal. The second portion of the low-resistance connection terminal is connected to the portion of the auxiliary electrode and the cathode disposed in the contact hole.

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