Tunnel-free floorplan in integrated circuits

Abstract

Various embodiments can include integrated circuits (ICs) and methods for designing integrated circuits (200), such as system on a chip (SOC). Embodiments include methods for planning and producing ICs without communication channels (also referred to as channel-less ICs). Embodiments can include overlay hard macros (210) that support routing and communication designs without requiring dedicated communication channels between functional hard macros, such as cores of a SOC. Various embodiments can include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro, and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, there can be no communication channels between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Patent Application No. 17 / 079,727, filed October 26, 2020, entitled “Channel Less Floor-Planning In Integrated Circuits,” the entirety of which is incorporated by reference herein. BACKGROUND

[0003] New integrated circuits (ICs) are being developed for ever-changing use cases, such as mobile devices, Internet of Things (IoT), wearable devices, and other small form factor devices. As these ever-evolving use cases and ever-growing feature sets associated with ICs, design complexity continues to increase. SUMMARY

[0004] Various aspects include integrated circuits (ICs) and methods for designing integrated circuits (ICs), such as system on a chip (SOCs). Various aspects include ICs without communication or interconnect channels and methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Various aspects include overlay hard macros that support routing and communication designs without requiring dedicated communication channels between functional hard macros (e.g., cores of an SOC).

[0005] Various aspects can include an integrated circuit including a first functional hard macro, a second functional hard macro, a third functional hard macro, one or more interconnect hard macros located within the third functional hard macro, and wires connecting the first functional hard macro, the second functional hard macro, and the one or more interconnect hard macros. In some aspects, the first functional hard macro can be electrically coupled to the second functional hard macro through the one or more interconnect hard macros and the wires. In some aspects, a side of the first functional hard macro and a side of the second functional hard macro can not abut. In some aspects, the first functional hard macro and the second functional hard macro can abut different sides of the third functional hard macro. In some aspects, there can be no communication channels between the first functional hard macro, the second functional hard macro, and the third functional hard macro. In some aspects, the third functional hard macro can completely surround each of the one or more interconnect hard macros. In some aspects, the one or more interconnect hard macros can include a communication pipeline hard macro. In some aspects, the integrated circuit can be an SOC, and the first functional hard macro, the second functional hard macro, and the third functional hard macro can be a first core, a second core, and a third core, respectively.

[0006] Various aspects can include a method of designing an integrated circuit, the method including determining a first functional hard macro and a second functional hard macro of the integrated circuit, the first functional hard macro and the second functional hard macro requiring a physical communication path from one another, wherein the first functional hard macro and the second functional hard macro are separated from one another by at least a portion of a third functional hard macro of the integrated circuit; determining locations for one or more interconnect hard macros and wires connecting the first functional hard macro, the second functional hard macro, and the one or more interconnect hard macros within the third functional hard macro; generating a wrapper indicating the determined locations of the one or more interconnect hard macros and the wires; and configuring the third functional hard macro according to the wrapper such that the third functional hard macro includes empty border regions at the determined locations of the one or more interconnect hard macros and the wires. Various aspects can also include overlaying the one or more interconnect hard macros and the wires into the empty border regions in the third functional hard macro. In some aspects, the wires can extend outside of the empty border regions in the third functional hard macro. In some aspects, the first functional hard macro, the second functional hard macro, and the third functional hard macro can be configured such that there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro. In some aspects, the one or more interconnect hard macros can be a communication pipeline hard macro. In some aspects, the integrated circuit can be a SOC, and the first functional hard macro, the second functional hard macro, and the third functional hard macro can be a first core, a second core, and a third core, respectively.

[0007] Other aspects include a computing device having a processor configured to perform the operations of any of the methods described above. Other aspects include a computing device having means for performing the functions of any of the methods described above. Other aspects can include a non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations of any of the methods described above. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate exemplary embodiments and together with the general description given above and the detailed description given below, serve to explain the features of the various embodiments.

[0009] Figure 1 is a component block diagram illustrating an example “system on a chip” (SOC) including a communication channel.

[0010] Figure 2 is a process flow diagram illustrating an embodiment method for designing an integrated circuit.

[0011] Figure 3A is a hierarchical block diagram of components of a wrapper according to various embodiments.

[0012] Figure 3B is a hierarchical block diagram of components of a wrapper according to various embodiments. Figure 3Aa block diagram of a wrapper.

[0013] Figure 4 is a component block diagram illustrating an example SOC having interconnect hard macros positioned with cores of the SOC, in accordance with various embodiments.

[0014] Figure 5 is a component block diagram of a computing device suitable for use with various embodiments.

[0015] Figure 6 is a component block diagram illustrating an example computing device suitable for use with various embodiments.

[0016] Figure 7 is a component block diagram illustrating an example computing device suitable for use with various embodiments. DETAILED DESCRIPTION

[0017] Various embodiments will be described in detail with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and embodiments are for illustrative purposes, and are not intended to limit the scope of the various embodiments or the claims.

[0018] Communication lanes on conventional ICs take up 2-3% of the conventional IC die area, which represents a proportional increase in die area cost. Die area cost contributes to application specific integrated circuit (ASIC) cell cost. As die sizes of conventional ICs continue to increase with the advent of new feature sets, the cost impact of communication lanes on ASIC cell cost also continues to increase. Power domain constraints and aggressive power performance area (PPA) targets of conventional ICs have limited cost savings and ASIC cell cost reduction in communication lane design of conventional ICs.

[0019] Various embodiments include integrated circuits (ICs) and methods for designing integrated circuits (ICs) such as system on a chip (SOC). Embodiments include methods for planning and producing ICs without communication lanes (also referred to as laneless ICs). Embodiments can include overlay hard macros that support routing and communication design without dedicated communication lanes between functional hard macros such as cores of a SOC. Embodiments ICs without dedicated communication lanes between functional hard macros such as SOCs without dedicated communication lanes designed between cores can encompass smaller die areas compared to conventionally designed ICs. Reducing die area of an IC can reduce power consumption compared to conventional ICs. Additionally, reducing die area such as reducing by approximately 1-2% can reduce ASIC cell cost compared to conventional ICs. Reduced die area and related power reduction and reduced ASIC cell cost represent improvements in IC design enabled by various embodiments compared to conventionally designed ICs.

[0020] The term “computing device” is used herein to refer to a cellular telephone, a smartphone, a portable computing device, a personal or mobile multimedia player, a notebook, a tablet, a smartbook, an ultrabook, a palmtop, an email receiver, a multimedia internet enabled cellular telephone, a server, a wired or wireless router device, an appliance, a medical device and instrument, a biometric sensor / device, a wearable device (including a smartwatch, smart clothing, smart glasses, smart wristband, smart jewelry (e.g., smart ring, smart bracelet, etc.)), an entertainment device (e.g., a wireless or wired game controller, a music and video player, a satellite radio, etc.), an internet of things (IoT) device (including a smart meter / sensor) that supports wireless or wired networking, an industrial manufacturing device, a large and small machinery and appliance for home or enterprise use, a wireless communication element within an autonomous and semi-autonomous vehicle, a wireless device fixed to or incorporated into various mobile platforms, a global positioning system device, and similar electronic devices that include memory and programmable processor.

[0021] The term “system on a chip” (SOC) (sometimes also referred to as “system on a chip”) is used herein to refer to a single integrated circuit (IC) chip that contains multiple resources or multiple processors integrated on a single substrate. A single SOC can include circuitry for digital, analog, mixed-signal, and radio-frequency functions. A single SOC can also include any number of general-purpose or special-purpose processors (digital signal processors, modem processors, video processors, etc.), memory blocks (such as ROM, RAM, flash, etc.), and resources (such as timers, voltage regulators, oscillators, etc.). An SOC can also include software for controlling the integrated resources and processors, as well as for controlling peripheral devices.

[0022] The term “system on a package” (SIP) is used herein to refer to a single module or package that contains multiple resources, computing units, cores, or processors on two or more IC chips, substrates, or SOCs. For example, a SIP can include a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP can include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a unified substrate. A SIP can also include multiple independent SOCs that are coupled together via high-speed communication circuitry and packaged in close proximity, such as on a single motherboard or in a single wireless device. The proximity of the SOCs facilitates high-speed communication as well as sharing of memory and resources.

[0023] The term“hard macro” (HM) is used herein to refer to a hardware design of a component of a logic function on an IC, such as a SOC, that defines how components within the logic function are interconnected and the physical paths and wiring between those components. The components of a hard macro are formed from circuit elements, such as transistors, resistors, capacitors, inductors, etc. These components of a hard macro can optionally be connected directly to each other and / or through wires. A hard macro can specify a fixed wiring pattern and cannot be modified after design. A hard macro can have a fixed physical shape. Examples of hard macros include functional hard macros and interconnect hard macros. The term“functional hard macro” is used herein to refer to a hard macro that is dedicated to a specific IC functional operation, including one or more components, and optional wiring between them, such as a core of a SOC (e.g., a multimedia core, a central processing unit (CPU) core, a power infrastructure core, a memory (e.g., double data rate (DDR) memory) core, a modem core, a graphics processing unit (GPU) core, a neural signal processor (NSP) core, an interface connection core (e.g., a peripheral component interconnect express (PCIE) core, etc.). The term“interconnect hard macro” is used herein to refer to a hard macro that is dedicated to communication and routing between other hard macros, including one or more components, and optional wiring between them, such as a communication pipeline hard macro, etc. A hard macro, such as a functional hard macro, an interconnect hard macro, etc., is different from a wire (or routing) discussed herein. A wire (or routing) discussed herein refers to an electrically conductive structure that is typically formed from metal, where there are no circuit elements.

[0024] In a conventional IC design, such as a conventional SOC design, functional hard macros, such as cores of a SOC, are independently developed and shared across many projects. Since an IC, such as a SOC, typically requires communication between functional hard macros, a communication channel for pipeline and routing placement is reserved in a conventional IC physical design. The dedicated communication channel in a conventional IC runs between various functional hard macros, such as between cores of a SOC, and can physically separate the functional hard macros from each other. In a conventional IC, functional hard macros are physically and logically separated from each other through the communication channel, and different functional hard macros (e.g., different SOC cores) typically operate in different voltage domains. Since the distance between functional hard macros from each other can change at the design stage of a conventional IC, the design of the communication channel and the adapted pipeline and clock changes on the conventional IC present significant challenges in IC design.

[0025] Various embodiments include methods for planning and producing an IC without a communication channel, also referred to as a channel-less IC. Embodiments can include overlay hard macros that support routing and communication design of an IC. In various embodiments, an additional hard macro layer of an IC, such as an additional interconnect hard macro layer, can be created to facilitate routing and pipeline placement within functional hard macros, such as within cores of a SOC.

[0026] Various embodiments can include creating a wrapper, such as a design level (DL) one (DL1) wrapper, to indicate locations of one or more interconnect hard macros and wires within a functional hard macro. In various embodiments, the wrapper can include an indication of empty border regions within the functional hard macro that will remain open during design of the functional hard macro. The indication of the empty border regions within the functional hard macro can be a (DL) two (DL2) level hard macro or property (or constraint) of the DL1 wrapper. The wrapper can include overlay hard macros, such as interconnect hard macros and wires. The overlay hard macros, such as interconnect hard macros and wires, can be DL2 level properties (or constraints) of the DL1 wrapper. In various embodiments, the wrapper can be used for ICs, such as SOCs, functional hard macro planning. For example, planar planning shapes of functional hard macros and planning well creation in functional hard macros to align with the indication of empty border regions can be performed using the DL1 wrapper according to various embodiments that includes overlay hard macros.

[0027] Various embodiments can include supporting overlay hard macros for routing and communication design without requiring dedicated communication channels between functional hard macros, such as cores of a SOC. Various embodiments can enable design of ICs, such as SOCs, that support communication paths between two functional hard macros that span IC space allocated to one or more other functional hard macros. By enabling communication paths through other functional hard macros, various embodiments can enable ICs, such as SOCs, to be designed without a die area dedicated (or reserved) for communication channels separate from die areas dedicated (or reserved) for functional hard macros.

[0028] Figure 1 is a component block diagram illustrating an example SOC 100 that includes a communication channel 150. While Figure 1 While one communication channel 150 is illustrated, more than one communication channel can be included in a SOC, such as the SOC 100, and not all communication channels included in a SOC can be connected to each other. The SOC 100 can include a series of functional hard macros, including a multimedia core 102, a CPU core 106, a power infrastructure core 112, a memory core, such as a double data rate (DDR) memory core 110, a modem core 114, a GPU core 116, a NSP core 108, and a PCIE core 104. The SOC 100 can be a conventional design IC, where a die area is dedicated (or reserved) for the communication channel 150 that is separate from die areas for the functional hard macros, specifically the multimedia core 102, the CPU core 106, the power infrastructure core 112, the DDR memory core 110, the modem core 114, the GPU core 116, the NSP core 108, and the PCIE core 104.

[0029] The communication channel 150 can be allocated and designed to support interconnecting the macro and wires for connecting one or more of the multimedia core 102, the CPU core 106, the power infrastructure core 112, the DDR memory core 110, the modem core 114, the GPU core 116, the NSP core 108, and the PCIE core 104. Since the communication channel 150 physically separates the functional hard macros, such as the multimedia core 102, the CPU core 106, the power infrastructure core 112, the DDR memory core 110, the modem core 114, the GPU core 116, the NSP core 108, and the PCIE core 104, from each other, the communication channel 150 adds the total die area required by the SOC 100 beyond any die area required by the functional hard macros themselves.

[0030] Figure 2 is a process flow diagram illustrating an embodiment method 200 for designing an integrated circuit. Referring to Figures 1-2 In various embodiments, the operations of the method 200 can be performed by a processor of a computing device. In various embodiments, the operations of the method 200 can enable an IC, such as a SOC, to be designed without a die area dedicated (or reserved) for a communication channel separate from a die area dedicated (or reserved) for a functional hard macro. In some embodiments, the method 200 can be implemented in a computer-based tool in which a processor is configured to perform the operations of the method.

[0031] In block 202, the processor can determine a first functional hard macro and a second functional hard macro of an integrated circuit, the first functional hard macro and the second functional hard macro needing a physical communication path from each other, wherein the first functional hard macro and the second functional hard macro are separated from each other by at least a portion of a third functional hard macro of the integrated circuit. For example, by receiving an indication of a selection of a first functional hard macro, such as a PCIE core of a SOC, and an indication of a selection of a second functional hard macro, such as a DDR memory core of the SOC, by a user of the computing device, the processor can determine a first functional hard macro and a second functional hard macro of an integrated circuit that need a physical communication path from each other, wherein the first functional hard macro can need to communicate with the second functional hard macro. The first functional hard macro, such as the PCIE core, can be allocated to a first dedicated (or reserved) area on a die of the SOC, and the second functional hard macro, such as the DDR memory core, can be allocated to a second dedicated (or reserved) area on the die of the SOC. Based on a layout of the SOC, the third functional hard macro, such as a multimedia core, can be positioned in a third dedicated (or reserved) area on the die of the SOC such that at least a portion of the third functional hard macro separates the first functional hard macro, such as the PCIE core, from the second functional hard macro, such as the DDR memory core.

[0032] In block 204, the processor can determine locations for one or more interconnect hard macros and wires connecting one or more interconnect hard macros within a first functional hard macro, a second functional hard macro, and a third functional hard macro. For example, based on constraints (or requirements) on timing latency, communication power consumption, and / or communication distance thresholds, the processor can determine locations for one or more interconnect hard macros and wires for connecting a first functional hard macro (such as a PCIE core) to a second functional hard macro (such as a DDR memory core). As a specific example, the locations of one or more communication pipeline hard macros can be determined based at least in part on latency thresholds and frequency requirements for communications between a first functional hard macro (such as a PCIE core) and a second functional hard macro (such as a DDR memory core). The locations of the one or more interconnect hard macros can be determined within a third functional hard macro such that a communication path from the first functional hard macro (such as a PCIE core) to the second functional hard macro (such as a DDR memory core) can span a die area dedicated (or reserved) for the third functional macro (such as a multimedia core). The locations of the one or more interconnect hard macros and wires can be determined such that the locations of the one or more interconnect hard macros and wires can support the first functional hard macro being electrically coupled to the second hard macro through the one or more interconnect hard macros and wires.

[0033] In block 206, the processor can generate a wrapper indicating the determined locations of the one or more interconnect hard macros and wires. For example, the generated wrapper can be a DL1 wrapper indicating the determined locations of the one or more interconnect hard macros and wires within a third functional hard macro (such as a multimedia core). The DL1 wrapper can include an indication of a free boundary region within the third functional hard macro (such as a multimedia core) that was left open during design of the third functional hard macro (such as a multimedia core). The indication of the free boundary region within the third functional hard macro (such as a multimedia core) can be a DL2 level hard macro or property (or constraint) of the DL1 wrapper. The DL1 wrapper can include overlay hard macros, such as interconnect hard macros and wires, to fill the free boundary region as a DL2 level hard macro or property (or constraint).

[0034] In block 208, the processor can configure the third functional hard macro according to the wrapper such that the third functional hard macro includes a free boundary region at the determined locations of the one or more interconnect hard macros and wires. In various embodiments, the wrapper can be used for IC (such as a SOC) functional hard macro planning. For example, planar planning shapes of the third functional hard macro (such as a multimedia core) and planning well creation in the third functional hard macro (such as a multimedia core) to align with the indication of the free boundary region can be performed using the DL1 wrapper.

[0035] In block 210, the processor can overlay one or more interconnect hard macros and wires into the empty border region in the third functional hard macro. In this way, the design of the overall IC, such as the overall IC, can include one or more interconnect hard macros and wires in-well in the third functional hard macro, such as the multimedia core, that correspond to the empty border region defined by the DL1 wrapper. As an example, the interconnect hard macros and wires can fill the empty border region such that the first functional hard macro can be electrically coupled to the second hard macro through the one or more interconnect hard macros and wires. In addition to being within the empty border region, in various embodiments, the wires can extend outside of the empty border region.

[0036] Figure 3A is a hierarchical block diagram of components of a DL1 wrapper 301 according to various embodiments. Referring to Figures 1-3A , the DL1 wrapper 301 can be a wrapper generated according to the operations of the method 200( Figure 2 ) of FIG. 2. The DL1 wrapper 301 can include a DL2 hard macro 302 having an empty border region 310 and a DL2 overlay 303 having locations of interconnect hard macros 320 and wires 325. As a specific example, the interconnect hard macros 320 can be a communication pipeline hard macro.

[0037] Figure 3B is a block diagram of the DL1 wrapper 301 showing an alignment between the DL2 hard macro 302 and the DL2 overlay 303 when the DL2 overlay 303 overlaps the DL2 hard macro 302 in the DL1 wrapper 301. Referring to Figures 1-3B , the locations of the interconnect hard macros 320 and wires 325 are aligned with the empty border region 310 such that the DL2 hard macro 302 completely surrounds the interconnect hard macros 320. In this way, the interconnect hard macros 320 can be included in the die area of the DL2 hard macro 302.

[0038] Figure 4 is a component block diagram showing an example SOC 400 according to various embodiments. Referring to Figures 1-4 , the SOC 400 can include interconnect hard macros 320 located within a functional hard macro of the SOC 400, such as the multimedia core 402. The SOC 400 can include a series of functional hard macros including the multimedia core 402, a CPU core 406, a power infrastructure core 412, a memory core such as the DDR memory core 110, a modem core 414, a GPU core 416, an NSP core 408, and a PCIE core 404. The SOC 400 can be an overall IC according to the method 200( Figure 2Examples of ICs designed for operation include the DL1 wrapper 301. For instance, the DL1 wrapper 301 can be used to establish a communication path between the PCIe core 404 and the DDR memory core 410 via the multimedia core 402. In various embodiments, according to the DL1 wrapper 301, an interconnect hardware macro 320 can be located within the multimedia core 402, and wires 325 can connect the PCIe core 404, the interconnect hardware macro 320, and the DDR memory core 410. In this way, the PCIe core 404 can be electrically coupled to the DDR memory core 410 via the interconnect hardware macro 320 and the wires 325.

[0039] like Figure 4 As shown, although the PCIe core 404 and the DDR memory core 410 are adjacent to different sides of the multimedia core 402 (e.g., Figure 4 The orientation is on the right and bottom sides), and the multimedia core 402 physically separates the PCIe core 404 from the DDR memory core 410, but the communication channel between the multimedia core 402, the PCIe core 404, and the DDR memory core 410 does not exist in the SOC 400. Figure 4 As shown, the PCIe core 404 and the DDR memory core 410 are not adjacent on the sides. In the SOC 100 including communication channel 150... Figure 1 ) and the channelless embodiment SOC 400 ( Figure 4 A comparison between the two implementations reveals that SOC 400 lacks a communication channel. In embodiment SOC 400, because the DL1 package 301 allows the interconnect macro 320 and wires 325 to reside within a die region dedicated to (or reserved for) the multimedia core 402, a dedicated (or reserved) communication channel separate from the die regions dedicated to (or reserved for) the multimedia core 402, PCIe core 404, and DDR memory core 410 is not required. In this way, the PCIe core 404 and DDR memory core 410 can communicate via the interconnect macro 320 and wires 325, without a dedicated (or reserved) communication channel between the PCIe core 404 and the DDR memory core 410.

[0040] Figure 5 It is suitable for implementing some embodiments (including but not limited to the above references) Figures 2-4 A component block diagram of a computing device in the form of a smartphone 500 (described from various aspects). Reference Figures 1-5, the smartphone 500 can implement operations of the method 200 and / or can use an IC designed according to various embodiments, such as the SOC 400. The smartphone 500 can include a first SOC 540, such as a SOC-CPU, coupled to a second SOC 502, such as a SOC with 5G capabilities. As one specific example, the SOC 502 can be the SOC 400. The first SOC 540 and the second SOC 502 can be coupled to internal memory 516, 506, a display 512, and a speaker 514. Further, the smartphone 500 can include an antenna 504 for sending and receiving electromagnetic radiation, which can be connected to a wireless data link or cellular telephone transceiver 508 coupled to one or more processors in the first SOC 540 or the second SOC 502. For example, the antenna 504 can be used to electrically connect and issue configuration and task mode memory access commands to external memory devices. The smartphone 500 also typically includes menu selection buttons or a rocker switch 520 for receiving user inputs.

[0041] A typical smartphone 500 also includes sound encoding / decoding (CODEC) circuitry 510 that digitizes sound received from a microphone into data packets suitable for wireless transmission and decodes received sound data packets to generate analog signals that are provided to a speaker to generate sound. Further, one or more processors in the first SOC 540 and the second SOC 502, the wireless transceiver 508, and the CODEC 510 can include digital signal processor (DSP) circuitry (not shown separately).

[0042] Various aspects, including but not limited to the above-referenced Figures 2-4 described aspects) can be implemented in various computing systems, including a laptop computer 600, an example of which is shown in Figure 6 Reference is made to Figures 1-6The laptop computer 600 can implement the operation of method 200 and / or can use an IC designed according to various embodiments, such as a SOC 400. Many laptop computers include a touchpad touch surface 617 that serves as a pointing device for the computer and can therefore receive drag, scroll, and flick gestures similar to those implemented on computing devices equipped with touchscreen displays and as described above. The laptop computer 600 will typically include a processor 611 coupled to volatile memory 612 and a disk drive 613 of mass non-volatile memory, such as flash memory. In addition, the computer 600 may have one or more antennas 608 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or a cellular transceiver 616 coupled to the processor 611. The computer 600 may also include a floppy disk drive 614 and an optical disc (CD) drive 615 coupled to the processor 611. In a laptop configuration, the computer casing includes a touchpad 617, a keyboard 618, and a display 619, all coupled to the processor 611. As a specific example, processor 611 could be an SOC 400. Other configurations of the computing device could include, for example, a computer mouse or trackball coupled to the processor (e.g., via Universal Serial Bus (USB) input), which could also be used in combination with other features.

[0043] All aspects (including but not limited to the above references) Figures 2-4 The described aspects can also be implemented in fixed computing systems, such as any of a variety of commercially available servers, such as Figure 7 The server is 700. (Reference) Figures 1-7 Server 700 can implement the operation of method 200 and / or may use an IC designed according to various embodiments, such as SOC 400. Such a server 700 typically includes one or more processor components 701 coupled to volatile memory 702 and mass non-volatile memory (such as disk drive 704). Figure 7 As shown, processor component 701 can be added to server 700 by inserting it into a rack. As a specific example, processor component 701 may be or may include SOC 400. Server 700 may also include floppy disk drive, compact disc (CD), or digital multifunction disc (DVD) drive 706 coupled to processor component 701. Server 700 may also include network access port 703 coupled to processor component 701 to establish a network interface connection with network 705, such as a local area network, the Internet, public switched telephone network, and / or cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0044] Processors 500, 611, 701 can be any programmable microprocessor, microcomputer or multiple processor chip that can be configured by processor executable instructions to perform a variety of functions, including the functions of the various embodiments described herein. In some computing devices, multiple processors can be provided, such as one processor within SOC 502 dedicated to wireless communication functions and one processor within SOC 540 dedicated to running other applications. Typically, software applications can be stored in storage before being accessed and loaded into the processor. The processor can include internal memory sufficient to store the application software instructions.

[0045] As used in this application, the terms“component,”“module,”“system” and the like are intended to include a computer-related entity, such as but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution, which are configured to perform particular operations or functions. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer. By way of illustration, both an application running on a wireless device and the wireless device can be referred to as a component. One or more components can reside within a process or thread of execution and a component can be localized on one processor or core or distributed across two or more processors or cores. In addition, these components can execute from various non-transitory computer-readable media having various instructions or data structures stored thereon. Components can communicate by way of local or remote processes, function or procedure calls, electronic signals, data packets, memory reads / writes, and other known computer, processor, or process related communication methods.

[0046] The various embodiments shown and described are provided merely as examples to illustrate various features of the claims. However, features shown and described with respect to any given embodiment are not necessarily limited to the associated embodiment and can be used with or combined with other embodiments shown and described. Moreover, the claims are not limited to any one example embodiment. For example, one or more operations of the methods disclosed herein can be substituted for or combined with one or more operations of the methods disclosed herein.

[0047] The following paragraphs describe implementation examples. While some implementation examples are described in terms of example methods, other example implementations can include: an example method discussed in the following paragraphs implemented by a computing device including a processor configured with processor-executable instructions to perform the operations of the method implementing the example; an example method discussed in the following paragraphs implemented by a computing device including components to perform the functionality of the method implementing the example; and an example method discussed in the following paragraphs can be implemented as a non-transitory processor-readable storage medium having stored processor-executable instructions configured to cause a processor of a computing device to perform the operations of the method implementing the example. While some implementation examples are described in terms of example integrated circuits, other example implementations can include devices having integrated circuits implementing the examples.

[0048] Example 1 : An integrated circuit comprising:

[0049] a first functional hard macro;

[0050] a second functional hard macro;

[0051] a third functional hard macro;

[0052] one or more interconnect hard macros within the third functional hard macro; and

[0053] wiring connecting the first functional hard macro, the second functional hard macro, and the one or more interconnect hard macros.

[0054] Example 2. The integrated circuit of example 1, wherein the first functional hard macro is electrically coupled to the second functional hard macro through the one or more interconnect hard macros and the wiring.

[0055] Example 3. The integrated circuit of any of examples 1-2, wherein a side of the first functional hard macro and a side of the second functional hard macro do not abut.

[0056] Example 4. The integrated circuit of any of examples 1-2, wherein the first functional hard macro and the second functional hard macro abut different sides of the third functional hard macro.

[0057] Example 5. The integrated circuit of any of examples 1-4, wherein there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

[0058] Example 6. The integrated circuit of any of examples 1-5, wherein the third functional hard macro completely surrounds the one or more interconnect hard macros.

[0059] Example 7. The integrated circuit of any of examples 1-6, wherein the one or more interconnect hard macros comprise a communication pipeline hard macro.

[0060] Example 8. The integrated circuit of any of examples 1-7, wherein:

[0061] the integrated circuit comprises a system on a chip (SOC); and

[0062] the first functional hard macro, the second functional hard macro, and the third functional hard macro each comprise a first core, a second core, and a third core.

[0063] Example 9. A method for designing an integrated circuit, comprising:

[0064] determining a first functional hard macro and a second functional hard macro of the integrated circuit, the first functional hard macro and the second functional hard macro requiring a physical communication path from one another, wherein the first functional hard macro and the second functional hard macro are separated from one another by at least a portion of a third functional hard macro of the integrated circuit;

[0065] determining locations for one or more interconnect hard macros and wires connecting the first functional hard macro, the second functional hard macro, and the one or more interconnect hard macros within the third functional hard macro;

[0066] generating a wrapper indicating the determined locations of the one or more interconnect hard macros and the wires; and

[0067] configuring the third functional hard macro according to the wrapper such that the third functional hard macro comprises empty border regions at the determined locations of the one or more interconnect hard macros and the wires.

[0068] Example 10. The method of example 9, further comprising: overlaying the one or more interconnect hard macros and the wires into the empty border regions in the third functional hard macro.

[0069] Example 11. The method of any of examples 9-10, wherein the first functional hard macro, the second functional hard macro, and the third functional hard macro are configured such that there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

[0070] Example 12. The method of any of examples 9-11, wherein the one or more interconnect hard macros comprise a communication pipeline hard macro.

[0071] Example 13. The method of any of examples 9-12, wherein:

[0072] the integrated circuit comprises a system on a chip (SOC); and

[0073] The first functional hard macro, the second functional hard macro, and the third functional hard macro include first, second, and third cores, respectively.

[0074] The foregoing method descriptions and the process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the blocks of the various embodiments must be performed in the order presented. As will be appreciated by one of ordinary skill in the art, the order of blocks in the foregoing embodiments can be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the blocks; these words are simply used to guide the reader through the description of the methods. Furthermore, any reference to claim elements in the singular, for example, using the articles "a," "an" or "the" is not

[0075] As used herein, the phrase "at least one of" a list of items refers to any combination of those items, including single members. For example, "at least one of a, b, or c" is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.

[0076] The various illustrative logical blocks, modules, circuits, and algorithm blocks described in connection with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and blocks have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the various embodiments.

[0077] The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some embodiments, particular processes and methods can be performed by circuitry that is specific to a given function.

[0078] In one or more aspects, the functions described can be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents, or in any combination thereof. Embodiments of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data processing apparatus.

[0079] Computer program code or "program code" for execution on a programmable processor for performing operations for various embodiments can be written in a high level programming language, such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, a structured query language (e.g., Transact-SQL), Perl, or various other programming languages. Program code or programs stored on a computer readable storage medium as used in this application can refer to machine language code (such as object code) whose format can be understood by a processor.

[0080] If implemented in software, the functions can be stored or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein can be implemented in a processor-executable software module which can reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. Storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. Disk and disc, as used herein, includes compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks and blu-ray discs where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm can reside in one or any combination of the machine-readable media used to store the code and instructions for the operating system and other programs utilized in performing the method of operations. The method can be implemented as a computer program, software, or firmware that operates to perform the processes described herein.

[0081] Various modifications to the embodiments described in this disclosure can be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the scope of the claims. Therefore, the claims are not intended to be limited to the embodiments shown herein, but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit, comprising: First function: hard macro; Second function: hard macro; Third function: hard macro; The first functional hard macro and the second functional hard macro are separated from each other by at least a portion of the third functional hard macro; One or more interconnect hard macros, wherein the one or more interconnect hard macros are located within the third functional hard macro; as well as A wire connects the first functional hard macro, the second functional hard macro, and the one or more interconnecting hard macros, wherein the third functional hard macro includes an empty boundary region at the location of the one or more interconnecting hard macros and the wire.

2. The integrated circuit of claim 1, wherein the first functional hard macro is electrically coupled to the second functional hard macro via the one or more interconnect hard macros and the wires.

3. The integrated circuit according to claim 1, wherein the side surface of the first functional hard macro and the side surface of the second functional hard macro are not adjacent.

4. The integrated circuit of claim 1, wherein the first functional hard macro and the second functional hard macro are adjacent to different sides of the third functional hard macro.

5. The integrated circuit of claim 4, wherein there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

6. The integrated circuit of claim 1, wherein the third functional hard macro completely surrounds the one or more interconnect hard macros.

7. The integrated circuit of claim 1, wherein the one or more interconnect hard macros include communication pipeline hard macros.

8. The integrated circuit according to claim 1, wherein: The integrated circuit includes a system-on-a-chip (SOC); and The first functional hard macro, the second functional hard macro, and the third functional hard macro each include a first core, a second core, and a third core, respectively.

9. A method for designing integrated circuits, comprising: A first functional hard macro and a second functional hard macro are determined in the integrated circuit, the first functional hard macro and the second functional hard macro require a physical communication path to each other, wherein the first functional hard macro and the second functional hard macro are separated from each other by at least a portion of a third functional hard macro of the integrated circuit; Determine the location for one or more interconnect hard macros and wires, the wires connecting the one or more interconnect hard macros within the first functional hard macro, the second functional hard macro, and the third functional hard macro; Generate a wrapper indicating the determined locations of the one or more interconnected hard macros and the wires; as well as The third functional hard macro is configured according to the packager such that the third functional hard macro includes empty boundary regions at the determined locations of the one or more interconnecting hard macros and the conductors.

10. The method of claim 9, further comprising: The one or more interconnecting hard macros and the wires are overlaid into the empty boundary region of the third functional hard macro.

11. The method of claim 9, wherein the first functional hard macro, the second functional hard macro, and the third functional hard macro are configured such that there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

12. The method of claim 9, wherein the one or more interconnect hard macros include communication pipeline hard macros.

13. The method according to claim 9, wherein: The integrated circuit includes a system-on-a-chip (SOC); and The first functional hard macro, the second functional hard macro, and the third functional hard macro each include a first core, a second core, and a third core, respectively.

14. A computing device, comprising: The processor is configured with processor-executable instructions for the following: A first functional hard macro and a second functional hard macro are determined for an integrated circuit, the first functional hard macro and the second functional hard macro require a physical communication path to each other, wherein the first functional hard macro and the second functional hard macro are separated from each other by at least a portion of a third functional hard macro of the integrated circuit. Determine the location for one or more interconnect hard macros and wires, the wires connecting the one or more interconnect hard macros within the first functional hard macro, the second functional hard macro, and the third functional hard macro; Generate a wrapper indicating the determined locations of the one or more interconnected hard macros and the wires; as well as The third functional hard macro is configured according to the packager such that the third functional hard macro includes empty boundary regions at the determined locations of the one or more interconnecting hard macros and the conductors.

15. The computing device of claim 14, wherein the processor is further configured with processor-executable instructions for covering the one or more interconnect hard macros and the wires into the empty boundary region of the third functional hard macro.

16. The computing device of claim 14, wherein the processor is configured with processor-executable instructions to configure the first functional hard macro, the second functional hard macro, and the third functional hard macro such that there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

17. The computing device of claim 14, wherein the one or more interconnect hard macros include communication pipeline hard macros.

18. The computing device according to claim 14, wherein: The integrated circuit includes a system-on-a-chip (SOC); and The first functional hard macro, the second functional hard macro, and the third functional hard macro each include a first core, a second core, and a third core, respectively.

19. A non-transitory processor-readable medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a processor of a computing device to perform operations including: A first functional hard macro and a second functional hard macro are determined for an integrated circuit, the first functional hard macro and the second functional hard macro require a physical communication path to each other, wherein the first functional hard macro and the second functional hard macro are separated from each other by at least a portion of a third functional hard macro of the integrated circuit. Determine the location for one or more interconnect hard macros and wires, the wires connecting the one or more interconnect hard macros within the first functional hard macro, the second functional hard macro, and the third functional hard macro; Generate a wrapper indicating the determined locations of the one or more interconnected hard macros and the wires; as well as The third functional hard macro is configured according to the packager such that the third functional hard macro includes empty boundary regions at the determined locations of the one or more interconnecting hard macros and the conductors.

20. The non-transitory processor-readable medium of claim 19, wherein the stored processor-executable instructions are configured to cause a processor of a computing device to perform an operation further comprising: covering the one or more interconnect hard macros and the wires into the empty boundary region of the third functional hard macro.

21. The non-transitory processor-readable medium of claim 19, wherein the stored processor-executable instructions are configured to cause a processor of a computing device to perform operations such that the first functional hard macro, the second functional hard macro, and the third functional hard macro are configured such that there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

22. The non-transitory processor-readable medium of claim 19, wherein the stored processor-executable instructions are configured to cause a processor of a computing device to perform operations such that the one or more interconnect hard macros include communication pipeline hard macros.

23. A computing device, comprising: Components for determining a first functional hard macro and a second functional hard macro of an integrated circuit, the first functional hard macro and the second functional hard macro requiring a physical communication path to each other, wherein the first functional hard macro and the second functional hard macro are separated from each other by at least a portion of a third functional hard macro of the integrated circuit. Components for determining the location of one or more interconnect hard macros and wires, the wires connecting the one or more interconnect hard macros within the first functional hard macro, the second functional hard macro, and the third functional hard macro; Components for generating a package that indicates the determined positions of the one or more interconnected hard macros and the wires; as well as Components for configuring the third functional hard macro according to the package such that the third functional hard macro includes empty boundary regions at the determined locations of the one or more interconnecting hard macros and the conductors.

24. The computing device of claim 23, further comprising: Components for covering the one or more interconnecting hard macros and the wires into the empty boundary area in the third functional hard macro.

25. The computing device of claim 23, wherein the first functional hard macro, the second functional hard macro, and the third functional hard macro are configured such that there is no communication channel between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

26. The computing device of claim 23, wherein the one or more interconnect hard macros include communication pipeline hard macros.

27. The computing device according to claim 23, wherein: The integrated circuit includes a system-on-a-chip (SOC); and The first functional hard macro, the second functional hard macro, and the third functional hard macro each include a first core, a second core, and a third core, respectively.

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