Semiconductor devices and their fabrication methods

Abstract

A semiconductor device and a method for fabricating the same, the semiconductor device comprising: a substrate (10), a first support structure (11), a first nanowire heterojunction (12), a source (13b), a drain (13c), and a ring gate (13a); wherein the substrate (10) comprises a first region (10a), and a second region (10b) and a third region (10c) respectively located on both sides of the first region (10a); the first support structure (11) is located at least on the second region (10b) and the third region (10c); the first nanowire heterojunction (13a) 12) includes a first gate segment (12a) corresponding to the first region (10a), a first source segment (12b) corresponding to the second region (10b), and a first drain segment (12c) corresponding to the third region (10c); the first source segment (12b) and the first drain segment (12c) are located on the first support structure (11); the source (13b) is located in the first source segment (12b), the drain (13c) is located in the first drain segment (12c), and the ring gate (13a) covers the first gate segment (12a). Since the first nanowire heterojunction (12) is confined, the two-dimensional electron gas or two-dimensional hole gas carriers in the heterojunction exhibit an approximately one-dimensional transport mode during migration, which can improve carrier mobility, breakdown voltage, and reduce leakage current.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] As a typical representative of third-generation semiconductor materials, group III nitrides, with their wide bandgap semiconductors, have excellent properties such as large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and easy formation of high-quality heterostructures. They are very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] For example, AlGaN / GaN heterojunctions have strong spontaneous polarization and piezoelectric polarization, resulting in a high concentration of two-dimensional electron gas (2DEG) at the AlGaN / GaN interface. They are widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] In planar devices, current flows along the plane within the quantum well formed by the heterojunction structure. Under reverse bias, the electric field distribution is typically non-uniform, generally resulting in severe electric field concentration at the gate or drain edges. This electric field increases rapidly with increasing reverse voltage, and the device breaks down when the critical breakdown field strength is reached.

[0005] A higher breakdown voltage means a wider operating voltage range, higher power density, and greater reliability. Therefore, improving the breakdown voltage of devices is a key focus for electronic device researchers. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device and its manufacturing method, thereby improving the breakdown voltage.

[0007] To achieve the above objectives, a first aspect of the present invention provides a semiconductor device comprising:

[0008] The substrate includes a first region and a second region and a third region located on both sides of the first region, respectively;

[0009] A first support structure located at least in the second region and the third region;

[0010] The first nanowire heterojunction includes a first gate segment corresponding to the first region, a first source segment corresponding to the second region, and a first drain segment corresponding to the third region; the first source segment and the first drain segment are located on the first support structure.

[0011] The source is located on the first source region, the drain is located on the first drain region, and the annular gate covers the first gate region.

[0012] Optionally, the first support structure is located only in the second region and the third region.

[0013] Optionally, the substrate further includes a fourth region located between the first region and the second region, and a fifth region located between the first region and the third region; the first support structure is located on the second region and the fourth region.

[0014] Optionally, a gate insulating layer is provided between the first gate segment and the annular gate.

[0015] Optionally, the first nanowire heterojunction includes, from bottom to top: a first channel layer and a first barrier layer, or includes: a first back barrier layer, a first channel layer and a first barrier layer; and / or the first nanowire heterojunction is surrounded by a first anti-scattering layer.

[0016] Optionally, the first nanowire heterojunction has multiple nanowires.

[0017] Optionally, each of the first nanowire heterojunctions shares the first source section and / or the first drain section.

[0018] Optionally, the annular gates covering each of the first nanowire heterojunctions are separated from each other, or the annular gates covering each of the first nanowire heterojunctions are connected together.

[0019] Optionally, the semiconductor device further includes:

[0020] A second support structure located at least on the first source region and the first drain region;

[0021] The second nanowire heterojunction includes a second gate segment corresponding to the first region, a second source segment corresponding to the second region, and a second drain segment corresponding to the third region; the second source segment and the second drain segment are located on the second support structure.

[0022] Optionally, the second nanowire heterostructure has multiple nanowires.

[0023] Optionally, each of the second nanowire heterojunctions shares the second source segment and / or the second drain segment.

[0024] Optionally, the annular gate covers a second nanowire heterojunction and the first nanowire heterojunction directly below the second nanowire heterojunction.

[0025] Another aspect of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0026] A substrate is provided, the substrate including a first region and a second region and a third region located on opposite sides of the first region; a first support structure is formed on at least the second region and the third region; a first sacrificial layer is formed on the substrate exposed by the first support structure;

[0027] A first nanowire heterojunction is grown on the first support structure and the first sacrificial layer. The first nanowire heterojunction includes a first gate segment corresponding to the first region, a first source segment corresponding to the second region, and a first drain segment corresponding to the third region. The first source segment and the first drain segment are located on the first support structure, and at least the first gate segment is located on the first sacrificial layer.

[0028] Remove the first sacrificial layer and suspend the first nanowire heterojunction.

[0029] A source is formed on the first source region, a drain is formed on the first drain region, and a ring gate is formed covering the first gate region.

[0030] Optionally, the first support structure is located only on the second region and the third region; after removing the first sacrificial layer, the suspended first nanowire heterojunction extends from the first source region to the first drain region.

[0031] Optionally, the substrate further includes a fourth region located between the first region and the second region, and a fifth region located between the first region and the third region; the first support structure is located on the second region and the fourth region, and on the third region and the fifth region; after removing the first sacrificial layer, the suspended first nanowire heterojunction is only the first gate segment.

[0032] Optionally, before forming the annular gate, a gate insulating layer is coated on the first gate segment; the annular gate is coated with the gate insulating layer.

[0033] Optionally, the grown first nanowire heterostructure consists of multiple nanowires.

[0034] Optionally, each of the first nanowire heterojunctions shares the first source section and / or the first drain section.

[0035] Optionally, forming the first support structure includes: growing a first epitaxial layer on the substrate; patterning the first epitaxial layer, retaining at least the first epitaxial layer on the second region and the third region to form the first support structure;

[0036] Alternatively, it may include: forming a first patterned mask layer on the substrate, the first patterned mask layer having a first opening, the first opening exposing at least the second region and the third region; and epitaxially growing the first support structure on the substrate using the first patterned mask layer as a mask.

[0037] Optionally, forming the first sacrificial layer includes: growing the first sacrificial layer on the first support structure and the substrate exposed by the first support structure, and removing the first sacrificial layer on the first support structure;

[0038] Alternatively, it may include: using the first support structure as a mask to grow the first sacrificial layer on the substrate.

[0039] Optionally, the method for fabricating the semiconductor device further includes:

[0040] A second support structure is formed at least on the first source region and the first drain region; a second sacrificial layer is formed on the first nanowire heterojunction exposed by the second support structure;

[0041] A second nanowire heterojunction is grown on the second support structure and the second sacrificial layer. The second nanowire heterojunction includes a second gate segment corresponding to the first region, a second source segment corresponding to the second region, and a second drain segment corresponding to the third region. The second source segment and the second drain segment are located on the second support structure, and at least the second gate segment is located on the second sacrificial layer.

[0042] Remove the second sacrificial layer to suspend the second nanowire heterojunction.

[0043] Optionally, forming the second support structure includes: growing a second epitaxial layer on the first nanowire heterojunction; patterning the second epitaxial layer, retaining at least the second epitaxial layer on the first source segment and the first drain segment to form the second support structure;

[0044] Alternatively, it may include: forming a second patterned mask layer on the first nanowire heterojunction, the second patterned mask layer having a second opening, the second opening exposing at least the first source segment and the first drain segment; using the second patterned mask layer as a mask, epitaxially growing the second support structure on the first nanowire heterojunction.

[0045] Optionally, forming the second sacrificial layer includes: growing the second sacrificial layer on the second support structure and the first nanowire heterojunction exposed by the second support structure, and removing the second sacrificial layer on the second support structure;

[0046] Alternatively, it may include: using the second support structure as a mask to grow the second sacrificial layer on the first nanowire heterojunction.

[0047] Optionally, the material of the first sacrificial layer and / or the second sacrificial layer is N-type GaN.

[0048] Optionally, the removal of the first sacrificial layer and / or the removal of the second sacrificial layer are achieved using a selective etching solution.

[0049] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0050] 1) In semiconductor devices, because the first nanowire heterojunction is confined, the two-dimensional electron gas carriers or two-dimensional hole gas carriers within the heterojunction exhibit an approximately one-dimensional transport mode during migration, which can improve carrier mobility. In addition, the ring gate's control over carriers is also greatly improved, thus significantly increasing the device's breakdown voltage and reducing leakage current problems, and improving the efficiency and linearity of RF devices.

[0051] 2) In the alternative scheme, a) the first support structure is located only on the second and third regions; or b) the substrate further includes a fourth region located between the first and second regions, and a fifth region located between the first and third regions; the first support structure is located on the second and fourth regions, and on the third and fifth regions. Compared to scheme b), the advantage of scheme a) is that it can increase the suspended segment of the first nanowire heterojunction, thus reducing the probability of carrier annihilation within the heterojunction and the contact layer.

[0052] 3) In the optional schemes, a) the annular gate directly contacts the first gate segment; or b) there is a gate insulating layer between the annular gate and the first gate segment. Compared with scheme a), the advantage of scheme b) is that the MIS gate can reduce gate leakage current.

[0053] 4) In the optional scheme, the first nanowire heterojunction has multiple segments, each sharing a first source segment and a first drain segment. The advantage is that, compared to a single first nanowire heterojunction, multiple nanowire heterojunctions provide multiple carrier migration channels, which can further improve carrier mobility.

[0054] 5) In the optional scheme, the annular gates covering each first nanowire heterojunction are separated from each other, or the annular gates covering each first nanowire heterojunction are connected together. The advantage is that it can meet different performance requirements.

[0055] 6) In an optional embodiment, the semiconductor device further includes a second nanowire heterojunction stacked on the first nanowire heterojunction. The advantage is that the second nanowire heterojunction effectively provides additional carrier migration channels, thus further improving carrier mobility. Attached Figure Description

[0056] Figure 1 This is a three-dimensional structural schematic diagram of the semiconductor device according to the first embodiment of the present invention;

[0057] Figure 2(a) and Figure 2(b) are along Figure 1 The cross-sectional view of the AA line in the image shows that the structures of the first nanowire heterojunctions are not the same.

[0058] Figure 2(c) is a schematic diagram of the first nanowire heterojunction in Figure 2(a) surrounded by the first anti-scattering layer;

[0059] Figure 3 It is to remove Figure 1 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate;

[0060] Figure 4 yes Figures 1 to 2(c) A flowchart of the semiconductor device fabrication method;

[0061] Figures 5 to 8(b) yes Figure 4 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0062] Figure 9 This is a three-dimensional structural schematic diagram of a semiconductor device according to a second embodiment of the present invention;

[0063] Figure 10 It is to remove Figure 9 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate;

[0064] Figure 11 This is a three-dimensional structural schematic diagram of a semiconductor device according to a third embodiment of the present invention;

[0065] Figure 12 This is a three-dimensional structural schematic diagram of the semiconductor device according to the fourth embodiment of the present invention;

[0066] Figure 13 This is a three-dimensional structural schematic diagram of the semiconductor device according to the fifth embodiment of the present invention;

[0067] Figure 14(a) and Figure 14(b) are along Figure 13 A cross-sectional view of the BB line in the image, where the structure of the second nanowire heterojunction is different;

[0068] Figure 14(c) is a schematic diagram of the second nanowire heterojunction in Figure 14(a) with a second anti-scattering layer surrounding it.

[0069] Figure 15 It is to remove Figure 13 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate;

[0070] Figure 16 It is to remove Figure 15 A three-dimensional schematic diagram of the semiconductor structure behind the gate insulating layer;

[0071] Figure 17 yes Figures 13 to 14(c) A flowchart of the semiconductor device fabrication method;

[0072] Figures 18 to 20 yes Figure 17 A schematic diagram of the intermediate structure corresponding to the process in the document;

[0073] Figure 21 This is a three-dimensional structural schematic diagram of a semiconductor device according to the sixth embodiment of the present invention;

[0074] Figure 22 This is a three-dimensional structural schematic diagram of the semiconductor device according to the seventh embodiment of the present invention;

[0075] Figure 23 This is a three-dimensional structural schematic diagram of the semiconductor device according to the eighth embodiment of the present invention;

[0076] Figure 24 It is to remove Figure 23 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate;

[0077] Figure 25 It is to remove Figure 24 A three-dimensional schematic diagram of the semiconductor structure behind the gate insulating layer;

[0078] Figure 26 This is a three-dimensional structural schematic diagram of a semiconductor device according to the ninth embodiment of the present invention.

[0079] To facilitate understanding of this invention, all reference numerals appearing in the accompanying drawings are listed below:

[0080] Substrate 10 First Region 10a

[0081] Zone 2 10b Zone 3 10c

[0082] Fourth region 10d, Fifth region 10e

[0083] First support structure 11 First nanowire heterojunction 12

[0084] First channel layer 121 First barrier layer 122

[0085] First back barrier layer 123 First gate segment 12a

[0086] First source section 12b First drain section 12c

[0087] Source 13b Drain 13c

[0088] Ring gate 13a Gate insulating layer 14

[0089] First anti-scattering layer 141; Second nanowire heterostructure 16

[0090] Second channel layer 161 Second barrier layer 162

[0091] Second back barrier layer 163 Second anti-scattering layer 142

[0092] Second gate section 16a Second source section 16b

[0093] Second drain section 16c, second support structure 15

[0094] First sacrificial layer 17 First extensional layer 11'

[0095] Second extensional layer 15' Second sacrificial layer 18

[0096] Semiconductor devices 1, 2, 3, 4, 5, 6, 7, 8, 9 Detailed Implementation

[0097] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0098] Figure 1 This is a three-dimensional structural schematic diagram of the semiconductor device according to the first embodiment of the present invention. Figures 2(a) and 2(b) are along... Figure 1 The cross-sectional view of line AA in Figure 2(a) shows that the structure of the first nanowire heterojunction is different. Figure 2(c) is a schematic diagram of the first nanowire heterojunction in Figure 2(a) surrounded by a first anti-scattering layer. Figure 3 It is to remove Figure 1 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate.

[0099] Reference Figures 1 to 3 As shown, semiconductor device 1 includes:

[0100] The substrate 10 includes a first region 10a, and a second region 10b and a third region 10c located on both sides of the first region 10a, respectively.

[0101] The first support structure 11 is located on the second region 10b and the third region 10c;

[0102] The first nanowire heterojunction 12 includes a first gate segment 12a corresponding to the first region 10a, a first source segment 12b corresponding to the second region 10b, and a first drain segment 12c corresponding to the third region 10c; the first source segment 12b and the first drain segment 12c are located on the first support structure 11.

[0103] The source 13b is located on the first source region 12b, the drain 13c is located on the first drain region 12c, and the annular gate 13a covers the first gate region 12a.

[0104] In this embodiment, the substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), diamond, or lithium niobate.

[0105] A buffer layer may be present on the substrate 10. A nucleation layer may be present between the buffer layer and the substrate 10. The material of the nucleation layer may be a group III nitride-based material, such as AlN, AlGaN, etc. The material of the buffer layer may also be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer and the substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, such as the first support structure 11, and improve the crystal quality.

[0106] The material of the first support structure 11 can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN and AlInGaN, or it can be a dielectric material, such as silicon dioxide.

[0107] Reference Figure 3 As shown, the length dimension of the first nanowire heterostructure 12 is much larger than its two-dimensional dimension on the vertical cross-section. The vertical cross-section is a cross-section along the thickness direction.

[0108] Referring to FIG2(a), in one embodiment, the first nanowire heterojunction 12 may include a first channel layer 121 and a first barrier layer 122 from bottom to top. A two-dimensional electron gas or a two-dimensional hole gas may be formed at the interface between the first channel layer 121 and the first barrier layer 122. In one alternative embodiment, the first channel layer 121 is an intrinsic GaN layer and the first barrier layer 122 is an N-type AlGaN layer. In other alternative embodiments, the materials of the first channel layer 121 and the first barrier layer 122 may also be at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. In addition, besides the first channel layer 121 and the first barrier layer 122 each having one layer as shown in FIG2(a), the first channel layer 121 and the first barrier layer 122 may each have multiple layers, which are alternately distributed; or one first channel layer 121 and two or more first barrier layers 122 to form a multi-barrier structure.

[0109] Referring to Figure 2(b), in one embodiment, the first nanowire heterojunction 12 may also include, from bottom to top, a first back barrier layer 123, a first channel layer 121, and a first barrier layer 122. The first back barrier layer 123, the first channel layer 121, and the first barrier layer 122 may each have one layer; or the first back barrier layer 123, the first channel layer 121, and the first barrier layer 122 may each have multiple layers, and these layers may be alternately distributed. Compared to the embodiment shown in Figure 2(a), the advantage of this embodiment is that the first back barrier layer 123 and the first barrier layer 122 can confine charge carriers within the first channel layer 121, preventing charge carrier leakage. In other embodiments, the first nanowire heterojunction 12 may also include only the first back barrier layer 123 and the first channel layer 121 from bottom to top.

[0110] Referring to Figure 2(c), in one embodiment, the first nanowire heterojunction 12 shown in Figure 2(a) is surrounded by a first anti-scattering layer 141. In other embodiments, the first anti-scattering layer 141 may also surround the first nanowire heterojunction 12 shown in Figure 2(b). The first anti-scattering layer 141 can reduce the scattering of charge carriers on the outer surface of the first nanowire heterojunction 12 and prevent charge carrier leakage.

[0111] The first anti-scattering layer 141 may consist of an AlN layer and an AlGaN layer from the inside out.

[0112] In this embodiment, there are three first nanowire heterojunctions 12. In other embodiments, the first nanowire heterojunction 12 can also be one, two, or other numbers.

[0113] In some embodiments, each of the first nanowire heterojunctions 12 may share a first source segment 12b and / or a first drain segment 12c. That is, the first source segments 12b of each of the first nanowire heterojunctions 12 are connected together, and / or the first drain segments 12c of each of the first nanowire heterojunctions 12 are connected together.

[0114] Ohmic contacts are formed between the source 13b and the first source segment 12b, between the drain 13c and the first drain segment 12c, and between the ring gate 13a and the first gate segment 12a. The source 13b, drain 13c, and ring gate 13a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au.

[0115] In some embodiments, ohmic contacts can be formed between the source 13b and the first source segment 12b, between the drain 13c and the first drain segment 12c, and between the ring gate 13a and the first gate segment 12a using N-type ion heavily doped layers. The N-type ion heavily doped layers enable the direct formation of ohmic contact layers between the source 13b and the first source segment 12b, between the drain 13c and the first drain segment 12c, and between the ring gate 13a and the first gate segment 12a without high-temperature annealing. This also avoids the performance degradation and reduced electron migration rate of the first nanowire heterojunction 12 caused by the high temperatures during the annealing process.

[0116] In the N-type ion heavily doped layer, the N-type ion can be at least one of Si ions, Ge ions, Sn ions, Se ions, and Te ions. For different N-type ions, the doping concentration can be greater than 1E18 / cm3. The N-type ion heavily doped layer can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0117] In semiconductor device 1, because the first nanowire heterojunction 12 is confined, the two-dimensional electron gas carriers or two-dimensional hole gas carriers within the heterojunction 12 exhibit an approximately one-dimensional transport mode during migration, which can improve carrier mobility. Furthermore, the ring gate 13a's control over carriers is also greatly improved, thus significantly increasing the device's breakdown voltage and reducing leakage current, and improving the efficiency and linearity of the radio frequency device.

[0118] The first embodiment of the present invention also provides Figures 1 to 2(c) Methods for fabricating semiconductor devices. Figure 4 It is a flowchart of the production method. Figures 5 to 8(b) yes Figure 4 The diagram shows the intermediate structure corresponding to the process flow.

[0119] First, refer to Figure 4 Step S1 and Figure 5 As shown, a substrate 10 is provided, the substrate 10 including a first region 10a, and a second region 10b and a third region 10c located on both sides of the first region 10a respectively; a first support structure 11 is formed on the second region 10b and the third region 10c; a first sacrificial layer 17 is formed on the substrate 10 exposed by the first support structure 11.

[0120] In this embodiment, the substrate 10 can be made of materials such as sapphire, silicon carbide, silicon, silicon-on-insulator (SOI), diamond, or lithium niobate.

[0121] Before forming the first support structure 11, a nucleation layer and a buffer layer can be grown sequentially on the substrate 10. The nucleation layer can be a group III nitride-based material, such as AlN or AlGaN. The buffer layer can also be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The nucleation layer can alleviate the problems of lattice mismatch and thermal mismatch between the epitaxially grown semiconductor layer and the substrate 10, while the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer, such as the first support structure 11, thereby improving crystal quality.

[0122] The epitaxial growth process of the nucleation layer and / or buffer layer may include: atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD), or combinations thereof.

[0123] In this embodiment, forming the first support structure 11 specifically includes: referring to Figure 6 As shown, a first epitaxial layer 11' is grown on substrate 10; refer to Figure 5 As shown, the first epitaxial layer 11' is graphically represented, and the first epitaxial layer 11' is retained on the second region 10b and the third region 10c to form the first support structure 11.

[0124] The material of the first epitaxial layer 11' can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The patterned first epitaxial layer 11' can be achieved by dry etching or wet etching.

[0125] In other embodiments, the first epitaxial layer 11' can also be replaced by a first material layer, the material of which is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., and is formed by physical vapor deposition or chemical vapor deposition.

[0126] In other embodiments, forming the first support structure 11 may further include: forming a first patterned mask layer on the substrate 10, the first patterned mask layer having a first opening that exposes the second region 10b and the third region 10c; using the first patterned mask layer as a mask, epitaxially growing the first support structure 11 on the substrate 10. Afterwards, the first patterned mask layer is removed.

[0127] The material of the first patterned mask layer is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., and is formed by physical vapor deposition or chemical vapor deposition.

[0128] The material of the first support structure 11 can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0129] In this embodiment, forming the first sacrificial layer 17 specifically includes: growing the first sacrificial layer 17 on the first support structure 11 and the substrate 10 exposed by the first support structure 11, and removing the first sacrificial layer 17 on the first support structure 11.

[0130] The material of the first sacrificial layer 17 can be a GaN-based material, such as N-type GaN. The epitaxial growth process of the first sacrificial layer 17 can refer to the epitaxial growth process of the nucleation layer and / or buffer layer. The first sacrificial layer 17 on the first support structure 11 can be removed by dry etching or wet etching.

[0131] In other embodiments, the material of the first sacrificial layer 17 may also be, for example, silicon nitride, silicon dioxide, etc., and is formed by physical vapor deposition or chemical vapor deposition.

[0132] In other embodiments, forming the first sacrificial layer 17 may specifically include growing the first sacrificial layer 17 on the substrate 10 using the first support structure 11 as a mask. This embodiment is applicable when the material of the first support structure 11 is silicon nitride, silicon dioxide, etc., and the first sacrificial layer 17 cannot be grown on it.

[0133] Reference Figure 5As shown, in this embodiment, the first sacrificial layer 17 on the substrate 10 is flush with the upper surface of the first support structure 11. In other embodiments, the upper surface of the first sacrificial layer 17 on the substrate 10 may be higher than or lower than the upper surface of the first support structure 11.

[0134] Next, refer to Figure 4 As shown in step S2, Figures 7(a) and 7(b), a first nanowire heterojunction 12 is grown on the first support structure 11 and the first sacrificial layer 17. The first nanowire heterojunction 12 includes a first gate segment 12a corresponding to the first region 10a, a first source segment 12b corresponding to the second region 10b, and a first drain segment 12c corresponding to the third region 10c. The first source segment 12b and the first drain segment 12c are located on the first support structure 11, and the first nanowire heterojunction 12 between the first source segment 12b and the first drain segment 12c is located on the first sacrificial layer 17.

[0135] Referring to FIG7(a), in one embodiment, the first nanowire heterojunction 12 may include a first channel layer 121 and a first barrier layer 122 from bottom to top. A two-dimensional electron gas or a two-dimensional hole gas may be formed at the interface between the first channel layer 121 and the first barrier layer 122. In one alternative embodiment, the first channel layer 121 is an intrinsic GaN layer and the first barrier layer 122 is an N-type AlGaN layer. In other alternative embodiments, the materials of the first channel layer 121 and the first barrier layer 122 may also be at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. In addition, besides the first channel layer 121 and the first barrier layer 122 each having one layer as shown in FIG7(a), the first channel layer 121 and the first barrier layer 122 may each have multiple layers, which are alternately distributed; or one first channel layer 121 and two or more first barrier layers 122 to form a multi-barrier structure.

[0136] Referring to FIG7(b), in one embodiment, the first nanowire heterojunction 12 may also include a first back barrier layer 123, a first channel layer 121, and a first barrier layer 122 from bottom to top. The first back barrier layer 123, the first channel layer 121, and the first barrier layer 122 may each have one layer; or the first back barrier layer 123, the first channel layer 121, and the first barrier layer 122 may each have multiple layers, and these layers may be alternately distributed. Compared to the embodiment shown in FIG7(a), the advantage of this embodiment is that the first back barrier layer 123 and the first barrier layer 122 can confine charge carriers within the first channel layer 121, preventing charge carrier leakage. In other embodiments, the first nanowire heterojunction 12 may also include only the first back barrier layer 123 and the first channel layer 121 from bottom to top.

[0137] The following steps will be described using the structure shown in Figure 7(a).

[0138] The epitaxial growth process of the first nanowire heterojunction 12 can refer to the epitaxial growth process of the nucleation layer and / or buffer layer.

[0139] In this embodiment, refer to Figure 3 As shown, there are three first nanowire heterojunctions 12. In other embodiments, the first nanowire heterojunction 12 can also be one, two, or other numbers.

[0140] Then, refer to Figure 4 Step S3, Figure 8(a) and Figure 3 As shown, the first sacrificial layer 17 is removed, and the first nanowire heterojunction 12 is suspended.

[0141] When the material of the first sacrificial layer 17 is N-type GaN, the removal method is wet solution etching, such as boric acid.

[0142] In some embodiments, the material of the first sacrificial layer 17 can be a GaN-based material, and its upper surface is an N-face. The material of the first nanowire heterojunction 12 can also be a GaN-based material, and its upper surface is a Ga-face. The etching solution used for wet etching can be an H3PO4 solution or a KOH solution, which is corrosive on the N-face and non-corrosive on the Ga-face. The GaN crystal has a wurtzite structure, in which the Ga and N atomic layers are stacked in an ABABAB hexagonal layer, and each Ga(N) atom is bonded to the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. Taking the Ga-N bond parallel to the C-axis (

[0001] crystal orientation) as a reference, if the Ga atom in each Ga-N bond is further away from the lower surface, the upper surface is a Ga-face; if the N atom in each Ga-N bond is further away from the lower surface, the upper surface is an N-face. In this embodiment, the first sacrificial layer 17 can be removed by selective etching of the N-face by an H3PO4 solution or a KOH solution.

[0143] When the material of the first sacrificial layer 17 is silicon nitride, it is removed by hot phosphoric acid; when the material of the first sacrificial layer 17 is silicon dioxide, it is removed by hydrofluoric acid.

[0144] Subsequently, in some embodiments, referring to FIG8(b), a first anti-scattering layer 141 may also be coated around the suspended first nanowire heterojunction 12. The first anti-scattering layer 141 can reduce the scattering of charge carriers on the outer surface of the first nanowire heterojunction 12 and prevent charge carrier leakage.

[0145] The first anti-scattering layer 141 may consist of an AlN layer and an AlGaN layer from the inside out.

[0146] The method for forming the first anti-scattering layer 141 can refer to the epitaxial growth process of the nucleation layer and / or buffer layer.

[0147] Next, refer to Figure 4 Step S4 in Figures 1 to 2(c) As shown, a source 13b is formed on the first source region 12b, a drain 13c is formed on the first drain region 12c, and a ring gate 13a is formed covering the first gate region 12a.

[0148] The source electrode 13b, drain electrode 13c, and ring gate 13a can be made of metal, such as existing conductive materials like Ti / Al / Ni / Au and Ni / Au. Correspondingly, they can be formed on the entire surface first using a deposition process, and then patterned using an etching process.

[0149] When the first nanowire heterojunction 12 is surrounded by a first anti-scattering layer 141, the ring gate 13a covers the first anti-scattering layer 141 of the first gate segment 12a.

[0150] In this embodiment, refer to Figure 1 As shown, the annular gates 13a covering each of the first nanowire heterojunctions 12 are connected together and contact the substrate 10.

[0151] In some embodiments, before forming the source 13b, drain 13c, and ring gate 13a, an N-type ion heavily doped layer is first formed on the first source segment 12b, the first drain segment 12c, and the first gate segment 12a. The N-type ion heavily doped layer can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. In the N-type ion heavily doped layer, the N-type ions can be at least one of Si ions, Ge ions, Sn ions, Se ions, and Te ions. For different N-type ions, the doping concentration can be greater than 1E18 / cm³. 3 .

[0152] The N-type ion-doped layer enables the formation of ohmic contact layers between the source 13b and the first source segment 12b, between the drain 13c and the first drain segment 12c, and between the ring gate 13a and the first gate segment 12a without high-temperature annealing. This avoids the performance degradation and reduced electron migration rate of the first nanowire heterojunction 12 caused by the high temperature during the annealing process.

[0153] Figure 9 This is a three-dimensional structural schematic diagram of a semiconductor device according to the second embodiment of the present invention. Figure 10 It is to remove Figure 9 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate.

[0154] Reference Figure 9 and Figure 10As shown, the structure of semiconductor device 2 in Embodiment 2 is largely the same as that of semiconductor device 1 in Embodiment 1, except that a gate insulating layer 14 is provided between the first gate segment 12a and the annular gate 13a. In other words, semiconductor device 2 has a MIS gate, which can reduce gate leakage current.

[0155] Accordingly, the method of fabricating semiconductor device 2 in Embodiment 2 is largely the same as the method of fabricating semiconductor device 1 in Embodiment 1, except that: in step S4, a gate insulating layer 14 is first coated on the first gate segment 12a; then an annular gate 13a is coated on the gate insulating layer 14.

[0156] Specifically, an insulating material layer and a metal layer can be formed sequentially using a deposition process, and then patterned in one process using an etching process.

[0157] Figure 11 This is a three-dimensional structural diagram of a semiconductor device according to the third embodiment of the present invention.

[0158] Reference Figure 11 As shown, the structure of semiconductor device 3 in Embodiment 3 is roughly the same as that of semiconductor devices 1 and 2 in Embodiments 1 and 2, except that the annular gates 13a covering each first nanowire heterojunction 12 are separated from each other.

[0159] Accordingly, the fabrication method of semiconductor device 3 in Embodiment 3 is roughly the same as the fabrication method of semiconductor devices 1 and 2 in Embodiments 1 and 2, the only difference being that: in step S4, when the etching process patterns the metal layer, not only is the metal layer between the first source segment 12b and the first gate segment 12a, and between the first drain segment 12c and the first gate segment 12a removed, but the metal layer between each of the first nanowire heterojunctions 12 is also broken.

[0160] Figure 12 This is a three-dimensional structural diagram of a semiconductor device according to the fourth embodiment of the present invention.

[0161] Reference Figure 12 As shown, the structure of semiconductor device 4 in Embodiment 4 is roughly the same as that of semiconductor devices 1, 2, and 3 in Embodiments 1, 2, and 3, except that there is a gap between the ring gate 13a and the substrate 10.

[0162] Accordingly, the method of fabricating semiconductor device 4 in Embodiment 4 is roughly the same as the method of fabricating semiconductor devices 1, 2, and 3 in Embodiments 1, 2, and 3, except that in step S4, the thickness of the metal layer deposited in the first gate segment 12a is reduced.

[0163] Figure 13This is a three-dimensional structural schematic diagram of a semiconductor device according to the fifth embodiment of the present invention. Figures 14(a) and 14(b) are along... Figure 13 The cross-sectional view of the BB line in Figure 14(a) shows that the structure of the second nanowire heterojunction is different. Figure 14(c) is a schematic diagram of the second nanowire heterojunction in Figure 14(a) surrounded by a second antiscattering layer. Figure 15 It is to remove Figure 13 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate. Figure 16 It is to remove Figure 15 A three-dimensional schematic diagram of the semiconductor structure behind the gate insulating layer.

[0164] Reference Figures 13 to 16 As shown, the structure of semiconductor device 5 in Embodiment 5 is largely the same as that of semiconductor device 4 in Embodiment 4, except that semiconductor device 5 further includes:

[0165] The second support structure 15 is located on the first source section 12b and the first drain section 12c;

[0166] The second nanowire heterojunction 16 includes a second gate segment 16a corresponding to the first region 10a, a second source segment 16b corresponding to the second region 10b, and a second drain segment 16c corresponding to the third region 10c; the second source segment 16b and the second drain segment 16c are located on the second support structure 15.

[0167] The shape and size of the second nanowire heterojunction 16 can be the same as those of the first nanowire heterojunction 12.

[0168] The material of the second support structure 15 can be the same as that of the first support structure 11.

[0169] Referring to FIG14(a), in one embodiment, the second nanowire heterojunction 16 may include a second channel layer 161 and a second barrier layer 162 from bottom to top. A two-dimensional electron gas or a two-dimensional hole gas may be formed at the interface between the second channel layer 161 and the second barrier layer 162. In one alternative embodiment, the second channel layer 161 is an intrinsic GaN layer and the second barrier layer 162 is an N-type AlGaN layer. In other alternative embodiments, the materials of the second channel layer 161 and the second barrier layer 162 may also be at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. In addition, besides the second channel layer 161 and the second barrier layer 162 each having one layer as shown in FIG14(a), the second channel layer 161 and the second barrier layer 162 may each have multiple layers, which are alternately distributed; or one second channel layer 161 and two or more second barrier layers 162 to form a multi-barrier structure.

[0170] Referring to FIG14(b), in one embodiment, the second nanowire heterojunction 16 may also include a second back barrier layer 163, a second channel layer 161, and a second barrier layer 162 from bottom to top. The second back barrier layer 163, the second channel layer 161, and the second barrier layer 162 may each have one layer; or the second back barrier layer 163, the second channel layer 161, and the second barrier layer 162 may each have multiple layers, and be alternately distributed. Compared to the embodiment shown in FIG14(a), the advantage of this embodiment is that the second back barrier layer 163 and the second barrier layer 162 can confine charge carriers within the second channel layer 161, preventing charge carrier leakage. In other embodiments, the second nanowire heterojunction 16 may also include only the second back barrier layer 163 and the second channel layer 161 from bottom to top.

[0171] Referring to Figure 14(c), in one embodiment, the second nanowire heterojunction 16 shown in Figure 14(a) is surrounded by a second anti-scattering layer 142. In other embodiments, the second anti-scattering layer 142 may also surround the second nanowire heterojunction 16 shown in Figure 14(b). The second anti-scattering layer 142 can reduce the scattering of charge carriers on the outer surface of the second nanowire heterojunction 16 and prevent charge carrier leakage.

[0172] The second anti-scattering layer 142 may consist of, from the inside out, an AlN layer and an AlGaN layer.

[0173] The annular gate 13a covering each of the first nanowire heterojunctions 12 and the annular gate 13a covering each of the second nanowire heterojunctions 16 are separated from each other. Furthermore, there is a gap between the annular gate 13a covering each of the first nanowire heterojunctions 12 and the substrate 10.

[0174] The fifth embodiment of the present invention also provides Figures 13 to 14(c) Methods for fabricating semiconductor devices. Figure 17 It is a flowchart of the production method. Figures 18 to 20 yes Figure 17 The diagram shows the intermediate structure corresponding to the process flow.

[0175] Reference Figure 17 As shown, the method of manufacturing semiconductor device 5 in Embodiment 5 is roughly the same as the method of manufacturing semiconductor devices 1 and 2 in Embodiments 1 and 2, except that: after step S3, the following steps S31 to S33 are performed.

[0176] Step S31, refer to Figure 18 As shown, a second support structure 15 is formed on the first source region 12b and the first drain region 12c; a second sacrificial layer 18 is formed on the first nanowire heterojunction 12 exposed by the second support structure 15.

[0177] In this embodiment, forming the second support structure 15 specifically includes: referring to Figure 19 As shown, a second epitaxial layer 15' is grown on the first nanowire heterostructure 12; reference Figure 18 As shown, the second epitaxial layer 15' is graphically represented, and the second epitaxial layer 15' on the first source segment 12b and the first drain segment 12c is retained to form the second support structure 15.

[0178] The material of the second epitaxial layer 15' can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The patterned second epitaxial layer 15' can be achieved by dry etching or wet etching.

[0179] In other embodiments, the second epitaxial layer 15' can also be replaced by a second material layer, the material of which is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., and is formed by physical vapor deposition or chemical vapor deposition.

[0180] In other embodiments, forming the second support structure 15 may further include: forming a second patterned mask layer on the first nanowire heterojunction 12, the second patterned mask layer having a second opening that exposes the first source segment 12b and the first drain segment 12c; using the second patterned mask layer as a mask, epitaxially growing the second support structure 15 on the first nanowire heterojunction 12. Afterwards, the first patterned mask layer is removed.

[0181] The material of the second patterned mask layer is, for example, silicon nitride, silicon dioxide, silicon oxynitride, etc., and is formed by physical vapor deposition or chemical vapor deposition.

[0182] The material of the second support structure 15 can be a group III nitride-based material, such as at least one of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN.

[0183] In this embodiment, forming the second sacrificial layer 18 specifically includes: growing the second sacrificial layer 18 on the second support structure 15 and the first nanowire heterojunction 12 exposed on the second support structure 15, and removing the second sacrificial layer 18 on the second support structure 15.

[0184] The material of the second sacrificial layer 18 can be N-type GaN. The epitaxial growth process of the second sacrificial layer 18 can refer to the epitaxial growth process of the nucleation layer and / or buffer layer. The second sacrificial layer 18 on the second support structure 15 can be removed by dry etching or wet etching.

[0185] In other embodiments, the material of the second sacrificial layer 18 may also be, for example, silicon nitride, silicon dioxide, etc., and is formed by physical vapor deposition or chemical vapor deposition.

[0186] In other embodiments, forming the second sacrificial layer 18 may specifically include: growing the second sacrificial layer 18 on the first nanowire heterojunction 12 using the second support structure 15 as a mask. This embodiment is applicable when the material of the second support structure 15 is silicon nitride, silicon dioxide, etc., and the second sacrificial layer 18 cannot be grown on it.

[0187] Reference Figure 18 As shown, in this embodiment, the second sacrificial layer 18 on the first nanowire heterojunction 12 is flush with the upper surface of the second support structure 15. In other embodiments, the upper surface of the second sacrificial layer 18 on the first nanowire heterojunction 12 may be higher than or lower than the upper surface of the second support structure 15.

[0188] Step S32, refer to Figure 20 As shown, a second nanowire heterojunction 16 is grown on the second support structure 15 and the second sacrificial layer 18. The second nanowire heterojunction 16 includes a second gate segment 16a corresponding to the first region 10a, a second source segment 16b corresponding to the second region 10b, and a second drain segment 16c corresponding to the third region 10c. The second source segment 16b and the second drain segment 16c are located on the second support structure 15, and the second nanowire heterojunction 16 between the second source segment 16b and the second drain segment 16c is located on the second sacrificial layer 18.

[0189] The epitaxial growth process of the second nanowire heterojunction 16 can refer to the epitaxial growth process of the nucleation layer and / or buffer layer.

[0190] In some embodiments, each of the second nanowire heterojunctions 16 may share a second source segment 16b and / or a second drain segment 16c. That is, the second source segments 16b of each of the second nanowire heterojunctions 16 are connected together, and / or the second drain segments 16c of each of the second nanowire heterojunctions 16 are connected together.

[0191] Step S33, refer to Figure 16 As shown, the second sacrificial layer 18 is removed, and the second nanowire heterojunction 16 is suspended.

[0192] When the material of the second sacrificial layer 18 is N-type GaN, the removal method is wet solution etching, such as boric acid.

[0193] In some embodiments, the material of the second sacrificial layer 18 can be a GaN-based material, and its upper surface is an N-face. The material of the second nanowire heterojunction 16 can also be a GaN-based material, and its upper surface is a Ga-face. The etching solution used for wet etching can be an H3PO4 solution or a KOH solution, which is corrosive on the N-face and non-corrosive on the Ga-face. The GaN crystal has a wurtzite structure, in which the Ga and N atomic layers are stacked in an ABABAB hexagonal layer, and each Ga(N) atom is bonded to the surrounding 4 N(Ga) atoms in a diamond-like tetrahedral structure. Taking the Ga-N bond parallel to the C-axis (

[0001] crystal direction) as a reference, if the Ga atom in each Ga-N bond is further away from the lower surface, the upper surface is a Ga-face; if the N atom in each Ga-N bond is further away from the lower surface, the upper surface is an N-face. In this embodiment, the second sacrificial layer 18 can be removed by selective etching of the N-face by an H3PO4 solution or a KOH solution.

[0194] When the material of the second sacrificial layer 18 is silicon nitride, it is removed by hot phosphoric acid; when the material of the second sacrificial layer 18 is silicon dioxide, it is removed by hydrofluoric acid.

[0195] In step S4', a source electrode 13b is formed on the first source electrode segment 12b and the second source electrode segment 16b, a drain electrode 13c is formed on the first drain electrode segment 12c and the second drain electrode segment 16c, and a ring gate 13a is formed covering the first gate segment 12a and the second gate segment 16a. The ring gate 13a covering each of the first nanowire heterojunctions 12 and the ring gate 13a covering each of the second nanowire heterojunctions 16 are separate from each other.

[0196] Figure 21 This is a three-dimensional structural diagram of a semiconductor device according to the sixth embodiment of the present invention.

[0197] Reference Figure 21 As shown, the semiconductor device 6 and its fabrication method in Embodiment Six are largely the same as those in Embodiment Five, except that the ring gate 13a is covered by each of the first nanowire heterojunctions 12 and each of the second nanowire heterojunctions 16.

[0198] In other embodiments, the ring gate 13a may cover a second nanowire heterojunction 16 and a first nanowire heterojunction 12 directly below the second nanowire heterojunction 16. In other words, the vertical cross-section of the ring gate 13a is figure-eight shaped.

[0199] Figure 22 This is a three-dimensional structural schematic diagram of a semiconductor device according to the seventh embodiment of the present invention.

[0200] Reference Figure 22As shown, the semiconductor device 7 and its fabrication method in Embodiment 7 are largely the same as those in Embodiment 6, except that the annular gate 13a contacts the substrate 10.

[0201] Figure 23 This is a three-dimensional structural schematic diagram of the semiconductor device according to the eighth embodiment of the present invention. Figure 24 It is to remove Figure 23 A three-dimensional schematic diagram of the semiconductor structure behind the source, drain, and ring gate. Figure 25 It is to remove Figure 24 A three-dimensional schematic diagram of the semiconductor structure behind the gate insulating layer.

[0202] Reference Figures 23 to 25 As shown, the semiconductor device 8 and its fabrication method in Embodiment 8 are largely the same as those in Embodiments 1 and 2, except that: the substrate 10 further includes a fourth region 10d located between the first region 10a and the second region 10b, and a fifth region 10e located between the first region 10a and the third region 10c; the first support structure 11 is located on the second region 10b and the fourth region 10d, and on the third region 10c and the fifth region 10e.

[0203] It can be seen that the suspended section of the first nanowire heterojunction 12 of semiconductor device 8 is shorter than the suspended section of the first nanowire heterojunction 12 of semiconductor devices 1 and 2.

[0204] In some embodiments, the semiconductor device 8 of embodiment eight can be combined with the semiconductor devices 5, 6, and 7 of embodiments five, six, and seven. The second support structure 15 can be located on the second region 10b and the fourth region 10d, and on the third region 10c and the fifth region 10e, or it can be located on the second region 10b and the third region 10c.

[0205] Figure 26 This is a three-dimensional structural schematic diagram of a semiconductor device according to the ninth embodiment of the present invention. (Refer to...) Figure 26 As shown, the semiconductor device 9 and its fabrication method in Embodiment 9 are largely the same as those in Embodiment 8, except that the annular gates 13a covering each of the first nanowire heterojunctions 12 are separated from each other, and / or the gate insulating layer 14 is omitted.

[0206] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate (10) includes a first region (10a) and a second region (10b) and a third region (10c) located on both sides of the first region (10a). A first support structure (11) located at least in the second region (10b) and the third region (10c). A first nanowire heterojunction (12) includes a first gate segment (12a) corresponding to the first region (10a), a first source segment (12b) corresponding to the second region (10b), and a first drain segment (12c) corresponding to the third region (10c); the first source segment (12b) and the first drain segment (12c) are located on the first support structure (11); The source (13b) is located on the first source section (12b), the drain (13c) is located on the first drain section (12c), and the ring gate (13a) covers the first gate section (12a). The first nanowire heterojunction (12) is surrounded by a first anti-scattering layer (141). The first nanowire heterojunction (12) includes, from bottom to top: a first channel layer (121) and a first barrier layer (122), or includes: a first back barrier layer (123), a first channel layer (121) and a first barrier layer (122).

2. The semiconductor device according to claim 1, characterized in that, The first support structure (11) is located only on the second region (10b) and the third region (10c); Alternatively, the substrate (10) may further include a fourth region (10d) located between the first region (10a) and the second region (10b), and a fifth region (10e) located between the first region (10a) and the third region (10c); the first support structure (11) is located on the second region (10b) and the fourth region (10d), and on the third region (10c) and the fifth region (10e).

3. The semiconductor device according to claim 1, characterized in that, A gate insulating layer (14) is provided between the first gate segment (12a) and the annular gate (13a).

4. The semiconductor device according to claim 1, characterized in that, The first nanowire heterojunction (12) has multiple nanowires.

5. The semiconductor device according to claim 4, characterized in that, Each of the first nanowire heterojunctions (12) shares the first source segment (12b) and / or the first drain segment (12c).

6. The semiconductor device according to claim 4 or 5, characterized in that, The annular gates (13a) covering each of the first nanowire heterojunctions (12) are separated from each other, or the annular gates (13a) covering each of the first nanowire heterojunctions (12) are connected together.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A second support structure (15) is located at least on the first source section (12b) and the first drain section (12c). The second nanowire heterojunction (16) includes a second gate segment (16a) corresponding to the first region (10a), a second source segment (16b) corresponding to the second region (10b), and a second drain segment (16c) corresponding to the third region (10c); the second source segment (16b) and the second drain segment (16c) are located on the second support structure (15).

8. The semiconductor device according to claim 7, characterized in that, The second nanowire heterostructure (16) has multiple nanowires.

9. The semiconductor device according to claim 8, characterized in that, Each of the second nanowire heterojunctions (16) shares the second source segment (16b) and / or the second drain segment (16c).

10. The semiconductor device according to claim 9, characterized in that, The ring gate (13a) covers a second nanowire heterojunction (16) and the first nanowire heterojunction (12) directly below the second nanowire heterojunction (16).

11. A method for fabricating a semiconductor device, characterized in that, include: A substrate (10) is provided, the substrate (10) including a first region (10a), and a second region (10b) and a third region (10c) located on both sides of the first region (10a); a first support structure (11) is formed on at least the second region (10b) and the third region (10c); a first sacrificial layer (17) is formed on the substrate (10) exposed by the first support structure (11). A first nanowire heterojunction (12) is grown on the first support structure (11) and the first sacrificial layer (17). The first nanowire heterojunction (12) includes a first gate segment (12a) corresponding to the first region (10a), a first source segment (12b) corresponding to the second region (10b), and a first drain segment (12c) corresponding to the third region (10c). The first source segment (12b) and the first drain segment (12c) are located on the first support structure (11), and at least the first gate segment (12a) is located on the first sacrificial layer (17). Remove the first sacrificial layer (17) to suspend the first nanowire heterostructure (12); A first anti-scattering layer (141) is wrapped around the suspended first nanowire heterojunction (12). A source (13b) is formed on the first source segment (12b), a drain (13c) is formed on the first drain segment (12c), and a ring gate (13a) is formed covering the first gate segment (12a). The first nanowire heterojunction (12) includes, from bottom to top: a first channel layer (121) and a first barrier layer (122), or includes: a first back barrier layer (123), a first channel layer (121) and a first barrier layer (122).

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The first support structure (11) is located only on the second region (10b) and the third region (10c); after removing the first sacrificial layer (17), the suspended first nanowire heterojunction (12) extends from the first source section (12b) to the first drain section (12c). Alternatively, the substrate (10) may further include a fourth region (10d) located between the first region (10a) and the second region (10b), and a fifth region (10e) located between the first region (10a) and the third region (10c); the first support structure (11) is located on the second region (10b) and the fourth region (10d), and on the third region (10c) and the fifth region (10e); after removing the first sacrificial layer (17), the suspended first nanowire heterojunction (12) is only the first gate segment (12a).

13. The method for fabricating a semiconductor device according to claim 11, characterized in that, Before forming the annular gate (13a), a gate insulating layer (14) is coated on the first gate segment (12a); the annular gate (13a) is coated with the gate insulating layer (14).

14. The method for fabricating a semiconductor device according to claim 11, characterized in that, The first nanowire heterojunction (12) grown consists of multiple nanowires.

15. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the first support structure (11) includes: growing a first epitaxial layer (11') on the substrate (10); patterning the first epitaxial layer (11') and retaining at least the first epitaxial layer (11') on the second region (10b) and the third region (10c) to form the first support structure (11). Alternatively, it may include: forming a first patterned mask layer on the substrate (10), the first patterned mask layer having a first opening, the first opening exposing at least the second region (10b) and the third region (10c); using the first patterned mask layer as a mask, epitaxially growing the first support structure (11) on the substrate (10).

16. The method for fabricating a semiconductor device according to claim 11, characterized in that, The formation of the first sacrificial layer (17) includes: growing the first sacrificial layer (17) on the first support structure (11) and the substrate (10) exposed by the first support structure (11), and removing the first sacrificial layer (17) on the first support structure (11). Or it may include: growing the first sacrificial layer (17) on the substrate (10) using the first support structure (11) as a mask.

17. The method for fabricating a semiconductor device according to claim 11, characterized in that, Also includes: A second support structure (15) is formed at least on the first source section (12b) and the first drain section (12c). A second sacrificial layer (18) is formed on the first nanowire heterojunction (12) exposed by the second support structure (15). A second nanowire heterojunction (16) is grown on the second support structure (15) and the second sacrificial layer (18). The second nanowire heterojunction (16) includes a second gate segment (16a) corresponding to the first region (10a), a second source segment (16b) corresponding to the second region (10b), and a second drain segment (16c) corresponding to the third region (10c). The second source segment (16b) and the second drain segment (16c) are located on the second support structure (15), and at least the second gate segment (16a) is located on the second sacrificial layer (18). Remove the second sacrificial layer (18) and suspend the second nanowire heterojunction (16).

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, The formation of the second support structure (15) includes: growing a second epitaxial layer (15') on the first nanowire heterojunction (12); patterning the second epitaxial layer (15') and retaining at least the second epitaxial layer (15') on the first source section (12b) and the first drain section (12c) to form the second support structure (15); Alternatively, it may include: forming a second patterned mask layer on the first nanowire heterojunction (12), the second patterned mask layer having a second opening, the second opening exposing at least the first source segment (12b) and the first drain segment (12c); using the second patterned mask layer as a mask, epitaxially growing the second support structure (15) on the first nanowire heterojunction (12).

19. The method for fabricating a semiconductor device according to claim 17, characterized in that, Forming the second sacrificial layer (18) includes: growing the second sacrificial layer (18) on the second support structure (15) and the first nanowire heterojunction (12) exposed by the second support structure (15), and removing the second sacrificial layer (18) on the second support structure (15). Or it may include: using the second support structure (15) as a mask, growing a second sacrificial layer (18) on the first nanowire heterostructure (12).

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