Transverse variable doping high-voltage LDMOS and manufacturing method thereof

Abstract

This invention provides a laterally variable doped high-voltage LDMOS and its fabrication method. The method includes the following steps: forming a drift region, a body region, a drain, a source, and a gate based on a substrate. The gate includes a main gate and a dummy gate. The main gate spans between the drift region and the body region, and the dummy gate is located on the drift region and between the main gate and the drain. The dummy gate has multiple ion implantation windows arranged sequentially in the direction from the main gate to the drain, with the spacing decreasing sequentially or intermittently. Ion implantation is performed on the drift region based on the dummy gate, followed by annealing to form a doped region in the drift region with a gradually increasing doping concentration in the direction from the main gate to the drain. The laterally variable doped high-voltage LDMOS of this invention achieves a gradual decrease in the doping concentration from the drain to the source drift region through ion implantation, thereby increasing the overall concentration and effectively reducing the on-resistance. Simultaneously, combined with field plate technology, it can effectively improve the breakdown voltage of the device. The process steps are simple and easily controlled precisely.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a lateral variable doping high voltage LDMOS and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) transistors are widely used due to their excellent performance in key device characteristics and easy compatibility with complementary metal-oxide-semiconductor (CMOS) processes. In LDMOS transistor devices, breakdown voltage and on-resistance are the two most important performance parameters, and their limitations currently hinder further improvements in LDMOS transistor performance.

[0003] In existing technologies, the electric field in the source and drain regions during channel turn-on can be reduced by using field plate technology, thereby improving the breakdown voltage. The specific process involves first forming the drain drift region and the source body region, then forming the gate, followed by source and drain doping, and finally forming the field plate to complete the LDMOS device structure. Please refer to [link to relevant documentation]. Figure 1 The image shows a schematic diagram of an existing LDMOS structure with a self-aligned silicide barrier (SAB) type field plate. However, this field plate structure mainly relies on the drain drift region to achieve high breakdown voltage, but the drift region uses low-concentration ion implantation, which comes at the cost of increased device on-resistance and loss of on-current.

[0004] Therefore, how to provide an LDMOS that can improve the breakdown voltage without increasing the on-resistance of the device and causing current loss, and achieve simple and precise process control, has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a simple and easily precisely controllable lateral doped high-voltage LDMOS and its fabrication method, which solves the problem of current loss caused by increasing the on-resistance when using field plate technology to improve the breakdown voltage of LDMOS.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a lateral variable-doped high-voltage LDMOS, comprising the following steps:

[0008] Provide a substrate;

[0009] A drift region, a body region, a drain, a source, and a gate are formed on the substrate. The drift region and the body region are both located in the substrate and are spaced apart. The drain is located in the off-drift region, the source is located in the body region, and the gate is located on the substrate. The gate includes a main gate and a dummy gate. The main gate spans between the drift region and the body region, with one end extending above the drift region and the other end extending above the source. The dummy gate is located on the drift region and between the main gate and the drain. The dummy gate has multiple ion implantation windows, which are arranged sequentially in the direction from the main gate to the drain, with the spacing decreasing sequentially or intermittently.

[0010] Ion implantation and annealing are performed on the drift region based on the virtual gate to form a doped region in the drift region, wherein the doping concentration of the doped region gradually increases in the direction from the main gate to the drain.

[0011] Optionally, the method further includes the step of forming a field plate on the upper surface of the dummy gate, the field plate further filling the ion implantation window.

[0012] Optionally, the field plate also extends to the upper surface of the main gate.

[0013] Optionally, the drain is connected to the doped region.

[0014] Optionally, the virtual gate is divided by a plurality of ion implantation windows into a first virtual portion, a second virtual portion, and a third virtual portion arranged sequentially along the direction from the main gate to the drain, wherein the width of the first virtual portion is greater than the width of the second virtual portion, and the width of the second virtual portion is greater than the width of the third virtual portion.

[0015] Optionally, the virtual gate includes one or more first virtual portions of the same width, the virtual gate includes one or more second virtual portions of the same width, and the virtual gate includes one or more third virtual portions of the same width.

[0016] Optionally, the drift region, the drain, the source, and the doped region are all of the first conductivity type, and the body region is of the second conductivity type opposite to the first conductivity type. The first conductivity type is P-type or N-type.

[0017] Optionally, the energy range of the ion implantation is 20 keV to 800 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 13 cm -2 ~1×10 15 cm -2 .

[0018] The present invention also provides a lateral variable doped high voltage LDMOS, comprising:

[0019] Substrate;

[0020] The substrate includes a drift region, a body region, a drain, a source, and a gate. The drift region and the body region are located in the substrate and are spaced apart. The drain is located in the off-drift region, the source is located in the body region, and the gate is located on the substrate. The gate includes a main gate and a dummy gate. The main gate spans between the drift region and the body region, with one end extending above the drift region and the other end extending above the source. The dummy gate is located on the drift region and between the main gate and the drain. The dummy gate has multiple ion implantation windows, which are arranged sequentially in the direction from the main gate to the drain, with the spacing decreasing sequentially or intermittently.

[0021] The doped region is located in the drift region and in the region where the virtual gate is located. The doping concentration of the doped region gradually increases in the direction from the main gate to the drain.

[0022] Optionally, it also includes a field plate located on the upper surface of the dummy gate and filling the ion implantation window.

[0023] Optionally, the field plate also extends to the upper surface of the main gate.

[0024] Optionally, the virtual gate is divided by a plurality of ion implantation windows into a first virtual portion, a second virtual portion, and a third virtual portion arranged sequentially along the direction from the main gate to the drain, wherein the width of the first virtual portion is greater than the width of the second virtual portion, and the width of the second virtual portion is greater than the width of the third virtual portion.

[0025] Optionally, the virtual gate includes one or more first virtual portions of the same width, the virtual gate includes one or more second virtual portions of the same width, and the virtual gate includes one or more third virtual portions of the same width.

[0026] Optionally, the width ratio between the first virtual part and the second virtual part is in the range of 2 to 10, and the width ratio between the first virtual part and the third virtual part is in the range of 5 to 20.

[0027] As described above, the fabrication method of the laterally variable doped high-voltage LDMOS of the present invention includes the following steps: providing a substrate, forming a drift region, a body region, a drain, a source, and a gate based on the substrate, the gate including a main gate and a dummy gate, the main gate spanning between the drift region and the body region, the dummy gate located on the drift region and between the main gate and the drain, the dummy gate having multiple ion implantation windows arranged sequentially in the direction from the main gate to the drain with decreasing spacing; performing ion implantation into the drift region based on the dummy gate and annealing to form a doped region in the drift region with a gradually increasing doping concentration in the direction from the main gate to the drain. The laterally variable doped high-voltage LDMOS of the present invention achieves a gradual decrease in the concentration of the drift region from the drain to the source by ion implantation based on the dummy gate with multiple ion implantation windows, thereby increasing the overall concentration, effectively reducing the on-resistance, and, combined with field plate technology, effectively improving the breakdown voltage of the device, the process steps are simple and easy to control precisely. Attached Figure Description

[0028] Figure 1 The diagram shows a schematic of an nLDMOS structure with an SAB-type field plate in the prior art.

[0029] Figure 2 The diagram shows the steps of the fabrication method of the lateral variable doped high voltage LDMOS of the present invention in Embodiment 1.

[0030] Figure 3 The diagram shown is a structural schematic of step S1 in Example 1 of the fabrication method of the lateral variable doped high voltage LDMOS of the present invention.

[0031] Figure 4 The diagram shown is a schematic representation of the structure presented in step S2 of Embodiment 1 of the fabrication method of the lateral variable doped high voltage LDMOS of the present invention.

[0032] Figure 5 Displayed as Figure 4 A magnified structural diagram of local region I in the middle.

[0033] Figure 6 The diagram shown is a schematic representation of the structure presented in step S3 of Example 1 of the fabrication method of the lateral variable doped high voltage LDMOS of the present invention.

[0034] Figure 7 The diagram shows a schematic representation of the formation of the field plate in Embodiment 1 of the fabrication method of the laterally doped high-voltage LDMOS of the present invention, and also shows a schematic representation of the structure of the laterally doped high-voltage LDMOS of the present invention in Embodiment 2.

[0035] Figure 8 The diagram shows the structure of the lateral variable doped high voltage LDMOS of the present invention when it has STI and metal leads.

[0036] Component designation explanation

[0037] 1 Substrate

[0038] 2 Drift Zone

[0039] 3 body areas

[0040] 4 Drain

[0041] 5 Source poles

[0042] 6 Main gate

[0043] 7 Ion implantation window

[0044] 8 First Virtual Department

[0045] 9 Second Virtual Department

[0046] 10 Third Virtual Department

[0047] 11 Doped Regions

[0048] 12 boards

[0049] 13 Shallow trench isolation structure

[0050] 14 Metal leads

[0051] Steps S1 to S3

[0052] I Local area

[0053] W1 First Spacing

[0054] W2 Second Spacing

[0055] W3 Third Spacing Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 2 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] Example 1

[0059] This embodiment provides a method for fabricating a lateral doped high-voltage LDMOS. Please refer to [link to relevant documentation]. Figure 2 The flowchart shown is a step-by-step diagram of the fabrication method of the lateral variable doped high-voltage LDMOS in this embodiment, including the following steps:

[0060] S1: Provide a substrate;

[0061] S2: A drift region, a body region, a drain, a source, and a gate are formed based on the substrate. The drift region and the body region are both located in the substrate and are spaced apart. The drain is located in the off-drift region, the source is located in the body region, and the gate is located on the substrate. The gate includes a main gate and a dummy gate. The main gate spans between the drift region and the body region, and one end of the main gate extends above the drift region, while the other end extends above the source. The dummy gate is located on the drift region and between the main gate and the drain. The dummy gate has multiple ion implantation windows, which are arranged sequentially in the direction from the main gate to the drain, with the spacing decreasing sequentially or intermittently.

[0062] S3: Ion implantation and annealing are performed on the drift region based on the virtual gate to form a doped region in the drift region, wherein the doping concentration of the doped region gradually increases in the direction from the main gate to the drain.

[0063] First, please refer to Figure 3 Step S1 is performed: a substrate 1 is provided. The substrate 1 can be an N-type substrate or a P-type substrate, which can be selected according to the actual situation. In this embodiment, the substrate 1 is a P-type substrate.

[0064] Please see again Figure 4 Step S2 is performed as follows: a drift region 2, a body region 3, a drain 4, a source 5, and a gate are formed based on the substrate 1. The drift region 2 and the body region 3 are both located in the substrate 1 and are spaced apart. The drain 4 is located in the drift region 2, the source 5 is located in the body region 3, and the gate is located on the substrate 1. The gate includes a main gate 6 and a dummy gate. The main gate 6 spans between the drift region 2 and the body region 3, and one end of the main gate 6 extends above the drift region 2, while the other end of the main gate 6 extends above the source 5. The dummy gate is located on the drift region 2 and between the main gate 6 and the drain 4. The dummy gate has multiple ion implantation windows 7, which are arranged sequentially in the direction from the main gate 6 to the drain 4, and the spacing between them decreases sequentially or intermittently.

[0065] As an example, the drift region 2 and the body region 3 can be formed by ion implantation and push-junction or other suitable methods. The depth, doping concentration, spacing width and other parameters of the drift region 2 and the body region 3 can be set according to actual needs.

[0066] As an example, the drain 4 and the source 5 can be formed by ion implantation and push-in or other suitable methods, wherein the doping concentration of the drain 4 is higher than that of the offset drift region 2, and the doping concentration of the source 5 is higher than that of the body region 3.

[0067] As an example, a gate material layer can be formed on the substrate 1 using chemical vapor deposition, physical vapor deposition, or other suitable methods, and the gate material layer can be patterned using processes such as photolithography and etching to obtain the gate.

[0068] For example, please refer to Figure 5 Displayed as Figure 4 A magnified structural diagram of local region I in this embodiment shows that the plurality of ion implantation windows 7 are of equal size and the spacing between the plurality of ion implantation windows 7 decreases intermittently from the main gate 6 to the drain 4.

[0069] As an example, Figure 5 The diagram shows the first spacing W1, the second spacing W2, and the third spacing W3, and the condition W1 > W2 > W3 is met.

[0070] As an example, the virtual gate is divided by a plurality of ion implantation windows 7 into a first virtual portion 8, a second virtual portion 9 and a third virtual portion 10 arranged sequentially along the direction from the main gate 6 to the drain 4, wherein the width of the first virtual portion 8 is greater than the width of the second virtual portion 9 and the width of the second virtual portion 9 is greater than the width of the third virtual portion 10.

[0071] As an example, the virtual gate includes one or more first virtual portions 8 of the same width, the virtual gate includes one or more second virtual portions 9 of the same width, and the virtual gate includes one or more third virtual portions 10 of the same width, wherein... Figure 4 The present case is that the virtual gate includes two first virtual portions 8 of the same width, two second virtual portions 9 of the same width, and two third virtual portions 10 of the same width.

[0072] Please see again Figure 6 Step S3 is performed, in which ion implantation and annealing are performed on the drift region 2 based on the virtual gate to form a doped region 11 in the drift region 2, wherein the doping concentration of the doped region 11 gradually increases in the direction from the main gate 6 to the drain 4.

[0073] In this embodiment, the first virtual part 8, the second virtual part 9, and the third virtual part 10 can serve as hard masks when forming the doped region 11 by ion implantation. When ion implantation is performed on the drift region 2 based on the virtual gate, only ions above the ion implantation window 7 pass through the ion implantation window and enter the drift region 2, while ions above the first virtual part 8, the second virtual part 9, and the third virtual part 10 fail to enter the drift region. Given that the widths of the first virtual part 8, the second virtual part 9, and the third virtual part 10 are different, and the size of the ion implantation window 7 is the same, the ion concentration in the corresponding regions has a relatively obvious difference. Therefore, by adjusting the spacing of the multiple ion implantation windows in the virtual gate, the ion implantation concentration in the doped region can be precisely controlled. Moreover, after the ion implantation step is completed, it is not necessary to remove the virtual gate, thereby reducing process costs and time and effectively improving production efficiency. In addition, during ion implantation, high-energy incident ions collide with atoms on the semiconductor lattice, causing some lattice atoms to shift and resulting in a large number of vacancies. This will cause the atoms in the implanted region to be arranged randomly or become an amorphous region. Annealing at a certain temperature after ion implantation can restore the crystal structure and eliminate defects. It can also move impurity atoms to lattice points and activate them.

[0074] As an example, the energy range of the ion implantation is 20 keV to 800 keV, and the dose range of the ion implantation is 1 × 10⁻⁶. 13 cm -2 ~1×10 15 cm -2 In practical applications, since the doped region 11 is formed by ion implantation into the drift region 2, the overall ion concentration of the drift region 2 is correspondingly increased, which can effectively reduce the on-resistance of the device and thus improve the device performance. Furthermore, while ensuring performance requirements, the ion concentration of the drift region 2 can be appropriately reduced from the conventional ion concentration.

[0075] As an example, the drift region 2, the drain 4, the source 5, and the doped region all have a first conductivity type, while the body region 3 has a second conductivity type opposite to the first conductivity type. The first conductivity type is either P-type or N-type. In this embodiment, the first conductivity type is N-type, meaning that the drift region 2, the drain 4, the source 5, and the doped region all have N-type conductivity, and the body region 3 has P-type conductivity. In other embodiments, the first conductivity type may also be P-type.

[0076] As an example, the drift region 2, the drain 4, the source 5, and the doped region are formed by N-type or P-type heavy doping (N+ / P+) or N-type or P-type lightly doped drain (NLDD / P Lightly Doped Drain, PLDD) implantation. The doped ions include at least one of N-type P, As, or P-type B, BF2. The doped ions of the body region 3 include P-type B, BF2, or N-type P, As, etc.

[0077] As an example, the drain 4 is connected to the doped region 12, thereby achieving a gradual decrease in the ion concentration of the drift region 2 from the drain 4 to the source 5.

[0078] For example, please refer to Figure 7 The fabrication method of the lateral variable doped high voltage LDMOS provided in this embodiment also includes the following steps: forming a field plate 12 on the upper surface of the virtual gate, and the field plate 12 is also filled into the ion implantation window 8.

[0079] As an example, the field plate 12 may be located only on the upper surface of the dummy gate, or it may selectively extend to the upper surface of the main gate 6. The field plate 12 can effectively reduce the electric field strength of the gate near the drain end, increase the radius of curvature of the curved junction, prevent the surface electric field from being too concentrated, thereby improving the breakdown voltage of the device, and at the same time reducing the probability of electrons in the channel being excited into the surface state by a strong electric field, thereby suppressing the current collapse of the device. In practical applications, the field plate 12 can be formed by chemical vapor deposition (CVD) and plasma-enhanced CVD, or other suitable methods; this is not a mandatory requirement.

[0080] The fabrication method of the laterally doped high-voltage LDMOS in this embodiment is based on ion implantation through a virtual gate with multiple ion implantation windows to achieve a gradual decrease in the concentration of the laterally doped high-voltage LDMOS from the drain to the source drift region, thereby increasing the overall concentration and effectively reducing the on-resistance. At the same time, combined with field plate technology, the breakdown voltage of the device can be effectively improved. The process steps are simple and easy to control precisely.

[0081] Example 2

[0082] This embodiment provides a lateral variable doping high-voltage LDMOS. Please refer to [link / reference]. Figure 7The diagram shows a schematic of the structure of a laterally doped high-voltage LDMOS according to this embodiment, including: a substrate 1, a drift region 2, a body region 3, a drain 4, a source 5, a gate, and a doped region 11; the drift region 2 and the body region 3 are both located in the substrate 1 and are spaced apart, the drain 4 is located in the drift region 2, the source 5 is located in the body region 3, and the gate is located on the substrate 1; the gate includes a main gate 6 and a dummy gate, the main gate 6 spans between the drift region 2 and the body region 3, and one end of the main gate 6 extends to the drift region 1. Above the drift region 2, the other end of the main gate 6 extends above the source 5. The virtual gate is located on the drift region 2 and between the main gate 6 and the drain 4. The virtual gate is provided with a plurality of ion implantation windows 7, which are arranged sequentially in the direction from the main gate 6 to the drain 4 and the spacing decreases sequentially or intermittently. The doped region 11 is located in the drift region 2 and in the region where the virtual gate is located. The doping concentration of the doped region 11 gradually increases in the direction from the main gate 6 to the drain 4.

[0083] As an example, the lateral variable doped high voltage LDMOS provided in this embodiment also includes a field plate 12, which is located on the upper surface of the virtual gate and fills the ion implantation window 7.

[0084] As an example, the field plate 12 may be located only on the upper surface of the virtual gate, or it may selectively extend to the upper surface of the main gate 6.

[0085] As an example, the virtual gate is divided by a plurality of ion implantation windows 7 into a first virtual portion 8, a second virtual portion 9 and a third virtual portion 10 arranged sequentially along the direction from the main gate 6 to the drain 4, wherein the width of the first virtual portion 8 is greater than the width of the second virtual portion 9 and the width of the second virtual portion 9 is greater than the width of the third virtual portion 10.

[0086] As an example, the virtual gate includes one or more first virtual portions 8 of the same width, the virtual gate includes one or more second virtual portions 9 of the same width, and the virtual gate includes one or more third virtual portions 10 of the same width.

[0087] As an example, the width ratio of the first virtual part 8 to the second virtual part 9 is in the range of 2 to 10, and the width ratio of the first virtual part 8 to the third virtual part 10 is in the range of 5 to 20.

[0088] For example, please refer to Figure 8The diagram shows a schematic of the laterally doped high-voltage LDMOS in this embodiment, where a shallow trench isolation (STI) structure 13 is provided. The STI 13 is located within the substrate 1 and is used to reduce leakage current between electrodes and improve breakdown voltage. Furthermore, the laterally doped high-voltage LDMOS in this embodiment also includes metal leads 14, which are connected to the drain 4, source 5, and main gate 6 respectively to electrically lead out the drain 4, source 5, and main gate 6.

[0089] The lateral variable doping high-voltage LDMOS of this embodiment includes a doped region that achieves a gradual decrease in concentration from the drain to the source drift region and an increase in overall concentration, effectively reducing the on-resistance. At the same time, the included field plate structure can effectively improve the breakdown voltage of the device, further improving the device performance.

[0090] In summary, the fabrication method of the laterally doped high-voltage LDMOS of the present invention includes the following steps: providing a substrate, forming a drift region, a body region, a drain, a source, and a gate based on the substrate, the gate including a main gate and a dummy gate, the main gate spanning between the drift region and the body region, the dummy gate located on the drift region and between the main gate and the drain, the dummy gate having multiple ion implantation windows arranged sequentially in the direction from the main gate to the drain with decreasing spacing; performing ion implantation into the drift region based on the dummy gate and annealing to form a doped region in the drift region with a gradually increasing doping concentration in the direction from the main gate to the drain. The laterally doped high-voltage LDMOS of the present invention achieves a gradual decrease in the concentration of the drift region from the drain to the source through ion implantation using a dummy gate with multiple ion implantation windows, thereby increasing the overall concentration and effectively reducing the on-resistance. Simultaneously, combined with field plate technology, it can effectively improve the breakdown voltage of the device. The process steps are simple and easily controlled precisely. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a lateral variable-doped high-voltage LDMOS, characterized in that, Includes the following steps: Provide a substrate; A drift region, a body region, a drain, a source, and a gate are formed on the substrate. The drift region and the body region are both located in the substrate and are spaced apart. The drain is located in the drift region, the source is located in the body region, and the gate is located on the substrate. The gate includes a main gate and a dummy gate. The main gate spans between the drift region and the body region, with one end extending above the drift region and the other end extending above the source. The dummy gate is located on the drift region and between the main gate and the drain. The dummy gate has multiple ion implantation windows, which are arranged sequentially in the direction from the main gate to the drain, with the spacing decreasing sequentially or intermittently. Ion implantation and annealing are performed on the drift region based on the virtual gate to form a doped region in the drift region. The doping concentration of the doped region gradually increases in the direction from the main gate to the drain, and the drain is connected to the doped region. A field plate is formed on the upper surface of the virtual gate, the field plate also fills the ion implantation window, and the field plate also extends to the upper surface of the main gate.

2. The fabrication method of lateral variable doped high-voltage LDMOS according to claim 1, characterized in that: The virtual gate is divided by a plurality of ion implantation windows into a first virtual portion, a second virtual portion, and a third virtual portion arranged sequentially along the direction from the main gate to the drain. The width of the first virtual portion is greater than the width of the second virtual portion, and the width of the second virtual portion is greater than the width of the third virtual portion.

3. The fabrication method of lateral variable doped high-voltage LDMOS according to claim 2, characterized in that: The virtual gate includes one or more first virtual portions of the same width, the virtual gate includes one or more second virtual portions of the same width, and the virtual gate includes one or more third virtual portions of the same width.

4. The method for fabricating a lateral variable-doped high-voltage LDMOS according to claim 1, characterized in that: The drift region, the drain, the source, and the doped region are all of the first conductivity type, and the body region is of the second conductivity type, which is opposite to the first conductivity type. The first conductivity type is either P-type or N-type.

5. The method for fabricating a lateral variable doped high-voltage LDMOS according to claim 1, characterized in that: The energy range of the ion implantation is 20 keV to 800 keV, and the dose range of the ion implantation is 1×10⁻⁶. 13 cm -2 ~1´10 15 cm -2 .

6. A lateral variable-doped high-voltage LDMOS, characterized in that, include: Substrate; The substrate includes a drift region, a body region, a drain, a source, and a gate. The drift region and the body region are located in the substrate and are spaced apart. The drain is located in the drift region, the source is located in the body region, and the gate is located on the substrate. The gate includes a main gate and a dummy gate. The main gate spans between the drift region and the body region, with one end extending above the drift region and the other end extending above the source. The dummy gate is located on the drift region and between the main gate and the drain. The dummy gate has multiple ion implantation windows, which are arranged sequentially in the direction from the main gate to the drain, with the spacing decreasing sequentially or intermittently. A doped region is located in the drift region and in the region where the virtual gate is located. The doping concentration of the doped region gradually increases in the direction from the main gate to the drain, and the drain is connected to the doped region. A field plate is located on the upper surface of the dummy gate and fills the ion implantation window, and the field plate also extends to the upper surface of the main gate.

7. The lateral variable doping high-voltage LDMOS according to claim 6, characterized in that: The virtual gate is divided by a plurality of ion implantation windows into a first virtual portion, a second virtual portion, and a third virtual portion arranged sequentially along the direction from the main gate to the drain. The width of the first virtual portion is greater than the width of the second virtual portion, and the width of the second virtual portion is greater than the width of the third virtual portion.

8. The lateral variable-doped high-voltage LDMOS according to claim 7, characterized in that: The virtual gate includes one or more first virtual portions of the same width, the virtual gate includes one or more second virtual portions of the same width, and the virtual gate includes one or more third virtual portions of the same width.

9. The lateral variable doping high-voltage LDMOS according to claim 7, characterized in that: The width ratio between the first virtual part and the second virtual part ranges from 2 to 10, and the width ratio between the first virtual part and the third virtual part ranges from 5 to 20.

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