Wiring substrate and manufacturing method thereof

Abstract

To provide a wiring substrate capable of suppressing migration between wirings and a manufacturing method thereof, in a manufacturing method of a wiring substrate including a first wiring substrate in which a first wiring layer is formed, and a second wiring substrate in which a second wiring layer finer than the first wiring layer is formed, the second wiring substrate is formed by performing the following steps: a step of forming a first insulating resin layer including a wiring pattern and an opening portion; a step of forming a first inorganic insulating film on the first insulating resin layer; a step of forming a first conductor layer corresponding to the wiring pattern and the opening portion on the inorganic insulating film; and a step of forming a second inorganic insulating film on the first conductor layer.

Description

TECHNICAL FIELD

[0001] The present application relates to a wiring substrate and a manufacturing method of a wiring substrate. BACKGROUND

[0002] In recent years, with the development of high speed and high integration of semiconductor devices, FC-BGA (Flip Chip-Ball Grid Array) wiring substrates on which semiconductor elements are mounted are also required to have narrow pitches of connection terminals connected to the semiconductor elements and fine wirings in the substrates. On the other hand, the connection of FC-BGA wiring substrates to mother boards is required to be performed using connection terminals having almost the same pitches as in the past.

[0003] To cope with the fine wirings in FC-BGA wiring substrates accompanying the narrow pitches of connection terminals connected to semiconductor elements, a technique of providing a multi-layer wiring substrate including fine wirings, called an interposer, between the FC-BGA wiring substrate and the semiconductor element is adopted.

[0004] One is a silicon interposer technique of forming an interposer on a silicon wafer using a manufacturing technique of semiconductor circuits.

[0005] In addition, a method of directly manufacturing an interposer on a FC-BGA wiring substrate without forming an interposer on a silicon wafer has also been developed. This is a method of planarizing the surface of a FC-BGA wiring substrate using CMP (Chemical Mechanical Polishing) or the like to directly form a multi-layer wiring substrate as an interposer on the FC-BGA wiring substrate. Regarding this method, it is disclosed in Patent Literature 1.

[0006] Further, there is a method of forming an interposer (multi-layer wiring substrate) on a support such as a glass substrate, mounting it on a FC-BGA substrate, and then peeling off the support to form a multi-layer wiring substrate with narrow pitches on a FC-BGA wiring substrate. Regarding this method, it is disclosed in Patent Literature 2.

[0007] PRIOR ART DOCUMENTS

[0008] PATENT LITERATURE

[0009] Patent Literature 1: Japanese Patent Application Publication No. 2014-225671

[0010] Patent Literature 2: International Publication No. 2018 / 047861 SUMMARY

[0011] PROBLEMS TO BE SOLVED BY THE INVENTION

[0012] Since the silicon interposer is produced by using a silicon wafer and using a device for a pre-process in semiconductor production, it is suitable for forming a fine wiring layer. However, the shape and size of the silicon wafer are limited, the number of interposers that can be produced from one wafer is small, and the production device is expensive, so the interposer becomes expensive. In addition, since the silicon wafer is a semiconductor, there is a problem of deterioration of transmission characteristics.

[0013] In addition, in a method in which the surface of the wiring substrate for FC-BGA is planarized and a multilayer wiring layer as an interposer is formed thereon, the deterioration of transmission characteristics that occurs in the silicon interposer is small, but there are problems of the production yield of the wiring substrate for FC-BGA itself, and the overall production yield is low because it is difficult to form fine wiring on the wiring substrate for FC-BGA. In addition, there is a problem of mounting of semiconductor elements due to warping and strain of the wiring substrate for FC-BGA.

[0014] Further, in a method in which a multilayer wiring substrate is formed on a support such as a glass substrate and is placed on the wiring substrate for FC-BGA, and the support is peeled off after that, when a fine wiring layer is formed on the support, a half-addition method is often used. Here, since the wiring layer is formed adjacent to a photosensitive resin layer used in the fine wiring layer, there is a problem that copper as a wiring layer material diffuses into the photosensitive resin layer in a high temperature and high humidity environment test or the like, and causes conduction between the wirings in the vicinity to occur, so-called migration (also called electromigration).

[0015] The present application was made in view of the above problems, and aims to provide a wiring substrate capable of suppressing migration between wirings and a manufacturing method thereof.

[0016] Means for solving the problems

[0017] To solve the above problems, a wiring substrate of a representative embodiment of the present application has a first wiring substrate in which a first wiring layer is formed, and a second wiring substrate in which a second wiring layer finer than the first wiring layer is formed, the first wiring substrate is joined to one face of the second wiring substrate, and a semiconductor element can be mounted to the other face.

[0018] An inorganic insulating film is formed between the second wiring layer of the second wiring substrate and an insulating resin layer.

[0019] In addition, a manufacturing method of a wiring substrate of a representative embodiment of the present application is a manufacturing method of a wiring substrate having a first wiring substrate in which a first wiring layer is formed, and a second wiring substrate in which two or more second wiring layers finer than the first wiring layer are formed, the first wiring substrate is joined to one face of the second wiring substrate, and a semiconductor element can be mounted to the other face.

[0020] The process of manufacturing the second wiring substrate has:

[0021] a process of forming a first insulating resin layer having a wiring pattern and an opening portion corresponding to the second wiring layer;

[0022] a process of forming a first inorganic insulating film on the first insulating resin layer;

[0023] a process of forming a first conductor layer corresponding to the wiring pattern and the opening portion on the first inorganic insulating film; and

[0024] a process of forming a second inorganic insulating film on the first conductor layer.

[0025] Effects of the Invention

[0026] According to the present application, a wiring substrate capable of suppressing migration between wirings and a manufacturing method thereof can be provided.

[0027] The problems, configurations, and effects other than the above will be clarified by the following embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] [ Figure 1 ] Figure 1 is a cross-sectional view of a semiconductor device using a wiring substrate shown in a state where a semiconductor element is mounted.

[0029] [ Figure 2 ] Figure 2 is a cross-sectional view showing a state where a peeling layer, a photosensitive resin layer, a seed adhesion layer, a seed layer, and a conductor layer are formed on a support.

[0030] [ Figure 3 ] Figure 3 is a cross-sectional view showing a state after the conductor layer and the seed layer are polished by surface polishing.

[0031] [ Figure 4 ] Figure 4 is a cross-sectional view showing a state where an electrode for bonding with a semiconductor element is formed by polishing the seed adhesion layer and the photosensitive resin layer by surface polishing.

[0032] [ Figure 5 ] Figure 5 is a cross-sectional view showing a state where an inorganic insulating film is formed.

[0033] [ Figure 6 ] Figure 6 is a cross-sectional view showing a state of the photosensitive resin layer where a via portion is formed.

[0034] [ Figure 7 ] Figure 7A cross-sectional view showing a state in which the through-hole portion and the wiring portion are formed.

[0035] [ Figure 8 ] Figure 8 A cross-sectional view showing a state in which the inorganic insulating film is formed in the through-hole portion and the wiring portion.

[0036] [ Figure 9 ] Figure 9 A cross-sectional view showing a state after the inorganic insulating film of the through-hole portion is removed.

[0037] [ Figure 10 ] Figure 10 A cross-sectional view showing a state in which the seed adhesion layer, the seed layer, and the conductor layer are formed in the same manner as described above.

[0038] [ Figure 11 ] Figure 11 A cross-sectional view showing a state in which the through-hole portion and the wiring portion are formed by surface polishing.

[0039] [ Figure 12 ] Figure 12 A cross-sectional view showing a state in which the interlayer connection conductor is formed by polishing the seed adhesion layer and the photosensitive resin layer.

[0040] [ Figure 13 ] Figure 13 A cross-sectional view showing a state in which the inorganic insulating film is formed.

[0041] [ Figure 14 ] Figure 14 A cross-sectional view showing a state in which the multilayer wiring is formed by repeating Figures 6-13 .

[0042] [ Figure 15 ] Figure 15 A cross-sectional view showing a state in which the photosensitive resin layer is formed.

[0043] [ Figure 16 ] Figure 16 A cross-sectional view showing a state in which the inorganic insulating film of the through-hole portion is removed, and the seed adhesion layer, the seed layer, and the resist pattern are formed in the same manner as the lower layer.

[0044] [ Figure 17 ] Figure 17 A cross-sectional view showing a state after the conductor layer is formed and the resist pattern is removed.

[0045] [ Figure 18 ] Figure 18 A cross-sectional view showing a state after the seed adhesion layer and the seed layer that are not needed are etched and removed.

[0046] [ Figure 19 ]Figure 19 FIG. 8 is a cross-sectional view showing a state where a solder bump is formed on the FC-BGA substrate.

[0047] [ Figure 20 ] Figure 20 FIG. 9 is a cross-sectional view showing a state where the FC-BGA substrate is joined to the wiring substrate on the support and a bottom-filling layer is sealed.

[0048] [ Figure 21 ] Figure 21 FIG. 10 is a cross-sectional view showing a state where the FC-BGA substrate is joined to the wiring substrate on the support and a bottom-filling layer is sealed.

[0049] [ Figure 22 ] Figure 22 FIG. 11 is a cross-sectional view showing a state where laser light is irradiated to the separation layer.

[0050] [ Figure 23 ] Figure 23 FIG. 12 is a cross-sectional view showing a state where the support is removed. DETAILED DESCRIPTION

[0051] Hereinafter, an embodiment of the present application will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each layer, and the like are different from the actual situation. Therefore, the specific thickness and dimension should be judged with reference to the following description. In addition, the drawings naturally include parts different in the dimensional relationship and the ratio from each other.

[0052] In addition, the embodiment shown below exemplifies a device and a method for embodying the technical idea of the present application, and the material, shape, structure, arrangement, and the like of the constituent parts are not specific to the following description. The technical idea of the present application can be variously changed within the technical scope defined in the claims.

[0053] Note that, in the present disclosure, "surface" refers not only to the surface of a plate-like member, but also, in the case of a layer included in a plate-like member, to the interface of the layer that is substantially parallel to the surface of the plate-like member. In addition, "upper surface" and "lower surface" refer to the surfaces shown on the upper side or the lower side in the drawing when the plate-like member or the layer included in the plate-like member is shown in the drawing.

[0054] In addition, "side surface" refers to the surface or the thickness portion of the plate-like member or the layer included in the plate-like member. Furthermore, a part of the surface and the side surface are sometimes collectively referred to as "end portion".

[0055] Additionally, "above" refers to the direction vertically above when a plate-like component or layer is placed horizontally. Furthermore, "above" and its opposite "below" are sometimes referred to as the "Z-axis direction"; for the horizontal direction, they are sometimes referred to as the "X-axis direction" and "Y-axis direction".

[0056] In addition, "planar shape" and "planar view" refer to the shape of a surface or layer when viewed from above. Furthermore, "sectional shape" and "sectional view" refer to the shape when viewed from the horizontal direction after cutting a plate-like component or layer in a specific direction.

[0057] Furthermore, "center portion" refers to the central portion that is not the periphery of a surface or layer. And "central direction" refers to the direction from the periphery of a surface or layer toward the center of its planar shape.

[0058] (Structure of wiring board)

[0059] The wiring substrate 16 in this embodiment is formed by bonding the second wiring substrate (intermediate layer) 13 to the FC-BGA substrate (also referred to as the first wiring substrate) 14. First, as Figure 1 As shown, the semiconductor device 18 manufactured using the wiring substrate 16 of this embodiment will be described in its entirety.

[0060] exist Figure 1 In this configuration, the second wiring substrate 13 is connected to the semiconductor element 17 on its first surface (top) and bonded to the FC-BGA substrate 14 on its second surface (bottom), forming a single semiconductor device 18. The wiring layers (also referred to as the second wiring layers) of the second wiring substrate 13 are finer than the wiring layers (also referred to as the first wiring layers) of the FC-BGA substrate 14, with adjacent wiring spacing set to, for example, 0.5 to 5.0 μm. Therefore, as will be described in detail later, migration suppression is required.

[0061] After the second wiring substrate 13 is connected to the semiconductor element 17 via the chip connection terminal 19, it is sealed and fixed by the sealing resin 26. In addition, after the second wiring substrate 13 is connected to the FC-BGA substrate 14 via the connection terminal 20 and the solder joint 12, it is sealed and fixed by the sealing resin 23.

[0062] As described below, the second wiring substrate 13 is formed above the support (carrier substrate) 1 via the release layer 2, and after being bonded to the FC-BGA substrate 14 together with the support 1, the support 1 is peeled off in the release layer 2.

[0063] The semiconductor element 17 can be joined to the second wiring substrate 13 after the FC-BGA substrate 14 is joined, or can be joined to the second wiring substrate 13 before the FC-BGA substrate 14 is joined. In the following description of the embodiments, a description will be given of a method in which the semiconductor element 17 is joined to the wiring substrate 16 after the second wiring substrate 13 is joined to the FC-BGA substrate 14.

[0064] (Method for manufacturing wiring substrate)

[0065] Use Figures 2-23 One example of a manufacturing process of a wiring substrate using a support according to the present embodiment will be described.

[0066] (1) Forming a release layer on the support

[0067] First, referring to Figure 2 A release layer 2 for releasing the support 1 in a subsequent process is formed on one face of the support 1.

[0068] The release layer 2 can be formed of, for example, a resin that generates heat or deteriorates by absorbing light such as UV light, and is thereby releasable, or can be formed of a resin that is foamed by heat and is thereby releasable. In the case of using a resin that is releasable by light such as UV light (for example, laser light), the support 1 can be removed from the bonded body of the second wiring substrate 13 and the FC-BGA substrate 14 on the support 1 by irradiating light from the face opposite to the side on which the release layer 2 is provided.

[0069] The material of the release layer 2 can be selected from, for example, organic resins such as epoxy resins, polyimide resins, polyurethane resins, silicone resins, polyester resins, oxetane resins, maleimide resins, and acrylic resins; or inorganic layers such as amorphous silicon, gallium nitride, and metal oxide layers. In addition, the material of the release layer 2 can contain additives such as photodecomposition accelerators, light absorbers, sensitizers, and fillers. In addition, the release layer 2 can be composed of a plurality of layers, for example, a protective layer can be further provided on the release layer 2 in order to protect the multilayer wiring layer formed on the support 1, or a layer that improves adhesion to the support 1 can be provided under the release layer 2. Further, a laser reflection layer or a metal layer can be provided between the release layer 2 and the multilayer wiring layer, and the configuration is not limited to the present embodiment.

[0070] Sometimes light is also irradiated onto the peeling layer 2 through the support 1, and therefore the support 1 is preferably transparent, and for example, glass can be used. Glass is excellent in flatness and high in rigidity, and therefore is suitable for fine pattern formation in a wiring substrate on a support. In addition, glass is small in CTE (coefficient of thermal expansion) and difficult to generate strain, and therefore is excellent in ensuring pattern arrangement accuracy and flatness.

[0071] In the case of using glass as the support 1, from the viewpoint of suppressing warping that occurs during manufacturing, it is desirable that the thickness of the glass be thick, for example, 0.5 mm or more, and preferably 1.2 mm or more. In addition, the CTE of the glass is preferably 3 ppm or more and 16 ppm or less, and from the viewpoint of the CTE of the FC-BGA wiring substrate 14 and the semiconductor element 17, it is more preferably set to about 10 ppm.

[0072] As the glass, for example, quartz glass, borosilicate glass, alkali-free glass, soda glass, or sapphire glass, or the like is used. On the other hand, in the case where a resin that is foamed by heat or the like is used in the peeling layer 2, and the support 1 does not need to have light transmittance at the time of peeling the support 1, the support 1 can use a material that is less strained, for example, metal or ceramic, or the like. In the present embodiment, a resin that is peelable by absorbing UV light is used as the peeling layer 2, and the support 1 uses glass.

[0073] (2) Forming a photosensitive resin layer on the peeling layer

[0074] Next, a photosensitive resin layer 3 as an insulating resin layer is formed on the peeling layer 2. In the present embodiment, as the photosensitive resin layer 3, for example, a photosensitive epoxy resin is formed by spin coating. The photosensitive epoxy resin can be cured at a low temperature, and is less in curing shrinkage after formation, and therefore is excellent in subsequent fine pattern formation.

[0075] As the method of forming the photosensitive resin, in the case of using a liquid photosensitive resin, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and blade coating. In the case of using a film-shaped photosensitive resin, lamination, vacuum lamination, vacuum pressing, or the like can be applied.

[0076] The photosensitive resin layer 3 can also use, for example, a photosensitive polyimide resin, a photosensitive benzocyclobutene resin, a photosensitive epoxy resin, and a modified product thereof as the insulating resin. Next, a large-diameter opening portion is provided on the photosensitive resin layer 3 by photolithography. The large-diameter opening portion can also be subjected to plasma treatment to remove residues at the time of development. The thickness of the photosensitive resin layer 3 is set in accordance with the thickness of the conductor layer formed in the large-diameter opening portion, and in the present embodiment, for example, is set to 8 μm. In addition, the shape of the large-diameter opening portion in plan view is set in accordance with the pitch and shape of the bonding electrodes of the semiconductor element, and in the present embodiment, for example, is formed to φ 25 μm with a pitch of 55 μm.

[0077] (3) Formation of Seed Adhesion Layer and Seed Layer

[0078] Next, a seed adhesion layer 4 and a seed layer 5 are formed in a vacuum. The seed adhesion layer 4 is a layer that improves the adhesion of the seed layer 5 to the photosensitive resin layer 3, and is a layer that prevents peeling of the seed layer 5. The seed layer 5 functions as a power supply layer for plating in the formation of wiring.

[0079] The seed adhesion layer 4 and the seed layer 5 are formed, for example, by a sputtering method or a vapor deposition method, and can apply, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu3N4, a Cu alloy, or a material obtained by combining a plurality of these. In the present embodiment, a titanium layer and a copper layer of the seed layer 5 are sequentially formed on the seed adhesion layer 4 by a sputtering method, taking into account the electric characteristics, ease of manufacturing, and cost aspects. The total film thickness of the titanium and copper layers as the power supply layer for plating is preferably 1 μm or less. In the present embodiment, Ti: 50 nm, Cu: 300 nm are formed.

[0080] (4) Formation of Conductor Layer

[0081] Next, a conductor layer 6 is formed by plating. The conductor layer 6 becomes an electrode for bonding with the semiconductor element 17. Examples of the plating can include plating nickel, plating copper, plating chromium, plating Pd, plating gold, plating rhodium, plating iridium, and the like, but plating copper is preferable because it is easy to handle and inexpensive, and has good electric conductivity. From the viewpoint of the electrode for bonding with the semiconductor element 17 and the solder bonding, the thickness of the plating copper is preferably 1 μm or more, and from the viewpoint of productivity, is preferably 30 μm or less. In the present embodiment, Cu: 10 μm is formed in the opening portion of the photosensitive resin layer 3, and Cu: 2 μm is formed in the upper portion of the photosensitive resin layer 3.

[0082] By the above procedures, a structure as shown in FIG. 1 can be obtained. Figure 2 Further, the following procedures are implemented.

[0083] (5) Polishing of the conductor layer

[0084] Next, as Figure 3 As shown, the copper layer is polished using CMP (chemical mechanical polishing) or other methods to remove the unwanted conductor layer 6 and seed layer 5. This allows the polishing process to be performed in a manner that makes the seed bonding layer 4 and conductor layer 6 the surface. In this embodiment, the Cu content of the conductor layer 6 of the photosensitive resin layer 3 is 2 μm, and the Cu content of the seed layer 5 is 300 nm, which are removed by polishing.

[0085] (6) Removal of the seed calyx and photosensitive resin layer

[0086] Next, as Figure 4 As shown, CMP processing and other grinding are performed again to remove the unwanted seed bonding layer 4 and photosensitive resin layer 3. Since the seed bonding layer 4 and photosensitive resin layer 3 are dissimilar materials, chemical grinding has little effect; physical grinding using an abrasive is more effective. However, to simplify the process, it is possible to refer to... Figure 3 Using the same grinding method as described above, the grinding method can be changed according to the material types of the seed bonding layer 4 and the photosensitive resin layer 3 in order to improve grinding efficiency. Then, the residual conductor layer 6 after grinding becomes an electrode for bonding with the semiconductor element 17.

[0087] (7) Formation of inorganic insulating film

[0088] Next, as Figure 5 As shown, an inorganic insulating film 7 is formed on top of the conductor layer 6 and the photosensitive resin layer 3, etc. The inorganic insulating film 7 can be made of silicon oxide (SiOx), silicon nitride (SiNx), SiC, SiOF, SiOC, etc. The thickness of the inorganic insulating film 7 is preferably 20 nm to 200 nm. In this embodiment, SiNx (50 nm thick) is used as the inorganic insulating film 7, and it is formed by plasma CVD, which allows for dense film formation at relatively low temperatures.

[0089] However, the inorganic insulating film 7 may not be an insulating film formed by plasma CVD, such as the silicon oxide film (SiOx) or silicon nitride film (SiNx). As long as it is an inorganic insulating film, there are no limitations on its type and manufacturing method.

[0090] (8) Formation of photosensitive resin layer

[0091] Next, as Figure 6As shown, a photosensitive resin layer 3 with a small-diameter opening is formed thereon using the same method as described above. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer formed at the small-diameter opening; in this embodiment, it is, for example, formed to be 2 μm. Furthermore, the shape of the small-diameter opening in the plan view is set from the perspective of connection with the conductor layer 6; in this embodiment, for example, an opening shape of φ11 μm is formed. This small-diameter opening has the shape of a through-hole connecting the upper and lower layers of multilayer wiring.

[0092] In addition, such as Figure 6 As shown, by placing the inorganic insulating film 7 at the interface between the photosensitive resin layers 3 and 3, the adhesion is improved compared to the case where the photosensitive resin layer 3 is formed directly on the photosensitive resin layer 3. Furthermore, by placing the inorganic insulating film 7 between the photosensitive resin layer 3 and the conductor layer 6, the adhesion is improved compared to the case where the conductor layer 6 is in direct contact with the photosensitive resin layer 3.

[0093] Furthermore, such as Figure 7 As shown, a photosensitive resin layer 3, having a large-diameter opening overlapping the small-diameter opening of the lower layer and a wiring pattern thereon, is formed thereon using the same method as described above. The thickness of the photosensitive resin layer 3 is set according to the thickness of the conductor layer formed in the large-diameter opening; in this embodiment, it is, for example, 2 μm. Furthermore, regarding the shape of the large-diameter opening in the plan view, from the viewpoint of the connectivity of the laminate, it is formed to surround the outer side of the small-diameter opening of the lower layer. In this embodiment, the shape of the large-diameter opening is, for example, φ25 μm. This large-diameter opening becomes the wiring portion of a multilayer wiring system; additionally, when multilayered, it becomes the solder receiving portion of a through-hole, i.e., a solder pad portion. In this embodiment, the through-hole portion for connecting layers is integrally formed together with the solder pad portion. As shown, the wiring portion constituting the wiring pattern of the photosensitive resin layer 3 has an isosceles trapezoidal shape with a lower base smaller than the upper base.

[0094] (9) Formation of inorganic insulating film

[0095] Next, as Figure 8 As shown, an inorganic insulating film 7' is formed on the photosensitive resin layer 3 and within the openings of the photosensitive resin layer 3. Similar to the inorganic insulating film 7, the inorganic insulating film 7' can also be made of silicon oxide (SiOx), silicon nitride (SiNx), SiC, SiOF, SiOC, etc. The thickness of the inorganic insulating film 7' is preferably 20 nm to 200 nm. In this embodiment, SiNx (50 nm thick) is used as the inorganic insulating film 7', and it is formed by plasma CVD, which allows for dense film formation at relatively low temperatures.

[0096] (10) Formation of openings in inorganic insulating films

[0097] Next, asFigure 9 As shown, for example, the inorganic insulating film 7' of the conductor layer 6 in the small-diameter opening portion of the photosensitive resin layer 3 is removed by a dry etching method in a vacuum. That is, by forming an opening in the inorganic insulating film 7' in a manner that the bottom of the small-diameter opening portion of the photosensitive resin layer 3 is open, a via portion is constituted by the conductor layer 6 formed inside the opening portion in a later-described process.

[0098] (11) Formation of Seed Adhesion Layer and Seed Layer

[0099] Next, by the same method as described above, the seed adhesion layer 4 and the seed layer 5 are formed in a vacuum, and further by the same method as described above, the conductor layer 6 is formed by electroplating. In the present embodiment, the seed adhesion layer 4 is formed to be Ti: 50 nm, the seed layer 5 is formed to be Cu: 300 nm, and the conductor layer 6 is formed to be Cu: 6 μm. This state is as shown in FIG. 6. Figure 2 Figure 10 As shown, since the seed layer 5 and the conductor layer 6 are the same material, the seed layer 5 is omitted in the figure. The conductor layer 6 becomes a via portion and a wiring portion.

[0100] (12) Removal of Conductor Layer and Seed Layer

[0101] As shown, by polishing by CMP (chemical mechanical polishing) processing or the like, the unnecessary conductor layer 6 and the seed layer 5 are removed. At this time, the seed adhesion layer 4 is formed on the side wall of the photosensitive resin layer 3 covered with the inorganic insulating film 7'. By making the seed adhesion layer 4 a continuous film and being formed with the inorganic insulating film 7' sandwiched on the side wall of the photosensitive resin layer 3, the risk of disconnection between the via portion and the pad portion due to thermal warping can be reduced. Figure 11 (13) Removal of Seed Adhesion Layer and Photosensitive Resin Layer

[0102] Next, as shown, by CMP (chemical mechanical polishing) processing or the like, polishing is performed again, and the unnecessary seed adhesion layer 4 and the photosensitive resin layer 3 are removed in a state where the inorganic insulating film 7' remains. Then, the conductor layer 6 remaining after the CMP processing or the like becomes a conductor portion of the via portion and the wiring portion. In the present embodiment, by polishing, Cu: 2 μm of the conductor layer 6 of the photosensitive resin layer 3 and Cu: 300 nm of the seed layer 5 are removed. In this way, an interlayer connection conductor layer in which the via portion and the pad portion are integrated can be formed.

[0103] Figure 12 (14) Formation of Inorganic Insulating Film

[0104] Next, as shown, by CMP (chemical mechanical polishing) processing or the like, polishing is performed again, and the unnecessary seed adhesion layer 4 and the photosensitive resin layer 3 are removed in a state where the inorganic insulating film 7' remains. Then, the conductor layer 6 remaining after the CMP processing or the like becomes a conductor portion of the via portion and the wiring portion. In the present embodiment, by polishing, Cu: 2 μm of the conductor layer 6 of the photosensitive resin layer 3 and Cu: 300 nm of the seed layer 5 are removed. In this way, an interlayer connection conductor layer in which the via portion and the pad portion are integrated can be formed.

[0105] Next, as shown, by CMP (chemical mechanical polishing) processing or the like, polishing is performed again, and the unnecessary seed adhesion layer 4 and the photosensitive resin layer 3 are removed in a state where the inorganic insulating film 7' remains. Then, the conductor layer 6 remaining after the CMP processing or the like becomes a conductor portion of the via portion and the wiring portion. In the present embodiment, by polishing, Cu: 2 μm of the conductor layer 6 of the photosensitive resin layer 3 and Cu: 300 nm of the seed layer 5 are removed. In this way, an interlayer connection conductor layer in which the via portion and the pad portion are integrated can be formed. Figure 13 ​​As shown, an inorganic insulating film 7 is formed on the residual inorganic insulating film 7'. The inorganic insulating film 7 can be made of silicon oxide (SiOx), silicon nitride (SiNx), SiC, SiOF, SiOC, etc. The thickness of the inorganic insulating film 7 is preferably 20 nm to 200 nm. In this embodiment, SiNx (50 nm thick) is used as the inorganic insulating film 7, and it is formed by plasma CVD, which allows for dense film formation at relatively low temperatures. Thus, the conductor layer 6 is surrounded by the photosensitive resin layer 3, and the inorganic insulating film 7' is further positioned between the photosensitive resin layer 3 and the conductor layer 6 below and to the side of the conductor layer 6, and as... Figure 14 As shown, in the further lamination process, the inorganic insulating films 7 and 7' are positioned between the photosensitive resin layer 3-2 and the conductor layer 6-1, above the conductor layer 6-1. Therefore, the second wiring layer formed by the conductor layer 6 is covered by the inorganic insulating films 7 and 7' in all directions, thereby preventing migration during high temperature and high humidity tests.

[0106] (15) Formation of multi-layer cabling

[0107] repeat Figures 6-13 The process involves forming a multilayer wiring structure by stacking two or more conductor layers 6. Specifically, the following process is performed: forming a first photosensitive resin layer 3 having a wiring pattern and openings corresponding to the second wiring layer. -1 The process (referred to as the first insulating resin layer) Figure 6 , 7 The process of forming an inorganic insulating film 7' (referred to as the first inorganic insulating film) on the first insulating resin layer. Figure 8 A first conductor layer 6 corresponding to the wiring pattern and the opening is formed on the first inorganic insulating film. -1 The process (referred to as the first conductor layer) Figure 10 , 11 The process of forming an inorganic insulating film 7 (referred to as the second inorganic insulating film) on the first conductor layer; and the process of forming an inorganic insulating film 7 (referred to as the second inorganic insulating film) on the first conductor layer. Figure 13 ).

[0108] Further, the following steps are performed: A second photosensitive resin layer 3, having wiring patterns and openings, is formed on the second inorganic insulating film using the same method as described above. -2 The process of forming an opening (referred to as the second insulating resin layer) on the second inorganic insulating film, for example, by dry etching in a vacuum, based on the opening of the second insulating resin layer. Figure 9 ); and a second conductor layer 6 forming an opening in the second inorganic insulating film that is connected to the first conductor layer. -2 The process (referred to as the second conductor layer) is then completed. This yields... Figure 14 The structure shown.

[0109] In the present embodiment, as shown in Figure 14 the second wiring layer is formed on the two conductor layers 6 having the isosceles trapezoidal shape with the lower base longer than the upper base. Further, in order to make the laminated second wiring layers conductive to each other, a via hole part 3a is formed using the opening part of the photosensitive resin layer 3 adjacent to the conductor layer 6, and an interlayer connection conductor layer is formed in the via hole part 3a. By forming an opening in the inorganic insulating film 7, 7' in the via hole part 3a, the second wiring layers can be made conductive to each other.

[0110] Further, as shown in Figure 14 the upper surface and the lower surface of each photosensitive resin layer 3 are covered with the inorganic insulating film 7, 7'.

[0111] (16) Formation of Photosensitive Resin Layer

[0112] Next, as shown in Figure 15 the photosensitive resin layer 3 is formed on the upper surface.

[0113] (17) Removal of Inorganic Insulating Film and Formation of Resist Pattern

[0114] Next, as shown in Figure 16 the inorganic insulating film 7 in the opening part of the photosensitive resin layer 3 is removed by dry etching by the same method as Figure 9 Then, by the same method as described above, the seed adhesion layer 4 and the seed layer 5 are formed in a vacuum, and further, the resist pattern 8 is formed.

[0115] (18) Formation of Electrode

[0116] Next, as shown in Figure 17 the conductor layer (solder connection) 9 is formed by plating. The conductor layer (solder connection) 9 becomes an electrode for joining with the FC-BGA substrate 14. As for the thickness of the plated copper, it is preferably 1 μm or more from the viewpoint of solder joining, and it is preferably 30 μm or less from the viewpoint of productivity. In the present embodiment, Cu: 10 μm is formed in the opening part of the photosensitive resin layer 3, and Cu: 8 μm is formed in the upper part of the photosensitive resin layer 3. Then, the resist pattern 8 is removed.

[0117] (19) Removal of Seed Adhesion Layer and Seed Layer

[0118] Next, as shown in Figure 18 the seed adhesion layer 4 and the seed layer 5 that are not needed are etched and removed.

[0119] (20) Formation of Solder Resist Layer

[0120] Next, as shown in Figure 19As shown, a solder resist layer 10 is formed. The solder resist layer 10 is exposed and developed to cover the photosensitive resin layer 3, and is formed with an opening that exposes the conductor layer (for solder connection) 9. It should be noted that, as the material of the solder resist layer 10, insulating resins such as epoxy resin and acrylic resin can be used. In this embodiment, as the solder resist layer 10, a photosensitive epoxy resin containing filler is used to form the solder resist layer 10.

[0121] Furthermore, a surface treatment layer 11 is provided to prevent surface oxidation of the conductor layer (for solder connection) 9 and to improve the wettability of solder bumps. In an embodiment of the present invention, an electroless Ni / Pd / Au plating film is formed as the surface treatment layer 11. It should be noted that an OSP (surface treatment using a water-soluble organic solderability preservative) film may also be formed on the surface treatment layer 11. Alternatively, an appropriate selection may be made from electroless tin plating, electroless Ni / Au plating, etc., depending on the application.

[0122] (21) Formation of solder joint

[0123] Next, as Figure 20 As shown, solder material is mounted on the surface treatment layer 11 and then fixed by a single melting and cooling process, thereby forming a solder joint 12 on the conductor layer 9 via the surface treatment layer 11. This completes the formation of the second wiring substrate 13 on the support body 1.

[0124] (22) Bonding of wiring substrate and FC-BGA substrate

[0125] Next, as Figure 21 As shown, the second wiring substrate 13 on the support is bonded to the FC-BGA substrate 14, and then the bonding portion is sealed using an underfill layer (sealing resin 23). The underfill layer is, for example, a material obtained by adding silica, titanium dioxide, aluminum oxide, magnesium oxide, or zinc oxide as fillers to a resin obtained by mixing one or more of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin. The underfill layer is formed by filling with liquid resin.

[0126] (23) Peeling off the support

[0127] Next, as Figure 22As shown, laser 15 is irradiated to make the release layer 2 peelable, and then the support 1 is peeled off. That is, by irradiating the release layer 2 formed at the interface with the support 1 from the back side of the support 1, that is, the side of the support 1 opposite to the FC-BGA substrate 14, with laser 15, the support 1 can be removed, making it peelable.

[0128] (24) Completion of wiring board

[0129] Next, as Figure 23 As shown, the support 1 is removed, and then the release layer 2, the seed bonding layer 4 and the seed layer 5 are removed to obtain the wiring substrate 16.

[0130] (25) Installation of semiconductor components

[0131] Then, by installing semiconductor element 17, the process is completed. Figure 1 The semiconductor device 18 is shown. Before mounting the semiconductor element 17, to prevent oxidation and improve the wettability of the solder bumps, surface treatments such as electroless Ni / Pd / Au plating, OSP, electroless tin plating, and electroless Ni / Au plating can be performed on the exposed conductor layer 6. Through these processes, the semiconductor device 18 is completed.

[0132] <Confirmation of Effect>

[0133] Next, the wiring substrate 16 manufactured as described above will be compared with a comparative example, and the comparison results will be explained.

[0134] The inventors used an example in which silicon nitride was used as inorganic insulating films 7 and 7' in the configuration of the wiring substrate 16 as an example, and a wiring substrate with the same configuration as the wiring substrate 16 except that it did not have inorganic insulating films 7 and 7' as a comparative example. Both were tested for 96 hours in a high-temperature and high-humidity bias test at 130°C, 85% humidity, and an applied voltage of 3.3V. The results showed that migration occurred in all cases in the comparative example, but no migration or conduction defects occurred in the example. This confirms the migration suppression effect provided by the inorganic insulating films 7 and 7'.

[0135] According to this embodiment, in the second wiring substrate on which a fine wiring layer is formed on a support substrate and mounted on an FC-BGA substrate, even when the substrate warps during heating, cracks in the photosensitive resin layer can be suppressed by surrounding the wiring portion with a seed bonding layer or an inorganic insulating film, and wiring breakage can be suppressed. Furthermore, peeling of the photosensitive resin can be suppressed, thereby improving the reliability of the second wiring substrate.

[0136] Further, by covering the periphery of the wiring with the inorganic insulating film, diffusion of the wiring material into the insulating resin can be suppressed, and thus the reliability of the wiring substrate can be further improved.

[0137] The present application can be used for a semiconductor device having a wiring substrate provided with an interposer or the like between a main substrate and an IC chip.

[0138] Explanation of symbols

[0139] 1: support, 2: release layer, 3: photosensitive resin layer (insulating resin layer), 4: seed adhesion layer, 5: seed layer, 6: conductor layer, 7 / 7': inorganic insulating film, 8: resist pattern, 9: conductor layer (solder connection portion), 10: solder resist layer, 11: surface treatment layer, 12: solder joint, 13: wiring substrate on support, 14: FC-BGA substrate, 15: laser, 16: wiring substrate, 17: semiconductor element, 18: semiconductor device, 19: chip connection terminal.

Claims

1. A wiring substrate comprising: a first wiring substrate having a first wiring layer formed thereon, and a second wiring substrate having a second wiring layer finer than the first wiring layer, wherein the first wiring substrate is bonded to one side of the second wiring substrate and a semiconductor element can be mounted on the other side. The feature is that an inorganic insulating film is formed between the second wiring layer and the insulating resin layer of the second wiring substrate. The second wiring substrate has two or more insulating resin layers, and the top and bottom surfaces of each insulating resin layer are covered with an inorganic insulating film. The inorganic insulating film is located at the interface between the insulating resin layers.

2. The wiring substrate according to claim 1, characterized in that, The second wiring layer is surrounded by the insulating resin layer, which sandwiches the inorganic insulating film and is adjacent to the second wiring layer.

3. The wiring substrate according to claim 1 or 2, characterized in that, The second wiring substrate has two or more second wiring layers, and the adjacent second wiring layers are connected via conductors formed in the openings of the inorganic insulating film.

4. The wiring substrate according to any one of claims 1 to 3, characterized in that, The inorganic insulating film is silicon nitride.

5. The wiring substrate according to any one of claims 1 to 4, characterized in that, The insulating resin layer is formed of a photosensitive insulating resin.

6. A method for manufacturing a wiring substrate, comprising a first wiring substrate having a first wiring layer and a second wiring substrate having two or more second wiring layers finer than the first wiring layer, wherein the first wiring substrate is bonded to one side of the second wiring substrate and semiconductor devices can be mounted on the other side of the wiring substrate, characterized in that, The process of manufacturing the second wiring substrate includes: The process of forming a first insulating resin layer having a wiring pattern and openings corresponding to the second wiring layer; The process of forming a first inorganic insulating film on the first insulating resin layer; The process of forming a first conductor layer on the first inorganic insulating film that corresponds to the wiring pattern and the opening; The process of forming a second inorganic insulating film on the first conductor layer; and The process of forming a second insulating resin layer having wiring patterns and openings on the second inorganic insulating film. The first insulating resin layer is covered with an inorganic insulating film on its upper and lower surfaces, and the second insulating resin layer is covered with an inorganic insulating film on its upper and lower surfaces, with the inorganic insulating film located at the interface between the first insulating resin layer and the second insulating resin layer.

7. The method for manufacturing a wiring substrate according to claim 6, characterized in that, have: The process of forming an opening on the second inorganic insulating film corresponding to the opening of the second insulating resin layer; and The process of forming a second conductor layer that is connected to the first conductor layer through an opening in the second inorganic insulating film.

8. The method for manufacturing a wiring substrate according to claim 7, characterized in that, At least one of the first inorganic insulating film and the second inorganic insulating film is made of silicon nitride and formed by plasma CVD.

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