Crystal ingot evaluation method and inspection apparatus

Abstract

A method and apparatus for evaluating a crystal ingot are provided. Defect information of a wafer obtained from the crystal ingot is acquired. The defect information includes locations of one or more defects identified by optical detection. A center of gravity of the defects is determined based on the defect information. Uniformity of the defects is evaluated based on the center of gravity. The uniformity is related to quality of the wafer after processing. Thus, production yield and quality can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a detection technique, and in particular, to a crystal ingot evaluation method and a detection device. BACKGROUND

[0002] Silicon carbide (SiC) is a compound semiconductor material composed of silicon and carbon, which is quite expensive and has special material properties. Notably, the quality of a SiC ingot directly affects subsequent processing. If a poor-quality ingot is processed, there may be poor yield and poor processing quality, or even cost. SUMMARY

[0003] The present application is directed to a crystal ingot evaluation method and a detection device, which can evaluate the quality of a crystal ingot early.

[0004] According to an embodiment of the present application, a crystal ingot evaluation method is applicable to evaluating a wafer. The crystal ingot evaluation method includes (but is not limited to) the following steps: obtaining defect information of a wafer from a crystal ingot. The defect information includes the positions of one or more defects identified by optical detection. The center of gravity positions of the defects are determined according to the defect information. The uniformity of the defects is evaluated according to the center of gravity positions. The uniformity is related to the quality of the wafer after processing.

[0005] According to an embodiment of the present application, a detection device includes (but is not limited to) a memory and a processor. The memory is used to store program code. The processor is coupled to the memory and is configured to load and execute the program code to obtain defect information of a wafer, determine the center of gravity positions of one or more defects according to the defect information, and evaluate the uniformity of the defects according to the center of gravity positions. The defect information includes the positions of the defects identified by optical detection. The uniformity is related to the quality of the wafer after processing.

[0006] Based on the above, according to the crystal ingot evaluation method and the detection device of the embodiments of the present application, the uniformity (e.g., whether concentrated) of the defect distribution is inferred based on the center of gravity of the defects, and is used as a basis for evaluating the quality of the crystal ingot. In this way, the quality of the crystal ingot can be judged early in the wafer inspection stage, which not only serves as a basis for procurement strategy judgment, but also saves a large amount of cost, such as processing cost, and improves production yield and quality, and reduces capacity loss. BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0008] Figure 1 is a block diagram of components of a detection device according to an embodiment of the present application;

[0009] Figure 2 is a flowchart of a crystal ingot evaluation method according to an embodiment of the present application;

[0010] Figure 3A and Figure 3B is a schematic diagram illustrating defect distribution for different quality wafer for basal plan dislocation (BPD);

[0011] Figure 4A and Figure 4B is a schematic diagram illustrating defect distribution for different quality wafer for threading edge dislocation (TED);

[0012] Figure 5A and Figure 5B is a schematic diagram illustrating defect distribution for different quality wafer for threading screw dislocation (TSD);

[0013] Figure 6 is a schematic diagram of a classification range according to an embodiment of the present application;

[0014] Figure 7 is a partial enlarged view of Figure 6 ;

[0015] Figure 8A is a schematic diagram illustrating defect distribution for a wafer of the highest evaluation value / ranking within 0-65 millimeters (mm) according to an example;

[0016] Figure 8B is a schematic diagram of a center of gravity of Figure 8A ;

[0017] Figure 9A is a schematic diagram illustrating defect distribution for a wafer of the highest evaluation value / ranking within 50-65 mm according to an example;

[0018] Figure 9B is a schematic diagram of a center of gravity of Figure 9A ;

[0019] Figure 10A is a schematic diagram illustrating defect distribution for a wafer of the highest evaluation value / ranking within 35-50 mm according to an example;

[0020] Figure 10B is a schematic diagram of a center of gravity of Figure 10A ;

[0021] Figure 11A is a schematic diagram illustrating defect distribution for a wafer of the highest evaluation value / ranking within 0-35 mm according to an example;

[0022] Figure 11B is Figure 11A a schematic view of the center of gravity of

[0023] Figure 12A is a schematic view of the distribution of defects within 0-65 mm of the lowest evaluated value / rating wafer of an example illustration;

[0024] Figure 12B is Figure 12A a schematic view of the center of gravity of

[0025] Figure 13A is a schematic view of the distribution of defects within 50-65 mm of the lowest evaluated value / rating wafer of an example illustration;

[0026] Figure 13B is Figure 13A a schematic view of the center of gravity of

[0027] Figure 14A is a schematic view of the distribution of defects within 35-50 mm of the lowest evaluated value / rating wafer of an example illustration;

[0028] Figure 14B is Figure 14A a schematic view of the center of gravity of

[0029] Figure 15A is a schematic view of the distribution of defects within 0-35 mm of the lowest evaluated value / rating wafer of an example illustration;

[0030] Figure 15B is Figure 15A a schematic view of the center of gravity of

[0031] BRIEF DESCRIPTION OF DRAWINGS

[0032] 100: detection device

[0033] 110: memory

[0034] 130: processor

[0035] S210-S250: steps

[0036] BPD: basal plane dislocation

[0037] TED: threading edge dislocation

[0038] TSD: threading screw dislocation

[0039] R1, R2: range

[0040] D1, D2, D3: distance

[0041] x, y: axis DETAILED DESCRIPTION

[0042] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0043] Figure 1 is a block diagram of components of a detection device 100 according to an embodiment of the application. Referring to Figure 1 , the detection device 100 includes, but is not limited to, a memory 110 and a processor 130.

[0044] The memory 110 can be any type of fixed or removable random access memory (RAM), read only memory (ROM), flash memory, conventional hard disk drive (HDD), solid-state drive (SSD), or the like. In an embodiment, the memory 110 is used to store program codes, software modules, configurations, data (e.g., defect information, barycenter position, uniformity, evaluation value or grade), or files, as will be described in later embodiments.

[0045] The processor 130 is coupled to the memory 110. The processor 130 can be a central processing unit (CPU), a graphic processing unit (GPU), or other programmable general purpose or special purpose microprocessors (Microprocessor), digital signal processors (Digital Signal Processor, DSP), programmable controllers, field programmable gate arrays (Field Programmable Gate Array, FPGA), application-specific integrated circuits (Application-Specific Integrated Circuit, ASIC), or other similar components or combinations thereof. In an embodiment, the functions of the processor 130 can be implemented in a standalone device, an integrated circuit (Integrated Circuit, IC), or software. In an embodiment, the processor 130 is used to perform all or part of the operations of the detection device 100, and can load and execute each software module, file, and data stored in the memory 110.

[0046] In the following, the method according to embodiments of the application will be described in conjunction with the components and modules in the detection device 100. Each flow of the method can be adjusted according to the implementation situation, and is not limited thereto.

[0047] Figure 2 is a flowchart of a wafer evaluation method according to an embodiment of the present application. Please refer to Figure 2 The processor 130 obtains defect information of a wafer from a wafer ingot (step S210). Specifically, the wafer ingot can be made of silicon carbide or other semiconductor materials. The wafer ingot can be cut to generate one or more wafers (or test pieces) to be tested. It is noted that the wafer can contain various crystal defects. For example, basal plane dislocation (BPD), threading edge dislocation (TED), and threading screw dislocation (TSD). An optical detection instrument (e.g., an automated optical inspection (AOI) device or a wafer inspection device) can perform defect detection on the crystal grains in the wafer to generate the defect information. In an embodiment, the defect information can include the positions of one or more defects identified by the optical detection. The positions can be coordinates, relative positions, or other position representative values. In another embodiment, the defect information can include the defect types of the detected defects. For example, basal plane dislocation, threading edge dislocation, and threading screw dislocation.

[0048] The processor 130 determines the barycentric position of the one or more defects according to the defect information (step S230). Specifically, the processor 130 can reconstruct each type of defect on an imaginary wafer surface according to the positions of the defects, and calculate the overall barycentric position of the positions of the defects. For example, assuming that the wafer is complete, the processor 130 can sum up the positions of all defects of a certain type relative to the center of the wafer and divide by the number of defects (i.e., position average) to obtain the barycentric position. For another example, if the test piece has a flat mouth or a notch, the processor 130 can only take the position average of the defects within the range with the flat mouth or the notch as the radius to obtain the barycentric position. It is noted that the center of the wafer can be the geometric center of the wafer or other specified position.

[0049] The processor 130 evaluates the uniformity of the one or more defects according to the barycentric position (step S250). Specifically, taking the center of the wafer, the origin of the coordinate system, or other specified center as the reference point, the closer the barycentric position is to the reference point, the higher the uniformity; the farther the barycentric position is from the reference point, the lower the uniformity. It is found by experiments that the uniformity is related to the quality of the wafer after processing. The higher the uniformity, the better the quality of the wafer after processing. The lower the uniformity, the worse the quality of the wafer after processing.

[0050] For example, Figure 3A andFigure 3B This is a schematic diagram illustrating the defect distribution of different quality specimens for basal plane dislocations (BPDs). Please refer to... Figure 3A and Figure 3B Defects are represented by black dots, with the horizontal axis being the x-axis and the vertical axis being the y-axis. Figure 3B The defects shown are partially concentrated in the lower left corner, and Figure 3A The defect distribution shown is relatively even. Therefore, processor 130 can be evaluated. Figure 3A The quality of the processed crystal ingots should be superior to Figure 3B The ingot. Specifically, the representation of defect locations can be designed differently depending on requirements; these locations can be coordinates, relative positions, or other positional representations. Figure 3A and 3B These are merely examples, and the invention is not limited thereto.

[0051] Figure 4A and Figure 4B This is a schematic diagram illustrating the defect distribution of different quality specimens for edge-shaped differential arrays (TED). Please refer to... Figure 4A and Figure 4B Defects are indicated by black dots. Figure 4B The defects shown are partially concentrated on the right side, and Figure 4A The defect distribution shown is relatively even. Therefore, processor 130 can be evaluated. Figure 4A The quality of the processed crystal ingots should be superior to Figure 4B Ingots.

[0052] Figure 5A and Figure 5B This is a schematic diagram illustrating the defect distribution of different quality specimens for through-screw dislocations (TSDs). Please refer to... Figure 3A and Figure 3B Defects are indicated by black dots. Therefore, processor 130 can be evaluated. Figure 5A The quality of the processed crystal ingots should be superior to Figure 5B Ingots.

[0053] In one embodiment, the uniformity index can be quantified into one or more evaluation values ​​(e.g., 1 to 5 points), grades (e.g., grades A, B, and C), or other units of quantification. The processor 130 can determine the classification range in which the center of gravity is located. Each evaluation value / grade corresponds to a classification range, and the centers of these classification ranges are the same as the center of the wafer. The wafer is divided into one or more classification ranges. The processor 130 can determine the evaluation value / grade of this type of defect based on the classification range in which the center of gravity is located. That is, if the center of gravity is located within one of these classification ranges, the processor 130 can use the evaluation value / grade corresponding to the classification range in which the center of gravity is located as the evaluation result of the uniformity of this defect type.

[0054] For example, Figure 6 is a schematic diagram of the classification ranges according to an embodiment of the present application. Please refer to Figure 6 , two concentric circles R1, R2 are formed on the coordinate graph. The distance from the center to the boundary of the two ranges R1, R2 is different. If the barycenter position is located within the range R1, the uniformity of this defect type belongs to level A. If the barycenter position is located between the range R1 and the range R2, the uniformity of this defect type belongs to level B. If the barycenter position is located outside the range R2, the uniformity of this defect type belongs to level C. Since the barycenter positions of the basal plane dislocations BPD, the threading edge dislocations TED and the threading screw dislocations TSD are all located within the range R1, the uniformity of these defect types all belong to level A.

[0055] In an embodiment, the processor 130 can further subdivide the evaluation values / levels of these types of defects for the same evaluation values / levels. For example, Figure 7 is a partial enlarged view of Figure 6 . Please refer to Figure 7 , the distance D1 between the barycenter position of the basal plane dislocation BPD and the reference point is less than the distance D2 between the barycenter position of the threading screw dislocation TSD and the reference point, and the distance D2 is less than the distance D3 between the barycenter position of the threading edge dislocation TED and the reference point. Therefore, the processor 130 determines that the basal plane dislocation BPD belongs to level AAA, the threading screw dislocation TSD belongs to level AA, and the threading edge dislocation TED belongs to level A.

[0056] In an embodiment, the processor 130 can determine the distance between the boundaries of one or more classification ranges, such as the ranges R1 and R2, from the center of the wafer according to the predicted bow degree of the wafer after the wafer processing process. For example, Figure 6 , if the processor 130 reduces the radius of the range R1, it can be predicted that the wafer within the range R1 has a lower bow degree. For another example, if a higher wafer bow degree is allowed, the processor 130 can expand the range R2.

[0057] In one embodiment, the processor 130 can set a plurality of evaluation values / ranks. For example, evaluation values 1 to 5, or ranks A to C. In addition, the processor 130 can obtain the barycentric positions of the defects of a plurality of defect types, and compare a first evaluation value / rank and a second evaluation value / rank among those evaluation values / ranks to generate a comparison result. Here, the first evaluation value / rank corresponds to a first barycentric position formed by defects of a first type among the defect types, and the second evaluation value / rank corresponds to a second barycentric position formed by defects of a second type among the defect types. For example, the comparison result is that the first evaluation value is lower than the second evaluation value, where the higher one of the evaluation values has a higher uniformity, and the lower one of the evaluation values has a lower uniformity. For another example, the comparison result is that the first rank is higher than the second rank, where the higher one of the ranks has a higher uniformity, and the lower one of the ranks has a lower uniformity. For yet another example, the comparison result is that the ranks / evaluation values are the same.

[0058] It should be noted that in some embodiments, it can also be that the higher one of the evaluation values has a lower uniformity, and the lower one of the evaluation values has a higher uniformity.

[0059] In one embodiment, the processor 130 can compare the distances of the first barycentric position and the second barycentric position from the center of the wafer to determine the comparison result of the two evaluation values / ranks. For example, the distance of the first barycentric position from the center of the wafer is shorter than the distance of the second barycentric position from the center of the wafer, then the comparison result is that the first rank is higher than the second rank, or the comparison result is that the first evaluation value is higher than the second evaluation value.

[0060] The processor 130 can determine the (total / final) evaluation value / rank of the defect types (or as the evaluation value / rank of the wafer) according to the comparison result of the first evaluation value / rank and the second evaluation value / rank. In one embodiment, if the comparison result is that the plurality of evaluation values / ranks are the same, the processor 130 can determine the evaluation value / rank of any defect type as the (total / final) evaluation value / rank of the defect types.

[0061] In one embodiment, if the comparison result is the lowest one of the plurality of evaluation values / ranks, the processor 130 can determine the lowest one of the evaluation values / ranks among the first evaluation value / rank and the second evaluation value / rank as the evaluation value / rank of the defect types. For example, if the basal plane dislocation BPD belongs to rank A, and the threading screw dislocation TSD belongs to rank B, then the wafer belongs to rank B.

[0062] It should be noted that the foregoing takes two defect types as an example, but the application can be similarly applied to more defect types. In addition, the foregoing embodiment is to evaluate the uniformity of the defects of the wafer as a whole, but it can also be evaluated in zones to improve accuracy.

[0063] In one embodiment, the processor 130 can divide the wafer into a plurality of zones and determine the center of gravity of one or more defects in each of the zones, respectively. The zones do not overlap and the range from the center of the wafer to the boundary of one of the zones is different from the range to the boundary of another of the zones. For example, the wafer has a radius of 65 millimeters (mm), a first zone is in a range of 0 to 35 mm from the center, a second zone is in a range of 35 to 50 mm from the center, and a third zone is in a range of 50 to 60 mm from the center.

[0064] Figure 8A is a schematic diagram of the distribution of defects in a wafer of the highest evaluation value / ranking according to the example explanation within 0-65 mm, and Figure 8B is Figure 8A a schematic diagram of the center of gravity of Figure 9A is a schematic diagram of the distribution of defects in a wafer of the highest evaluation value / ranking according to the example explanation within 50-65 mm, Figure 9B is Figure 9A a schematic diagram of the center of gravity of Figure 10A is a schematic diagram of the distribution of defects in a wafer of the highest evaluation value / ranking according to the example explanation within 35-50 mm, and Figure 10B is Figure 10A a schematic diagram of the center of gravity of Figure 11A is a schematic diagram of the distribution of defects in a wafer of the highest evaluation value / ranking according to the example explanation within 0-35 mm, and Figure 11B is Figure 11A a schematic diagram of the center of gravity of Figures 8A to 11B Referring to Figure 11B each of the center of gravity positions shown in FIG. 8A is closer to the center than Figure 9B each of the center of gravity positions shown in FIG. 8B.

[0065] Figure 12A is a schematic diagram of the distribution of defects in a wafer of the lowest evaluation value / ranking according to the example explanation within 0-65 mm, and Figure 12B is Figure 12A a schematic diagram of the center of gravity of Figure 13A is a schematic diagram of the distribution of defects in a wafer of the lowest evaluation value / ranking according to the example explanation within 50-65 mm, and Figure 13B is Figure 13A a schematic diagram of the center of gravity of Figure 14A is a schematic diagram of the distribution of defects in a wafer of the lowest evaluation value / ranking according to the example explanation within 35-50 mm, and Figure 14B is Figure 14A a schematic diagram of the center of gravity of Figure 15A is a schematic diagram of the distribution of defects in a wafer of the lowest evaluation value / ranking according to the example explanation within 0-35 mm, and Figure 15B is Figure 15Aa schematic diagram of the centers of gravity of the defects. Please refer to Figures 12A to 15B Similarly, the centers of gravity of different regions can be different. For example, Figure 15B The centers of gravity of the defects shown in FIG. 3 are farther away from the center than the centers of gravity of the defects shown in FIG. 2. Figure 13B The centers of gravity of the defects shown in FIG. 3 are farther away from the center than the centers of gravity of the defects shown in FIG. 2.

[0066] In an embodiment, the processor 130 can compare the third lowest evaluation value / rating of those regions and the fourth lowest evaluation value / rating of those defect types, and determine the lowest one of the third lowest evaluation value / rating and the fourth lowest evaluation value / rating as the (total / final) evaluation value / rating of those types of defects (or as the evaluation value / rating of the wafer). That is, the processor 130 can take the lowest evaluation value / rating of all defect types in all regions as the evaluation value / rating of the wafer.

[0067] For example, Table (1) is an example of uniformity evaluation:

[0068] Table (1)

[0069]

[0070] wherein the first evaluation is performed on defects of all defect types in the whole wafer, and the second evaluation is performed on defects of all defect types in each wafer region. If the first evaluation is rating A and the second evaluation is rating C, then the final rating is rating C, and the rest follows the same rule (i.e., take the lowest one). It is worth noting that if the first evaluation is already the lowest rating (e.g., rating C), the processor 130 can ignore the second evaluation and directly take the lowest rating as the final rating. Alternatively, if the first evaluation is lower than the second evaluation, the processor 130 can take the first evaluation as the final rating. Similarly, if the first evaluation is higher than the second evaluation, the processor 130 can take the second evaluation as the final rating. It is to be noted that the example is taken as rating, but evaluation value or other quantification of uniformity can also be applicable, and is not elaborated herein.

[0071] In summary, in the ingot evaluation method and the detection device of the embodiments of the present application, the uniformity of defect distribution is inferred according to the centers of gravity of the defects, and is further used as a basis for evaluating the quality of the ingot. In this way, the quality of the ingot can be judged early, not only saving cost, but also improving the quality, yield and time of subsequent processing.

[0072] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of evaluating a crystal ingot for evaluating a wafer, characterized by, The ingot evaluation method comprises: obtaining defect information of a wafer from an ingot, wherein the defect information comprises a position of at least one defect identified by optical detection; determining a barycentric position of the defect according to the defect information; evaluating uniformity of the defect according to the barycentric position, wherein the uniformity is related to quality of the wafer after a processing procedure; determining a distance from a center of the wafer to a boundary of a classification range according to a degree of bending expected after the wafer is processed by the processing procedure, wherein an index of the uniformity comprises at least one evaluation value, and the step of evaluating the uniformity of the defect according to the barycentric position comprises: determining the classification range in which the barycentric position is located, wherein each of the evaluation values corresponds to one of the classification ranges, and the center of the classification range is identical to the center of the wafer; and determining the evaluation value of the defect according to the classification range.

2. The ingot evaluation method according to claim 1, characterized by, The evaluation value comprises a plurality of evaluation values, the defect comprises a plurality of defects of a plurality of defect types, the defect information further comprises the defect types of the defects, and the step of determining the evaluation value of the defect according to the classification range comprises: comparing a first evaluation value and a second evaluation value in the evaluation values, wherein the first evaluation value corresponds to a first barycentric position formed by defects of a first type in the defect types, and the second evaluation value corresponds to a second barycentric position formed by defects of a second type in the defect types; and determining the evaluation value of the defect according to a comparison result of the first evaluation value and the second evaluation value.

3. The ingot evaluation method according to claim 2, characterized by, The step of determining the evaluation value of the defect according to the comparison result of the first evaluation value and the second evaluation value comprises: determining the evaluation value of the defect as the one with the lowest value in the first evaluation value and the second evaluation value.

4. The ingot evaluation method according to claim 2, characterized by, The step of comparing the first evaluation value and the second evaluation value in the evaluation values comprises: comparing a distance from the center of the wafer to the first barycentric position and a distance from the center of the wafer to the second barycentric position.

5. The ingot evaluation method according to claim 2, characterized by, The step of determining the barycentric position of the defect according to the defect information comprises: dividing the wafer into a plurality of regions, wherein the regions are not overlapped, and a range from the center of the wafer to a boundary of one of the regions is different from a range from the center of the wafer to a boundary of another of the regions; and respectively determining the barycentric position of the defect in the regions.

6. The ingot evaluation method according to claim 5, characterized by, The step of determining the evaluation value of the defect according to the comparison result of the first evaluation value and the second evaluation value comprises: comparing the one with the lowest value in the first evaluation value in the regions and the one with the lowest value in the second evaluation value in the defect types; and determining the evaluation value of the defect as the one with the lowest value in the one with the lowest value in the first evaluation value and the one with the lowest value in the second evaluation value.

7. A detection device, characterized in that comprises: a memory to store program codes; and a processor coupled to the memory and configured to load and execute the program codes to: obtain defect information of a wafer, wherein the defect information comprises a position of at least one defect identified by optical detection; determine a barycentric position of the defect according to the defect information; ​ evaluating uniformity of the defects according to the barycenter positions, wherein the uniformity is related to quality of the wafer after a processing procedure; determining a classification range in which the barycenter positions are located, wherein each of at least one grade corresponds to one of the classification ranges, and a center of the classification ranges is identical to a center of the wafer; and determining the grade of the defects according to the classification range; and determining a distance from the center of the wafer to a boundary of the classification range according to a degree of warping of the wafer after the processing procedure. The grade includes a plurality of grades, the defects include defects of a plurality of defect types, the defect information further includes the defect types of the defects, and the processor is further configured to:

8. The detection device of claim 7, wherein, compare a first grade and a second grade in the grades, wherein the first grade corresponds to a first barycenter position formed by defects of a first type in the defect types, and the second grade corresponds to a second barycenter position formed by defects of a second type in the defect types; and determine the grade of the defects according to a comparison result of the first grade and the second grade. The processor is further configured to:

9. The detection device of claim 8, wherein, determine a lowest one of the first grade and the second grade as the grade of the defects. The processor is further configured to:

10. The detection device of claim 8, wherein, compare distances from the center of the wafer to the first barycenter position and the second barycenter position. The processor is further configured to:

11. The detection device of claim 8, wherein, divide the wafer into a plurality of regions, wherein the regions are non-overlapping, and a range from the center of the wafer to a boundary of one of the regions is different from a range from the center of the wafer to a boundary of another one of the regions; and determine the barycenter positions of the defects in the regions, respectively. ​

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