Chip testing method and device, terminal equipment and computer readable storage medium

Abstract

The application discloses a chip testing method and device, a terminal device and a computer readable storage medium. The chip testing method comprises the following steps: acquiring first test results of a plurality of test chips tested by each probe in a last test process, wherein the first test results comprise failure and non-failure, and the plurality of test chips are located on the same wafer; determining a first failure degree of the plurality of test chips according to the first test results; and when the first failure degree reaches a failure threshold, retesting a first failure test chip, wherein the first failure test chip is a test chip with the first test result being failure. The above technical solution can improve the efficiency of chip testing.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and more specifically, to a chip testing method and apparatus, terminal equipment, and computer-readable storage medium. Background Technology

[0002] To ensure the quality of each chip on the wafer and to identify potential problems during manufacturing, parameter measurements and functional tests are required before shipment to verify the chip's functional integrity. During chip testing, problems with the probes themselves (such as probe tip contamination) can lead to low chip yields on the wafer.

[0003] When the yield of chips on a wafer is too low, it is necessary to analyze the reasons for the low yield and determine the source of the yield loss. Current technology usually involves manually screening for the causes of low yield, and then continuing chip testing after identifying the cause.

[0004] However, manually screening for problems relies heavily on the experience of technicians and takes a long time, resulting in low efficiency in chip testing. Summary of the Invention

[0005] The technical problem solved by this invention is how to perform chip testing in order to improve the efficiency of chip testing.

[0006] To address the aforementioned technical problems, the present invention provides a chip testing method, comprising: acquiring a first test result of multiple test chips tested by each probe in a previous test, the first test result including failure and non-failure, wherein the multiple test chips are located on the same wafer; determining a first failure degree of the multiple test chips based on the first test result; and retesting a first failed test chip when the first failure degree reaches a failure threshold, wherein the first failed test chip is the test chip whose first test result indicates failure.

[0007] Optionally, the first failure level is the number of consecutive failures, and determining the failure level of the plurality of test chips based on the first test result includes: determining the number of consecutive failures of the plurality of test chips, wherein the number of consecutive failures represents the maximum number of the first failed test chips that are tested in a consecutive order.

[0008] Optionally, determining the consecutive failure count of the plurality of test chips includes: if the first test result of the current test chip is a failure, determining whether the first test result of the previous test chip is a failure; if the first test result of the previous test chip is a failure, incrementing the consecutive failure count by 1; otherwise, setting the consecutive failure count to 1.

[0009] Optionally, the first failure level is the failure rate, and determining the failure level of the plurality of test chips based on the first test result includes: determining the failure rate of the plurality of test chips, wherein the failure rate represents the proportion of the first failed test chip to the total number of test chips.

[0010] Optionally, before retesting the first failed test chip, the process includes recording the position of the probe used to test the first failed test chip during the previous test in the probe card and the position of the first failed test chip in the wafer.

[0011] Optionally, the retesting of the first failed test chip includes: determining the probe that tested the first failed test chip during the previous test; and retesting the first failed test chip using the probe.

[0012] Optionally, the chip testing method further includes: obtaining second test results of multiple first failed test chips tested during the retesting process; determining a second failure degree based on the second test results; and generating a test report if the second failure degree reaches the failure threshold. The test report includes the positions of the probes for retesting the second failed test chips in the probe card and the positions of each second failed test chip in the wafer. The second failed test chips are the test chips whose second test results are failed during the retesting process.

[0013] The present invention also discloses a chip testing apparatus, comprising: an acquisition module for acquiring a first test result of multiple test chips tested by each probe in a previous test, the first test result including failure and non-failure, wherein the multiple test chips are located on the same wafer; a determination module for determining a first failure degree of the multiple test chips based on the first test result; and a testing module for retesting the first failed test chip when the failure degree reaches a failure threshold, wherein the first failed test chip is the test chip whose first test result indicates failure.

[0014] The present invention also discloses a terminal device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the computer program is executed by the processor to perform the steps of any of the chip testing methods described above.

[0015] The present invention also discloses a computer-readable storage medium storing a computer program thereon. The computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium. When the computer program is run by a processor, it executes the steps of any of the chip testing methods described above.

[0016] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0017] This invention proposes a chip testing method. By acquiring the first test results of multiple test chips located on the same wafer, tested by each probe in the previous test, the method determines the first degree of failure of the multiple test chips based on these results. When the failure degree reaches a failure threshold, the first failed test chip is retested. The first failed test chip is the one whose first test result indicates failure. This invention determines the first degree of failure of multiple test chips based on their test results to determine whether the multiple test chips meet yield requirements. Retesting the test chips when the first degree of failure reaches the failure threshold allows for verification of the test results of the first failed test chip, ensuring the accuracy of the test results. This saves technicians time in screening for problems when test chips encounter issues, ensures uninterrupted chip testing, and improves chip testing efficiency.

[0018] Furthermore, the probes used to test the first failed test chip in the previous test are identified, and the first failed test chip is retested using these probes to obtain second test results for multiple first failed test chips tested during the retest. Each probe tests multiple test chips at fixed locations on the wafer. After determining the first test result of a test chip, to verify the accuracy of the first test result, the probes used to test the first failed test chip can be used to retest its corresponding first failed test chip to ensure the accuracy of the first test result. If the second failure level reaches a failure threshold, a test report is generated to help technicians quickly determine the location of the second failed test chip on the wafer and the location of the probes used to test the second failed test chip in the probe card, improving the user experience for technicians. Attached Figure Description

[0019] Figure 1 This is an overall flowchart of a chip testing method provided in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram illustrating a usage scenario of a chip testing method provided in an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the structure of a chip testing device provided in an embodiment of the present invention. Detailed Implementation

[0022] As described in the background section, chip testing may result in low chip yield on the wafer due to problems with the probes themselves (such as probe tip contamination). When the chip yield on the wafer is too low, it is necessary to analyze the cause of the low yield and determine the source of the yield loss. Existing technology typically involves manually screening for the cause of the low yield, and then continuing chip testing after identifying the cause. However, manual problem screening is highly dependent on the experience of technicians and is time-consuming, resulting in low efficiency in chip testing.

[0023] In this invention, the first test results of multiple test chips located on the same wafer, tested by each probe in the previous test, are obtained to determine the first degree of failure of the multiple test chips based on the first test results. When the degree of failure reaches a failure threshold, the first failed test chip is retested. The first failed test chip is the test chip whose first test result indicates failure. This invention determines the first degree of failure of multiple test chips based on the test results of multiple test chips to determine whether the multiple test chips meet yield requirements. Retesting the test chips when the first degree of failure reaches the failure threshold allows for verification of the test results of the first failed test chip, ensuring the accuracy of the test results. This saves technicians time in screening for problems when test chips encounter issues, ensures uninterrupted chip testing, and improves chip testing efficiency.

[0024] Furthermore, the probes used to test the first failed test chip in the previous test are identified, and the first failed test chip is retested using these probes to obtain second test results for multiple first failed test chips tested during the retest. Each probe tests multiple test chips at fixed locations on the wafer. After determining the first test result of a test chip, to verify the accuracy of the first test result, the probes used to test the first failed test chip can be used to retest its corresponding first failed test chip to ensure the accuracy of the first test result. If the second failure level reaches a failure threshold, a test report is generated to help technicians quickly determine the location of the second failed test chip on the wafer and the location of the probes used to test the second failed test chip in the probe card, improving the user experience for technicians.

[0025] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Figure 1 This is an overall flowchart of a chip testing method provided in an embodiment of the present invention.

[0027] In specific implementation, the chip testing methods described in steps 101 to 103 below can be used in terminal devices. These steps can be executed by the terminal device itself, by a chip with data processing capabilities within the terminal device, or by a chip module within the terminal device that includes a chip with data processing capabilities.

[0028] Specifically, such as Figure 1 As shown, the chip testing method may include the following steps:

[0029] In step 101, the first test results of the multiple test chips tested by each probe in the previous test process are obtained;

[0030] In step 102, the first degree of failure of the plurality of test chips is determined based on the first test result;

[0031] In step 103, when the first failure level reaches the failure threshold, the first failure test chip is retested.

[0032] In this embodiment, multiple test chips are located on the same wafer. Testing the test chips on a wafer-by-wafer basis ensures that the manufacturing conditions of each test chip are the same, avoiding differences in the manufacturing process of test chips on different wafers that could lead to variations in test chip quality.

[0033] In a specific embodiment of step 101, the terminal device acquires the first test results of the multiple test chips tested by each probe in the previous test process. During actual testing, the test card has multiple probes, each of which tests the corresponding test chip on the wafer. Each time the probe card performs a touchdown, the probe makes electrical contact with the test chip at its corresponding position to transmit the test signal to the test chip, completing the test. After a touchdown, the wafer can be moved so that the position of each probe on the probe card corresponds to another test chip on the wafer, allowing for the next test of that other test chip.

[0034] After the probes on the probe card complete the tests on all the test chips on the wafer, the first test results for each probe on multiple test chips are obtained. The first test results include failure and no failure. A first test result of failure indicates that the test chip's function does not meet the standard, while a first test result of no failure indicates that the test chip's function can operate normally.

[0035] In a specific embodiment of step 102, a first degree of failure of the multiple test chips is determined based on the first test results. The first degree of failure indicates the extent to which the functions of the multiple test chips on the wafer fail to meet the standards.

[0036] Specifically, the first degree of failure can be determined based on the number of consecutive failures of multiple test chips and / or the failure rate of multiple test chips.

[0037] In one specific embodiment, the first failure level can be the number of consecutive failures of the test chips. Each probe tests multiple test chips on the wafer. If the probe is contaminated, it will cause the first test result of multiple consecutive test chips tested by that probe to be a failure. The number of consecutive failures of multiple test chips can be determined. If the number of consecutive failures reaches a failure threshold, it means that the first failed test chip needs to be retested. The first failed test chip is the test chip whose first test result is a failure.

[0038] The consecutive failure count represents the maximum number of test chips that fail consecutively in a test sequence. If the first test result of the current test chip is a failure, it checks whether the first test result of the previous test chip is also a failure. If the first test result of the previous test chip is a failure, the consecutive failure count is incremented by 1; otherwise, the consecutive failure count is set to 1. For example, probe A tests test chips 1 to 6 in a consecutive test sequence. Test chip 3's first test result is not a failure, while the first test results of the other test chips are failures. Specifically, if test chip 1's first test result is determined to be a failure, the consecutive failure count is 1; if test chip 2's first test result is a failure, and test chip 1's first test result is also a failure, the consecutive failure count is 2; if test chip 3's first test result is not a failure, the calculation of the consecutive failure count ends, and the consecutive failure count is 2. Similarly, if test chips 4 to 6 fail consecutively, the maximum number of test chips that fail consecutively in a test sequence is used as the consecutive failure count, meaning the consecutive failure count for the multiple test chips corresponding to probe A is determined to be 3.

[0039] In another specific embodiment, the first failure level can be the failure rate of multiple test chips, where the failure rate represents the proportion of test chips that fail first out of the total test chips. For example, probe A tests test chips 1 through 6 respectively. If test chips 1, 3, and 5 show failure as the first test result, while the other test chips show no failure as the first test result, then the failure rate of the multiple test chips corresponding to probe A is 50%.

[0040] It should be noted that the number of consecutive failures or failure rate of multiple test chips can be used as the first degree of failure, or the number of consecutive failures and failure rate of multiple test chips can be used together as the first degree of failure. The criteria for judging the first degree of failure can be selected according to the actual situation, and this application does not impose any restrictions on this.

[0041] In a specific implementation, the positions of the probes that tested the first failed test chip in the probe card and the positions of the first failed test chip in the wafer during the previous test can be recorded to facilitate retesting of the first failed test chip.

[0042] In a specific implementation of step 103, it is determined whether the first failure level has reached a failure threshold. Specifically, if the number of consecutive failures is used as the first failure level, it can be determined whether the number of consecutive failures has reached the failure threshold. In this case, the failure threshold is a preset positive integer. For example, a preset proportion of the number of times the probe card touchdowns can be used as the failure threshold. If the failure rate is used as the first failure level, it can be determined whether the failure rate has reached the failure threshold. In this case, the failure threshold is a preset proportion.

[0043] In a specific implementation, the number of consecutive failures and the failure rate can be used together as the first failure level. When both the number of consecutive failures and the failure rate reach the failure threshold, it can be determined that the first failure test chip should be retested.

[0044] In a non-limiting embodiment, if the first failure level of the multiple test chips corresponding to the probe reaches the failure threshold, the probe that tested the first failed test chip in the previous test is determined, so that the first failed test chip can be retested using the probe.

[0045] Furthermore, the second test results of multiple first-failed test chips tested during the retesting process are obtained, and the second failure level is determined based on the second test results. If the second failure level reaches a failure threshold, it indicates that the second-failed test chip and its corresponding probes are highly likely to have a problem. Retesting can then be stopped, and a test report is generated to facilitate problem analysis by technicians. The second-failed test chip is the test chip whose second test result indicates failure during the retesting process. Specifically, the test report may include the positions of the probes retesting the second-failed test chip in the probe card and the positions of each second-failed test chip on the wafer. Using the test report, technicians can quickly locate the specific positions of the second-failed test chip and its corresponding probes, improving the efficiency of problem screening.

[0046] In a non-limiting embodiment, the second failure test chip can be retested when the second failure level reaches the failure threshold, and the retesting can continue when the failure level obtained in the next retest reaches the failure threshold until the end condition of the retest is met and a test report is generated.

[0047] It should be noted that the termination conditions for retesting can be selected according to the actual situation, and this application does not impose any restrictions on this.

[0048] Now combined Figure 2 The retesting process for the first failed test chip is described in detail.

[0049] like Figure 2 As shown, the wafer includes eight test chips, C1 to C8, and the probe card includes probes P1 and P2. Probes P1 and P2 correspond to the positions of test chips C1 and C2, respectively. After a touchdown, the probe card completes the testing of test chips C1 and C2. Further, probe P1 sequentially tests test chips C3, C7, and C5, and probe P2 sequentially tests test chips C4, C8, and C6 to obtain the first test result for each chip. The first test result for test chips C1, C2, C3, and C6 is considered a failure, while the first test result for the other chips is considered a success. Test chips C1, C2, C3, and C6 are designated as the first failed test chips.

[0050] When the first failure level is defined as consecutive failures and the failure threshold is 2, the first failure test chips C1 and C3 corresponding to probe P1 are consecutively failing test chips, reaching the failure threshold. Therefore, they need to be retested using probe P1. However, the first failure test chip corresponding to probe P2 has a consecutive failure count of 1, which does not reach the failure threshold, so it does not need to be retested.

[0051] When the first failure level is the failure rate and the failure threshold is 50%, the failure rate of the first failure test chip corresponding to probe P1 is 50%, and the failure rate of the first failure test chip corresponding to probe P2 is 50%, both reaching the failure threshold. It is necessary to retest the first failure test chips C1 and C3 using probe P1, and to retest the first failure test chips C2 and C6 using probe P2.

[0052] In this embodiment, the number of consecutive failures and the failure rate are used together as the first failure level.

[0053] In a specific implementation, probe P1 is used to retest the first failure test chips C1 and C3, and probe P2 is used to retest the first failure test chips C2 and C6 to obtain the second test results for each of the first failure test chips. At this point, the second test results for the first failure test chips C1 and C3 are "failed," while the second test results for the first failure test chips C2 and C6 are "not failed." Therefore, the first failure test chips C1 and C3 are designated as the second failure test chips.

[0054] The second failure level is determined based on the second test results of each first failure test chip. The steps for determining the second failure level are the same as those for determining the first failure level, and will not be repeated here. When the second failure test chips C1 and C3 corresponding to probe P1 reach the failure threshold, a test report can be generated. The test report can include the positions of the second failure test chips C1 and C3 on the wafer. For example, taking the test chip at the top left corner of the wafer as the origin, the coordinates of the second failure test chip C1 are (0,0), and the coordinates of the second failure test chip C3 are (2,0). The test report can also include the position of probe P1 corresponding to the second failure test chip on the probe card. For example, taking the probe at the top left corner of the probe card as the origin (the probes on the probe card can be arrayed), the coordinates of probe P1 are (0,0). Technicians can quickly locate the problematic probe and the second failure test chip based on the test report, facilitating problem analysis and greatly improving their work efficiency.

[0055] In this embodiment, the probes used to test the first failed test chip are used to retest the corresponding first failed test chip, ensuring the accuracy of the initial test results. Furthermore, verifying the test results of the first failed test chip saves technicians time in troubleshooting when problems arise, ensuring the continuity of the chip testing process and improving testing efficiency. A test report is generated when the second failure level reaches the failure threshold, allowing technicians to quickly locate the second failed test chip and its corresponding probes, accelerating the troubleshooting process and improving the user experience.

[0056] like Figure 3 As shown, this embodiment of the invention also discloses a chip testing apparatus. The chip testing apparatus 30 includes:

[0057] The acquisition module 301 is used to acquire the first test results of multiple test chips tested by each probe in the previous test process. The first test results include failure and non-failure, and the multiple test chips are located on the same wafer.

[0058] The determining module 302 is used to determine the first failure degree of the plurality of test chips based on the first test result;

[0059] The test module 303 is used to retest the first failure test chip when the failure level reaches the failure threshold, wherein the first failure test chip is the test chip whose first test result is failure.

[0060] In specific implementation, the aforementioned chip testing device may correspond to a chip with data processing function in a terminal device, such as a SOC (System-On-a-Chip), a baseband chip, etc.; or to a chip module in a terminal device that includes a chip with data processing function; or to a chip module with a chip having data processing function; or to a terminal device.

[0061] For more information on the working principle and operation mode of the chip testing device 30, please refer to [link / reference needed]. Figure 1 and Figure 2 The relevant descriptions in the text will not be repeated here.

[0062] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0063] This invention also discloses a storage medium, wherein the computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and the storage medium stores a computer program thereon, which can be executed when the computer program is run. Figure 1 and Figure 2The steps of the method shown are illustrated. The storage medium may include ROM, RAM, disk, or optical disk, etc. The storage medium may also include non-volatile memory or non-transitory memory, etc.

[0064] This invention also discloses a terminal device, which may include a memory and a processor. The memory stores a computer program that can run on the processor, and the processor can execute the computer program. Figure 1 and Figure 2 The steps of the method shown are as follows.

[0065] In the embodiments of this application, "multiple" refers to two or more.

[0066] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0067] It should be understood that in the embodiments of this application, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0068] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0069] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0070] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0071] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0072] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0073] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically comprised separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional units.

[0074] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute some steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0075] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A chip testing method, characterized in that, include: Obtain the first test results of multiple test chips tested by each probe in the previous test process, the first test results including failure and non-failure, the multiple test chips are located on the same wafer; The first failure degree of the plurality of test chips is determined based on the first test result, and the first failure degree is determined based on the number of consecutive failures of the plurality of test chips and / or the failure rate of the plurality of test chips; When the first failure level reaches the failure threshold, the first failure test chip is retested. The first failure test chip is the test chip whose first test result is failure.

2. The chip testing method according to claim 1, characterized in that, The first failure level is the number of consecutive failures, and determining the failure level of the plurality of test chips based on the first test result includes: The consecutive failure number of the plurality of test chips is determined, wherein the consecutive failure number represents the maximum number of first failed test chips that are tested in a consecutive order.

3. The chip testing method according to claim 2, characterized in that, Determining the number of consecutive failures of the plurality of test chips includes: If the first test result of the current test chip is failure, determine whether the first test result of the previous test chip is failure; If the first test result of the previous test chip is a failure, the consecutive failure count is incremented by 1; otherwise, the consecutive failure count is set to 1.

4. The chip testing method according to claim 1, characterized in that, The first failure level is the failure rate, and determining the failure level of the plurality of test chips based on the first test result includes: Determine the failure rate of the plurality of test chips, wherein the failure rate represents the proportion of the first failed test chip to the total number of test chips.

5. The chip testing method according to claim 1, characterized in that, Before retesting the failed test chip, the following steps are included: Record the position of the probe used to test the first failure test chip in the probe card and the position of the first failure test chip in the wafer during the previous test.

6. The chip testing method according to claim 1, characterized in that, The retesting of the first failed test chip includes: Determine the probe that was used to test the first failure test chip during the previous test; The first failed test chip was retested using the probe.

7. The chip testing method according to claim 1, characterized in that, Also includes: Obtain the second test results of multiple first-failure test chips tested during the retesting process; The second degree of failure is determined based on the results of the second test. If the second failure level reaches the failure threshold, a test report is generated. The test report includes the position of the probe in the probe card for retesting the second failure test chip and the position of each second failure test chip in the wafer. The second failure test chip is the test chip whose second test result is failure during the retesting process.

8. A chip testing device, characterized in that, include: The acquisition module is used to acquire the first test results of multiple test chips tested by each probe in the previous test process. The first test results include failure and non-failure, and the multiple test chips are located on the same wafer. A determining module is configured to determine a first failure degree of the plurality of test chips based on the first test result, wherein the first failure degree is determined based on the number of consecutive failures of the plurality of test chips and / or the failure rate of the plurality of test chips; The testing module is used to retest the first failure test chip when the failure level reaches the failure threshold, wherein the first failure test chip is the test chip whose first test result is failure.

9. A terminal device, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the chip testing method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer-readable storage medium is a non-volatile storage medium or a non-transient storage medium, and the computer program is executed by the processor to perform the steps of the chip testing method according to any one of claims 1 to 7.

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