Signal synchronization circuit, method and communication device

Abstract

The present disclosure provides a signal synchronization circuit, method and communication device, the signal synchronization circuit comprising a signal selection sub-circuit configured to select at least two input digital signals from a plurality of input digital signals according to a time sequence, and to perform a conjugate complex multiplication process on the selected at least two input digital signals to obtain a first output signal; a first signal processing sub-circuit configured to perform a logic operation process on the first output signal to obtain a second output signal; and a second signal processing sub-circuit configured to sequentially perform a modulo operation process and a power difference process with a reference signal on the second output signal to obtain a synchronization signal.

Description

Technical Field

[0001] This disclosure relates to the field of synchronization circuit technology, and more specifically, to a signal synchronization circuit, method, and communication device. Background Technology

[0002] A synchronization circuit is a sequential logic circuit synchronized by a time pulse signal sub-circuit. In wireless communication, the synchronization circuit is used to process a frame of data from the input signal to obtain the synchronization point (i.e., the synchronization signal).

[0003] In related technologies, finding the synchronization point of the input signal through a synchronization circuit often requires a relatively complex clock control signal, which results in an increase in the area of ​​the synchronization circuit and a large power consumption output. Summary of the Invention

[0004] This disclosure presents a signal synchronization circuit, method, and communication device.

[0005] According to a first aspect of this disclosure, a signal synchronization circuit is proposed, comprising a signal selection sub-circuit configured to select at least two input digital signals from a plurality of input digital signals according to a time sequence, and to perform conjugate complex multiplication on the selected at least two input digital signals to obtain a first output signal; a first signal processing sub-circuit configured to perform logical operation processing on the first output signal to obtain a second output signal; and a second signal processing sub-circuit configured to sequentially perform modulo processing and power difference processing with a reference signal on the second output signal to obtain a synchronization signal.

[0006] For example, the signal selection sub-circuit includes: a data selection unit configured to select from multiple input digital signals according to a time series to obtain a first digital signal and a second digital signal for the current processing cycle; a conjugate processing unit configured to perform conjugate processing on the first digital signal to obtain a conjugate-processed first digital signal; and a conjugate complex multiplication processing unit configured to perform conjugate complex multiplication processing on the conjugate-processed first digital signal and the second digital signal to obtain a first output signal.

[0007] For example, the data selection unit includes a first data selector configured to select from multiple input digital signals according to a time series to obtain a first target signal, a second target signal, a third target signal, and a fourth target signal; a second data selector configured to select from the first target signal, the second target signal, and a 0 signal according to a time series to obtain a first digital signal; and a third data selector configured to select from the third target signal, the fourth target signal, and a 0 signal according to a time series to obtain a second digital signal.

[0008] For example, the first signal processing sub-circuit includes a first adder unit configured to perform an addition operation on a first output signal and a delayed output signal of the first adder unit according to a selection signal to obtain a first output signal after addition; and a first multiplier unit configured to perform a multiplication operation on the first output signal after addition according to preset multiplication coefficients to obtain a second output signal.

[0009] For example, the first signal processing sub-circuit further includes a first signal delay unit, configured to delay the output signal of the first adder unit to obtain the delayed output signal of the first adder unit.

[0010] For example, the first signal delay unit includes a fourth data selector configured to select the output signal of the first adder unit according to a selection signal to obtain a selected output signal; multiple storage units configured to store the output signal of the fourth data selector unit according to a time sequence; and a fifth data selector configured to select each signal in the multiple storage sub-units according to a selection signal and output the reselected signal to the first adder unit.

[0011] For example, the second signal processing sub-circuit includes a first rounding unit configured to round the second output signal to obtain a rounded second output signal; a sixth data selector configured to select the rounded second output signal according to a selection signal to obtain a first output signal, a second output signal, and a third output signal; a first branch configured to perform modulo processing, logical operation processing, and rounding processing on the second output signal to obtain an autocorrelation signal; and a second branch configured to perform logical operation processing and rounding processing on the third output signal, and to perform logical operation processing on the rounded third output signal and the autocorrelation signal to obtain a synchronization signal.

[0012] For example, the first branch includes a modulus-taking unit configured to perform modulus-taking processing on the second output signal to obtain a modulo-taken second output signal; a second addition unit configured to perform addition operations on the modulo-taken second output signal and the delayed output signal of the second addition unit to obtain a logically operated second output signal; and a second rounding unit configured to perform rounding processing on the logically operated second output signal to obtain an autocorrelation signal.

[0013] For example, the second branch includes a second multiplication unit configured to perform multiplication operations on the third output signal according to preset multiplication coefficients to obtain a multiplied third output signal; a third rounding unit configured to round the multiplied third output signal to obtain a rounded third output signal; and a third addition unit configured to perform subtraction operations on the rounded third output signal and the autocorrelation signal to obtain a synchronization signal.

[0014] For example, the second signal processing sub-circuit also includes a third branch configured to output a first output signal.

[0015] According to a second aspect of the present disclosure, a method for generating a synchronization signal is provided. The method is applied to a signal synchronization circuit, comprising selecting at least two input digital signals from a plurality of input digital signals according to a time sequence, and performing conjugate complex multiplication on the selected at least two input digital signals to obtain a first output signal; performing logical operation processing on the first output signal to obtain a second output signal; and sequentially performing modulo processing and power difference processing with a reference signal on the second output signal to obtain a synchronization signal.

[0016] According to a third aspect of the present disclosure, a communication device is provided, including a signal synchronization circuit as provided in the first aspect of the present disclosure.

[0017] According to the technical solution of the disclosed embodiment, a signal synchronization circuit is provided. This circuit obtains a synchronization signal by selecting and processing multiple input digital signals. This synchronization signal is an autocorrelation-based synchronization signal. By multiplexing adders and multipliers in the first and second signal processing sub-circuits, the circuit area and power consumption are reduced. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become clearer from the following description of embodiments in conjunction with the accompanying drawings. It should be noted that throughout the drawings, the same elements are indicated by the same or similar reference numerals. In the figures:

[0019] Figure 1 A schematic diagram of a signal synchronization circuit according to an embodiment of the present disclosure is shown;

[0020] Figure 2 A schematic diagram of the structure of a signal synchronization circuit according to another embodiment of the present disclosure is shown;

[0021] Figure 3 A schematic diagram of the structure of a first equivalent circuit according to an embodiment of the present disclosure is shown;

[0022] Figure 4 A schematic diagram of the structure of a second equivalent circuit according to an embodiment of the present disclosure is shown;

[0023] Figure 5 A flowchart of a synchronization signal generation method according to an embodiment of the present disclosure is shown; and

[0024] Figure 6 A schematic diagram of a synchronization device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0026] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by those skilled in the art. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0027] The figures illustrate several block diagrams and / or flowcharts. It should be understood that some blocks, or combinations thereof, in the block diagrams and / or flowcharts can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that, when executed by the processor, these instructions can create means for implementing the functions / operations described in these block diagrams and / or flowcharts. The technology disclosed herein can be implemented in hardware and / or software (including firmware, microcode, etc.). Alternatively, the technology disclosed herein can take the form of a computer program product stored on a computer-readable storage medium, which is available for use by or in conjunction with an instruction execution system.

[0028] This disclosure provides a signal synchronization circuit, including a signal selection sub-circuit configured to select at least two input digital signals from a plurality of input digital signals according to a time sequence, and to perform conjugate complex multiplication on the selected at least two input digital signals to obtain a first output signal; a first signal processing sub-circuit configured to perform logical operation processing on the first output signal to obtain a second output signal; and a second signal processing sub-circuit configured to sequentially perform modulo processing and power difference processing with a reference signal on the second output signal to obtain a synchronization signal.

[0029] This disclosure provides a signal synchronization circuit. The circuit selects and processes multiple input digital signals to obtain a synchronization signal. This synchronization signal is an autocorrelation-based synchronization signal. By using multiplexed adders and multipliers in the first and second signal processing sub-circuits, the circuit area and power consumption are reduced.

[0030] Figure 1 A schematic diagram of a signal synchronization circuit according to an embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, the signal synchronization circuit 100 includes a signal selection sub-circuit 110, a first signal processing sub-circuit 120, and a second signal processing sub-circuit 130.

[0032] The signal selection sub-circuit 110 is configured to select at least two input digital signals from a plurality of input digital signals according to a time series, and to perform conjugate complex multiplication on the selected at least two input digital signals to obtain a first output signal.

[0033] The first signal processing sub-circuit 120 is configured to perform logical operations on the first output signal to obtain the second output signal.

[0034] The second signal processing sub-circuit 130 is configured to sequentially perform modulus-taking processing on the second output signal and power difference processing with the reference signal to obtain a synchronization signal.

[0035] In this embodiment of the disclosure, the time series can be a periodic, cyclical time series. The time series can consist of multiple clock cycles. The digital signals input in each clock cycle can be the same or different.

[0036] For example, multiple input digital signals can be digital signals zc0 to zc12, etc.

[0037] For example, during the first and second clock cycles, the signal selection sub-circuit 110 receives and processes digital signals zc0 and zc12. At other clock cycles, the signal selection sub-circuit 110 receives and processes any two digital signals from zc1 to zc11.

[0038] For example, signal selection sub-circuit 110 may include a data selection unit. This data selection unit is configured to select from multiple input digital signals according to a time series to obtain a selected first digital signal and a second digital signal.

[0039] For example, the signal selection sub-circuit 110 is further configured to perform conjugation processing on the first digital signal to obtain a conjugated first digital signal, and to perform conjugated complex multiplication processing on the second digital signal and the conjugated first digital signal to obtain a first output signal.

[0040] For example, the first signal processing sub-circuit 120 is configured to perform logical operations on the first output signal output by the signal selection sub-circuit 110 to obtain a second output signal.

[0041] For example, the logical operation processing may include logical addition and logical multiplication operations to obtain a second output signal.

[0042] For example, logical addition can be performed by adding the first output signal and the delayed first output signal according to the selection signal.

[0043] For example, selecting signals to match time series.

[0044] For example, logical multiplication can be performed by multiplying the first output signal after addition according to preset multiplication coefficients to obtain the second output signal.

[0045] In this embodiment of the disclosure, the preset multiplication coefficient can be set according to actual needs. For example, the preset multiplication coefficient can be 1489, 1638, 1820, 2048, 2341, 2731, 3277, 4096, 5461, 8192 or 1498, etc.

[0046] For example, the second signal processing sub-circuit 130 is configured to perform normalization processing, modulo processing, and power difference processing with the reference signal on the second output signal output by the first signal processing sub-circuit 120 to obtain the target signal and the synchronization signal.

[0047] For example, the target signal may include the signal used in the frequency offset estimation module and the autocorrelation result signal.

[0048] For example, the second signal processing sub-circuit 130 performs multiple rounding operations on the second output signal to complete the signal normalization process and avoid the influence caused by unnecessary signals.

[0049] According to embodiments of this disclosure, the circuit obtains a synchronization signal by selecting and processing multiple input digital signals. This synchronization signal is an autocorrelation-based synchronization signal, which can be used as a control signal in a communication device to provide a signal for simultaneous time reference.

[0050] Figure 2 A schematic diagram of a signal synchronization circuit according to another embodiment of the present disclosure is shown.

[0051] like Figure 2 As shown, the signal synchronization circuit 200 includes a signal selection sub-circuit 210, a first signal processing sub-circuit 220, and a second signal processing sub-circuit 230. It can be understood that the signal selection sub-circuit 210 and... Figure 1The signal selection sub-circuit 110 shown has the same structure and function. The first signal processing sub-circuit 220 and... Figure 1 The first signal processing sub-circuit 120 shown has the same structure and function. The second signal processing sub-circuit 230 is similar in structure and function to... Figure 1 The second signal processing sub-circuit 130 shown has the same structure and function.

[0052] The input terminal of the signal selection sub-circuit 210 is electrically connected to the output terminal of the random access memory (RAM). The signal selection sub-circuit 210 is configured to select at least two input digital signals from a plurality of input digital signals output from the RAM according to a time sequence, and to perform conjugate complex multiplication on the selected at least two input digital signals to obtain a first output signal.

[0053] The input terminal of the first signal processing sub-circuit 220 is electrically connected to the output terminal of the signal selection sub-circuit 210. The first signal processing sub-circuit 220 is configured to perform logical operations on the first output signal output by the signal selection sub-circuit 210 to obtain a second output signal.

[0054] The input terminal of the second signal processing sub-circuit 230 is electrically connected to the output terminal of the first signal processing sub-circuit 220. The second signal processing sub-circuit 230 is configured to perform normalization processing, modulus-taking processing, and power difference processing with the reference signal sequentially on the second output signal to obtain a synchronization signal.

[0055] In this embodiment of the disclosure, the signal selection sub-circuit 210 includes a data selection unit 211, a conjugate processing unit 212, and a conjugate complex multiplication processing unit 213.

[0056] The input terminal of the data selection unit 211 is electrically connected to the output terminal of the RAM. The data selection unit 211 is configured to select from multiple input digital signals output from the RAM according to a time sequence to obtain a first digital signal and a second digital signal for the current processing cycle.

[0057] For example, the input terminal of the conjugate processing unit 212 is electrically connected to the first output terminal of the data selection unit 211. The conjugate processing unit 212 is configured to perform conjugate processing on the first digital signal to obtain the conjugate-processed first digital signal.

[0058] For example, the first input terminal of the conjugate complex multiplication processing unit 213 is electrically connected to the output terminal of the first conjugate processing unit 212, and the second input terminal of the conjugate complex multiplication processing unit 213 is electrically connected to the second output terminal of the data selection unit 211. The conjugate complex multiplication processing unit 213 is configured to perform conjugate complex multiplication processing on the second digital signal and the first digital signal after conjugate processing to obtain the first output signal.

[0059] In this embodiment of the disclosure, the data selection unit 211 includes a first data selector MUX1, a second data selector MUX2, a third data selector MUX3, a first register ZC0, and a second register ZC12.

[0060] For example, the first data selector MUX1 is configured to receive digital signals zc0 and zc12 from RAM output during the first clock cycle and the second clock cycle, and to output the digital signals zc0 and zc12 to the first register ZC0 and the second register ZC12 respectively for storage, so as to obtain the first target signal zc0 and the fourth target signal zc12.

[0061] For example, the first data selector MUX1 is also configured to receive two digital signals from the digital signals zc1 to zc11 output by the RAM in other clock cycles and output them to obtain the second target signal and the third target signal.

[0062] For example, the second target signal and the third target signal can be any digital signal from zc1 to zc11.

[0063] For example, the amplitude of the first target signal zc0 is different from the amplitude of the fourth target signal zc12.

[0064] For example, the amplitude of the second target signal is the same as the amplitude of the third target signal.

[0065] For example, the second data selector MUX2 is configured to select a first target signal zc0, a second target signal, and a 0 signal based on a time series to obtain a first digital signal.

[0066] For example, in the third clock cycle, the fifth clock cycle, the seventh clock cycle, ..., the twenty-third clock cycle, the second data selector MUX2 is configured to select the first target signal zc0, the second target signal and the 0 signal, and the resulting first digital signal is zc0.

[0067] For example, in the fourth clock cycle, the sixth clock cycle, the eighth clock cycle, ..., the twenty-fourth clock cycle, the second data selector MUX2 is configured to select the first target signal zc0, the second target signal and the 0 signal, and the resulting first digital signal is either the second target signal or the 0 signal.

[0068] For example, in the fourth clock cycle, the second data selector MUX2 is configured to select the first target signal zc0, the second target signal zc11, and the 0 signal according to the first preset signal selection rule, and the resulting first digital signal is the second target signal zc11 or the 0 signal.

[0069] For example, in the sixth clock cycle, the second data selector MUX2 is configured to select the first target signal zc0, the second target signal zc10, and the 0 signal according to the first preset signal selection rule, and the resulting first digital signal is the second target signal zc10 or the 0 signal.

[0070] Similarly, in the twenty-fourth clock cycle, the second data selector MUX2 is configured to select the first target signal zc0, the second target signal zc1, and the 0 signal according to the first preset signal selection rule, and the resulting first digital signal is either the second target signal zc1 or the 0 signal. This process continues in a loop, selecting the digital signal for different clock cycles based on the time sequence.

[0071] For example, the first preset signal selection rule can be to perform an AND operation on each second target signal and digital signal ("0" or "1") in different clock processing cycles, so that the resulting first digital signal is the second target signal or the 0 signal.

[0072] For example, in the fourth clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 11×64. If the counting signal data_cnt is greater than or equal to 11×64, the second target signal zc11 and the digital signal "1" are ANDed to obtain the first digital signal zc11. Conversely, if the counting signal data_cnt is less than 11×64, the second target signal zc11 and the digital signal "0" are ANDed to obtain the first digital signal 0.

[0073] For example, in the sixth clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 10×64. If the counting signal data_cnt is greater than or equal to 10×64, the second target signal zc10 and the digital signal "1" are ANDed to obtain the first digital signal zc10. Conversely, if the counting signal data_cnt is less than 10×64, the second target signal zc10 and the digital signal "0" are ANDed to obtain the first digital signal 0.

[0074] Similarly, in the twenty-fourth clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 1×64. If the counting signal data_cnt is greater than or equal to 1×64, the second target signal zc1 and the digital signal "1" are ANDed to obtain the first digital signal zc1. Conversely, if the counting signal data_cnt is less than 1×64, the second target signal zc1 and the digital signal "0" are ANDed to obtain the first digital signal 0.

[0075] It is understood that a time series can consist of 24 clocks arranged in sequence, or other numbers of clocks, and this disclosure does not limit this.

[0076] For example, the third data selector MUX3 is configured to select the third target signal, the fourth target signal zc12, and the 0 signal according to the time series to obtain the second digital signal.

[0077] For example, in the third clock cycle, the fifth clock cycle, ..., the twenty-third clock cycle, the third data selector MUX3 is configured to select the third target signal, the fourth target signal zc12 and the 0 signal according to the second preset signal selection rule, so as to obtain the second digital signal as the third target signal or the 0 signal.

[0078] In this embodiment of the disclosure, the second preset signal selection rule can be to perform an AND operation on each third target signal and digital signal ("0" or "1") in different clock processing cycles, so that the resulting second digital signal is the third target signal or the 0 signal.

[0079] For example, in the third clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 1×64. If the counting signal data_cnt is greater than or equal to 1×64, the third target signal zc1 and the digital signal "1" are ANDed to obtain the second digital signal zc1. Conversely, if the counting signal data_cnt is less than 1×64, the third target signal zc1 and the digital signal "0" are ANDed to obtain the second digital signal 0.

[0080] For example, in the fifth clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 2×64. If the counting signal data_cnt is greater than or equal to 2×64, the third target signal zc2 and the digital signal "1" are ANDed to obtain the second digital signal zc2. Conversely, if the counting signal data_cnt is less than 2×64, the third target signal zc1 and the digital signal "0" are ANDed to obtain the second digital signal 0.

[0081] For example, in the 23rd clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 11 × 64. If the counting signal data_cnt is greater than or equal to 11 × 64, the third target signal zc11 and the digital signal "1" are ANDed to obtain the second digital signal zc11. Conversely, if the counting signal data_cnt is less than 11 × 64, the third target signal zc11 and the digital signal "0" are ANDed to obtain the second digital signal 0. This process is repeated to select the digital signal for different clock cycles based on the time sequence.

[0082] For example, in the fourth clock cycle, the sixth clock cycle, ..., the twenty-fourth clock cycle, the third data selector MUX3 is configured to select the third target signal, the fourth target signal zc12, and the 0 signal according to the third preset signal selection rule, so as to obtain the second digital signal as the fourth target signal zc12 or the 0 signal.

[0083] In this embodiment of the disclosure, the third preset signal selection rule can be to perform an AND operation on the fourth target signal zc12 and the digital signal ("0" or "1") in different clock processing cycles, so that the resulting second digital signal is the fourth target signal zc12 or the 0 signal.

[0084] For example, in the fourth clock cycle, the sixth clock cycle, ..., the twenty-fourth clock cycle, it is determined whether the counting signal data_cnt is greater than or equal to 12 × 64. If the counting signal data_cnt is greater than or equal to 12 × 64, the fourth target signal zc12 and the digital signal "1" are ANDed to obtain the second digital signal, which is the fourth target signal zc12. Conversely, if the counting signal data_cnt is less than 12 × 64, the fourth target signal zc12 and the digital signal "0" are ANDed to obtain the second digital signal, which is the 0 signal.

[0085] For example, the first input terminal of the conjugate complex multiplication processing unit 213 is electrically connected to the output terminal of the conjugate processing unit 212, and the second input terminal of the conjugate complex multiplication processing unit 213 is electrically connected to the output terminal of the third data selector MUX3. The conjugate complex multiplication processing unit 213 is configured to perform conjugate complex multiplication processing on the second digital signal and the first digital signal after conjugate processing to obtain the first output signal.

[0086] In this embodiment of the disclosure, the signal selection sub-circuit 210 performs conjugate complex multiplication on the input data of the current processing cycle and its sequences with different delays to achieve noise reduction processing of the input signal and enhance the signal.

[0087] According to embodiments of the present disclosure, the first signal processing sub-circuit 220 includes a first addition unit 221, a first signal delay unit 222, and a first multiplication unit 223.

[0088] The first input terminal of the first adder unit 221 is electrically connected to the output terminal of the conjugate complex multiplication processing unit 213, and the second input terminal of the first adder unit 221 is electrically connected to the output terminal of the first signal delay unit 222. The first adder unit 221 is configured to perform logical addition processing on the first output signal and the delayed output signal of the first adder unit according to the selection signal to obtain the first output signal after addition processing.

[0089] The input terminal of the first signal delay unit 222 is electrically connected to the output terminal of the first adder unit 221. The first signal delay unit 222 is configured to delay the output signal of the first adder unit 221 to obtain the delayed output signal of the first adder unit 221.

[0090] The input terminal of the first multiplication unit 223 is electrically connected to the output terminal of the first addition unit 221. The first multiplication unit 223 is configured to perform logical multiplication on the first output signal after addition processing according to preset multiplication coefficients to obtain the second output signal.

[0091] For example, the selection signal is used to determine whether the first adder unit 221 performs logical addition or logical subtraction.

[0092] For example, the selection signal is matched with a clock sequence. The embodiments of this disclosure do not provide detailed descriptions of the selection signal.

[0093] For example, the first signal delay unit 222 may include a fourth data selector MUX4, multiple storage units, and a fifth data selector MUX5.

[0094] For example, the input of the fourth data selector MUX4 is electrically connected to the output of the first adder unit 221, and the multiple outputs of the fourth data selector MUX4 are electrically connected to the inputs of multiple memory units, respectively. The fourth data selector MUX4 is configured to select the output signal of the first adder unit 221 according to the selection signal to obtain the selected output signal.

[0095] For example, there can be 11 storage units, namely Sum0, Sum1, ..., Sum10. These storage units are configured to store the output signals of the fourth data selection unit MUX4 according to the time sequence.

[0096] For example, the outputs of the 11 storage cells Sum0 to Sum11 are electrically connected to multiple inputs of the fifth data selector MUX5.

[0097] For example, the output of the fifth data selector MUX5 is electrically connected to the second input of the first adder unit 221. The fifth data selector MUX5 is configured to select each signal in the plurality of storage sub-units Sum0 to Sum11 according to the selection signal, and output the reselected signal to the first adder unit 221.

[0098] According to embodiments of this disclosure, the first processing sub-circuit accumulates the product results of the conjugate complex multiplication processed signals within the corresponding autocorrelation length. By increasing the clock frequency and adding a data selector to select the corresponding product result, multiple operations are merged into one. This structure reuses the adder, thereby reducing the circuit area and power consumption.

[0099] In this embodiment of the disclosure, the second signal processing sub-circuit 230 includes a first rounding unit RND1, a sixth data selector MUX6, a first branch, a second branch, and a third branch.

[0100] The input terminal of the first rounding unit RND1 is electrically connected to the output terminal of the first multiplication unit 223. The first rounding unit RND1 is configured to perform rounding processing on the second output signal to obtain the rounded second output signal.

[0101] The input of the sixth data selector MUX6 is electrically connected to the output of the first rounding unit RND1. The sixth data selector MUX6 is configured to select the rounded second output signal according to the selection signal to obtain the first output signal Corr_out1, the second output signal, and the third output signal.

[0102] The input of the first branch is electrically connected to the first output of the sixth data selector MUX6. The first branch is configured to perform modulo operation, logical operation, and rounding on the second output signal to obtain the autocorrelation signal Corr_out2.

[0103] The input of the second branch is electrically connected to the second output of the sixth data selector MUX6. The second branch is configured to perform logical operations and rounding on the third output signal, and to perform logical operations on the rounded third output signal and the autocorrelation signal to obtain the synchronization signal Corr_out3.

[0104] The input of the third branch is electrically connected to the third output of the sixth data selector MUX6. The third branch is configured to output the first output signal Corr_out1.

[0105] For example, the first output signal Corr_out1 is used by the frequency offset estimation module to perform frequency offset estimation.

[0106] For example, the first branch includes a modulus-taking unit, a second addition unit, a second signal delay unit, and a second rounding unit RND2.

[0107] The input terminal of the modulus-taking unit is electrically connected to the first output terminal of the sixth data selector MUX6. The modulus-taking unit is configured to perform modulus-taking processing on the second output signal to obtain the modulated second output signal.

[0108] The input terminal of the second adder unit is electrically connected to the output terminal of the modulo-taking unit. The second adder unit is configured to perform an addition operation on the modulo-taken second output signal and the delayed output signal of the second adder unit to obtain the logically operated second output signal.

[0109] The input terminal of the second signal delay unit is electrically connected to the output terminal of the second adder unit. The second signal delay unit is configured to delay the output signal of the second adder unit to obtain the delayed output signal of the second adder unit.

[0110] The input of the second rounding unit RND2 is electrically connected to the output of the second adder unit. The second rounding unit RND2 is configured to round the second output signal after the logical operation to obtain the autocorrelation signal Corr out2.

[0111] For example, the second signal delay unit may include an eighth data selector MUX8 and a register. The eighth data selector MUX8 selects and stores the output signal and the 0 signal of the second adder unit according to the selection signal to obtain the delayed output signal of the second adder unit.

[0112] For example, the second branch includes a second multiplication unit, a third rounding unit RND3, and a third addition unit.

[0113] The input of the second multiplication unit is electrically connected to the second output of the sixth data selector MUX6. The input of the second multiplication unit is configured to perform multiplication operations on the third output signal according to preset multiplication coefficients to obtain the multiplied third output signal.

[0114] For example, the preset multiplication coefficient can be 3932, etc.

[0115] The input of the third rounding unit RND3 is electrically connected to the output of the second multiplication unit. The third rounding unit RND3 is configured to round the third output signal after multiplication to obtain the rounded third output signal.

[0116] For example, the rounded third output signal can be the signal power of the reference signal.

[0117] The input of the third adder unit is electrically connected to the output of the third rounding unit RND3. The third adder unit is configured to perform logical subtraction on the rounded third output signal and the autocorrelation signal Corrout2 to obtain the synchronization signal Corrout3.

[0118] According to embodiments of this disclosure, the second signal processing sub-circuit 330 performs normalization, modulo operation, and power difference processing with the reference path to obtain output signals Corr out1, Corr out2, and Corr out3. Output signal Corr out1 can be used as the input signal for frequency offset estimation by the frequency offset estimation module. Output signal Corr out2 is an autocorrelation signal. Output signal Corr out3 is a synchronization signal, which can be used as a signal providing a common time reference for the communication system.

[0119] It is understood that, in this embodiment of the present disclosure, a peak detection unit can be electrically connected to the output of the third adder unit. The peak value of the output signal Corr out3 is detected by the peak detection unit to obtain the peak point (synchronization point) of the synchronization signal, which is used as the control signal of the communication system.

[0120] Figure 3 A schematic diagram of the structure of a first equivalent circuit according to an embodiment of the present disclosure is shown. It can be understood that the first equivalent circuit 300 can be as follows: Figure 2 The equivalent circuits of the second branches of the signal selection sub-circuit 110, the first signal processing sub-circuit 120, and the second signal processing sub-circuit 130 shown are illustrated. For simplicity, the second branches of the signal selection sub-circuit 110, the first signal processing sub-circuit 120, and the second signal processing sub-circuit 130 will not be described in detail in this disclosure.

[0121] like Figure 3 As shown, Z(K), Z(K-64), Z(K-64×2), Z(K-64×3), ..., Z(K-64×11), Z(K-64×12) represent the signals output after selection by the data selection unit in the zero clock cycle (i.e., during circuit reset), the first clock cycle, the second clock cycle, ..., the eleventh clock cycle, and the twelfth clock cycle, respectively. K can take the value 64×12, where K is an integer.

[0122] For example, Z -1 This indicates signal delay processing.

[0123] For example, k1, k2, k3, ..., k11 represent the multiplication coefficients. k1 to k11 take different values.

[0124] For example, k1 to k11 can take one of the following values: 1489, 1638, 1820, 2048, 2341, 2731, 3277, 4096, 5461, 8192, and 1498.

[0125] For example, the first input digital signal selected by the data selection unit in the first clock cycle is Z(K). After the first input digital signal Z(K) is conjugate processed, it is multiplied by the second input digital signal Z(K-64) selected by the data selection unit in the second clock cycle to obtain the first output signal Z1.

[0126] For example, the eleventh input digital signal after being selected by the data selection unit in the eleventh clock cycle is Z(K-64×11). The eleventh input digital signal Z(K-64×11) is conjugate processed and then multiplied with the twelfth input digital signal Z(K-64×12) after being selected by the data selection unit in the twelfth clock cycle to obtain the first output signal Z2.

[0127] It can be understood that the first output signal Z2 is used to control the logic operation of the first adder to be either addition or subtraction.

[0128] For example, when the first output signal Z2 indicates that the logic operation of the first adder is subtraction, the first output signal Z1 is logically subtracted from the first output signal after delay processing, and the first output signal after logical subtraction is logically multiplied (multiplication coefficient is k1) to obtain the second output signal Z.

[0129] For example, the second output signal Z is normalized and moduloed sequentially, and then input to the second adder.

[0130] It should be noted that the signal processing process of each equivalent branch in the first equivalent circuit is the same, except that the digital signal selected by the data selection unit and the coefficient k of the multiplication process are different. The embodiments of this disclosure will not describe the signal processing process of other equivalent branches one by one.

[0131] According to the embodiments of this disclosure, and in conjunction with the first equivalent circuit, it can be seen that the signal synchronization circuit provided by this disclosure multiplies the current input data with the conjugate complex of its sequences with different delays. By increasing the clock frequency, the multipliers of different branches can be shared, thereby reducing the circuit area and power consumption.

[0132] Figure 4 A schematic diagram of a second equivalent circuit according to an embodiment of the present disclosure is shown. It will be understood that the second equivalent circuit 400 can be as follows: Figure 2 The equivalent circuit of the third branch of the signal selection sub-circuit 110, the first signal processing sub-circuit 120, and the second signal processing sub-circuit 130 shown is illustrated. For simplicity, the third branch of the signal selection sub-circuit 110, the first signal processing sub-circuit 120, and the second signal processing sub-circuit 130 will not be described in detail in this disclosure.

[0133] like Figure 4 As shown, the input digital signal Z(K) and input digital signal Z(K-64) selected by the data selection unit are subjected to modulo processing respectively, and the two modulo-processed signals Z0 and Z1 are subjected to logical addition to obtain the output signal Z.

[0134] For example, the output signal Z is sequentially processed by shifting, logical operation, rounding, logical multiplication, and rounding again to obtain the synchronization signal Corr_out3.

[0135] According to the embodiments of this disclosure, and in conjunction with the second equivalent circuit, it can be seen that the signal synchronization circuit provided by this disclosure accumulates the product results within the corresponding autocorrelation length. By increasing the clock frequency and adding a data selector MUX to select the corresponding product results, the original multiple branches are merged into one branch. This structure reuses the adder, thereby reducing the circuit area and power consumption.

[0136] Figure 5 A flowchart of a synchronization signal generation method according to an embodiment of the present disclosure is shown. Figure 5 As shown, the synchronization signal generation method according to embodiments of this disclosure may include the following steps. It should be noted that the sequence numbers of each step in the following methods are for descriptive purposes only and should not be considered as indicating the execution order of the steps. Unless explicitly stated otherwise, the method need not be performed in the exact order shown.

[0137] like Figure 5 As shown, the synchronization signal generation method 500 is applied to a signal synchronization circuit and includes steps S510 to S530. It can be understood that this method can be applied to, for example... Figure 1 The signal synchronization circuit is shown. For the sake of simplicity, the signal synchronization circuit will not be described in detail in this disclosure.

[0138] In step S510, at least two input digital signals are selected from multiple input digital signals according to the time series, and the selected at least two input digital signals are subjected to conjugate complex multiplication to obtain a first output signal.

[0139] It is understandable that step S510 can be performed by... Figure 1 The signal selection sub-circuit shown or Figure 2 The signal selection sub-circuit shown is executed. For simplicity, this disclosure... Figure 1 The signal selection sub-circuit shown and Figure 2 The signal selection sub-circuit shown will not be described in detail.

[0140] In step S520, the first output signal is processed by logical operation to obtain the second output signal.

[0141] It is understandable that step S520 can be performed by... Figure 1 The first signal processing sub-circuit shown or Figure 2 The first signal processing sub-circuit shown is executed. For simplicity, this disclosure... Figure 1 The first signal processing sub-circuit shown and Figure 2 The first signal processing sub-circuit shown will not be described in detail.

[0142] In step S530, the second output signal is sequentially subjected to modulus extraction and power difference processing with the reference signal to obtain a synchronization signal.

[0143] It is understandable that step S530 can be performed by... Figure 1 The second signal processing sub-circuit shown or Figure 2 The second signal processing sub-circuit shown is executed. For simplicity, this disclosure... Figure 1 The second signal processing sub-circuit shown and Figure 2 The second signal processing sub-circuit shown will not be described in detail.

[0144] Figure 6 A schematic diagram of the structure of a communication device according to an embodiment of the present disclosure is shown.

[0145] like Figure 6 As shown, the communication device 600 includes a signal synchronization circuit 610.

[0146] It is understandable that the signal synchronization circuit 610 and such Figure 1 The signal synchronization circuit 100 shown and as follows Figure 2 The signal synchronization circuit 200 shown has the same structure. For the sake of simplicity, the signal synchronization circuit will not be described in detail in this disclosure.

[0147] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0148] Although this disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above embodiments, but should be defined not only by the appended claims, but also by their equivalents.

Claims

1. A signal synchronization circuit, comprising: The signal selection sub-circuit is configured to select at least two input digital signals from a plurality of input digital signals according to a time series, and to perform conjugate complex multiplication on the selected at least two input digital signals to obtain a first output signal; The first signal processing sub-circuit is configured to perform logical operations on the first output signal to obtain the second output signal; as well as The second signal processing sub-circuit is configured to sequentially perform modulus-taking processing on the second output signal and power difference processing with the reference signal to obtain a synchronization signal; The signal selection sub-circuit includes: The data selection unit is configured to select from the plurality of input digital signals according to the time series to obtain a first digital signal and a second digital signal for the current processing cycle; A conjugation processing unit is configured to perform conjugation processing on the first digital signal to obtain a conjugated first digital signal; and The conjugate complex multiplication processing unit is configured to perform conjugate complex multiplication processing on the first digital signal and the second digital signal after conjugate processing to obtain the first output signal; The first signal processing sub-circuit includes: The first addition unit is configured to perform addition operations on the first output signal and the delayed output signal of the first addition unit according to a selection signal, to obtain the first output signal after addition processing; and The first multiplication unit is configured to perform multiplication operations on the first output signal after addition processing according to preset multiplication coefficients to obtain the second output signal; The second signal processing sub-circuit includes: The first rounding unit is configured to perform rounding on the second output signal to obtain the rounded second output signal. The sixth data selector is configured to select the rounded second output signal according to the selection signal to obtain a first output signal, a second output signal and a third output signal; The first branch is configured to perform modulo operation, logical operation, and rounding on the second output signal to obtain an autocorrelation signal; and The second branch is configured to perform logical operations and rounding on the third output signal, and to perform logical operations on the rounded third output signal and the autocorrelation signal to obtain the synchronization signal.

2. The circuit according to claim 1, wherein, The data selection unit includes: A first data selector is configured to select from the plurality of input digital signals according to the time series to obtain a first target signal, a second target signal, a third target signal, and a fourth target signal; A second data selector is configured to select from the first target signal, the second target signal, and the 0 signal according to the time series to obtain the first digital signal; and The third data selector is configured to select the third target signal, the fourth target signal, and the 0 signal according to the time series to obtain the second digital signal.

3. The circuit according to claim 1, wherein, The first signal processing sub-circuit further includes: The first signal delay unit is configured to delay the output signal of the first adder unit to obtain the delayed output signal of the first adder unit.

4. The circuit according to claim 3, wherein, The first signal delay unit includes: The fourth data selector is configured to select the output signal of the first adder unit according to the selection signal to obtain the selected output signal; Multiple storage units are configured to store the output signals of the fourth data selector according to a time series; and The fifth data selector is configured to select each signal in the plurality of storage units according to the selection signal, and output the selected signal to the first adder unit.

5. The circuit according to claim 1, wherein, The first branch includes: The modulus unit is configured to perform modulus processing on the second output signal to obtain the modulus-processed second output signal; The second addition unit is configured to perform an addition operation on the modulo-taken second output signal and the delayed output signal of the second addition unit to obtain a logically operated second output signal; and The second rounding unit is configured to round the second output signal after the logical operation to obtain the autocorrelation signal.

6. The circuit according to claim 1, wherein, The second branch includes: The second multiplication unit is configured to perform multiplication operations on the third output signal according to preset multiplication coefficients to obtain the multiplied third output signal. The third rounding unit is configured to round the third output signal after the multiplication process to obtain the rounded third output signal; and The third addition unit is configured to perform a subtraction operation on the rounded third output signal and the autocorrelation signal to obtain the synchronization signal.

7. The circuit according to claim 1, wherein, The second signal processing sub-circuit also includes: The third branch is configured to output the first output signal.

8. A method for generating a synchronization signal, the method being applied to a signal synchronization circuit as described in any one of claims 1 to 7, comprising: Based on the time series, at least two input digital signals are selected from multiple input digital signals, and the selected at least two input digital signals are subjected to conjugate complex multiplication to obtain the first output signal; The first output signal is processed by logical operations to obtain the second output signal; The second output signal is sequentially subjected to modulus extraction and power difference processing with the reference signal to obtain a synchronization signal.

9. A communication device, comprising: The signal synchronization circuit as described in any one of claims 1 to 7.

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