Wake-up circuit and processing circuit

Abstract

The present application provides a wake-up circuit and a processing circuit. The wake-up circuit is used to generate a wake-up signal and an interrupt signal, and includes a detection circuit, a first logic circuit, a synchronization circuit, a flip-flop and a second logic circuit. When a wake-up event occurs and a first set signal is enabled, the detection circuit enables a detection signal. When the detection signal and a low power signal are enabled, the first logic circuit enables the wake-up signal. The synchronization circuit generates a synchronization signal according to the detection signal. An edge of the synchronization signal is aligned with an edge of an operation clock. When the synchronization signal is enabled, the flip-flop enables an output signal. When the output signal and a second set signal are enabled, the second logic circuit enables the interrupt signal.

Description

Technical Field

[0001] This invention relates to a wake-up circuit, and more particularly to a wake-up circuit that enables a wake-up signal when a wake-up event occurs. Background Technology

[0002] With the advancement of technology, electronic devices are becoming increasingly diverse in type and function. Most electronic devices have a built-in rechargeable battery to power their internal components. To reduce battery consumption, electronic devices may automatically enter a power-saving mode when the user has not used them for a period of time. However, if a wake-up event occurs during the transition from a normal mode to a power-saving mode, the electronic device may not be able to detect the wake-up event in time. Summary of the Invention

[0003] An embodiment of the present invention provides a wake-up circuit for generating a wake-up signal and an interrupt signal, and includes a detection circuit, a first logic circuit, a synchronization circuit, a flip-flop, and a second logic circuit. When a wake-up event occurs and a first setting signal is enabled, the detection circuit enables a detection signal. When the detection signal and an offline signal are enabled, the first logic circuit enables the wake-up signal. The synchronization circuit generates a synchronization signal based on the detection signal. The edge of the synchronization signal is aligned with the edge of an operating clock. When the synchronization signal is enabled, the flip-flop enables an output signal. When the output signal and a second setting signal are enabled, the second logic circuit enables the interrupt signal.

[0004] Another embodiment of the present invention provides a processing circuit including an operating system and a wake-up circuit. The wake-up circuit provides a wake-up signal and an interrupt signal to the operating system. The wake-up circuit includes a detection circuit, a first logic circuit, a synchronization circuit, a flip-flop, and a second logic circuit. When a wake-up event occurs and a first setting signal is enabled, the detection circuit enables a detection signal. When the detection signal and a power-down signal are enabled, the first logic circuit enables a wake-up signal to wake up the operating system. The synchronization circuit generates a synchronization signal based on the detection signal. The edge of the synchronization signal is aligned with the edge of an operating clock. When the synchronization signal is enabled, the flip-flop enables a first output signal. When the first output signal and a second setting signal are enabled, the second logic circuit enables an interrupt signal.

[0005] Because the trigger's setting terminal receives the trigger signal, the wake-up circuit can immediately detect any wake-up event, regardless of whether the external operating system is operating in a normal mode, a power-saving mode (sleep mode), or at the boundary between normal and power-saving modes. It then determines whether to enable the wake-up signal based on the setting signal. The interrupt signal is enabled later than the wake-up signal, thus ensuring that the operating system does not miss interrupt signals. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the processing circuit of the present invention.

[0007] Figure 2 This is a schematic diagram of the wake-up circuit of the present invention.

[0008] Figure 3 This is another schematic diagram of the wake-up circuit of the present invention.

[0009] Figure 4 This is another schematic diagram of the wake-up circuit of the present invention.

[0010] Figure 5 This is a schematic diagram of the detection circuit of the present invention.

[0011] Attached icon number

[0012] 100: Processing circuit

[0013] 110, 200, 300, 400: Wake-up circuit

[0014] 120: Operating System

[0015] 121: Power Management Circuit

[0016] 122: Central Processing Unit

[0017] 123: Clock Generation Circuit

[0018] WKUP: Wake-up signal

[0019] INT: Interrupt signal

[0020] CKO: Clock signal

[0021] sig: trigger signal

[0022] wken: Set signal

[0023] INTEN: Setting signal

[0024] Sw_clr: Clear signal

[0025] PWR_DN: Power-down signal

[0026] PW1, PW2: Operating voltage

[0027] 205, 210, 305, 310, 405A, 405B, 410A, 410B, 500: Detection circuit

[0028] 220, 320, 420A, 420B: Synchronization circuit

[0029] 230, 330, 430A, 430B, 530: Triggers

[0030] 240, 250, 340, 350, 360, 440, 450, 460A, 460B, 470, 480, 540: Logic circuits

[0031] SD, SDA, SDB: Detection signals

[0032] SS, SSA, SSB: Synchronization signals

[0033] SO1, SO1A, SO1B, SO2A, SO2B: Output signals

[0034] clk: clock signal

[0035] SI, SIA, SIB: Input signals

[0036] 510: Multiplexer

[0037] 520: Switching Circuit

[0038] VL: Preset Level Detailed Implementation

[0039] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0040] Figure 1 This is a schematic diagram of the processing circuit of the present invention. The processing circuit 100 includes a wake-up circuit 110 and an operating system 120. The wake-up circuit 110 detects whether a wake-up event has occurred. When a wake-up event occurs, the wake-up circuit 110 enables a wake-up signal WKUP. In other embodiments, after enabling the wake-up signal WKUP, the wake-up circuit 110 further enables an interrupt signal INT. In this example, the wake-up circuit 110 may generate the interrupt signal INT based on a clock signal CKO provided by the operating system 120. Therefore, the edge (e.g., rising edge) of the interrupt signal INT is aligned with the edge (e.g., rising or falling edge) of the clock signal CKO.

[0041] This invention does not limit the types of wake-up events. In one possible embodiment, a wake-up event occurs when a specific button (not shown) is pressed. In this example, no wake-up event occurs when the specific button is not pressed. In another possible embodiment, a wake-up event occurs when a specific element (not shown) completes its operation. However, no wake-up event occurs when the specific element has not yet completed its operation. For example, a wake-up event occurs when a counter completes a counting operation. In this example, no wake-up event occurs when the counter has not yet completed its counting operation.

[0042] This invention does not limit how the wake-up circuit 110 detects whether a wake-up event has occurred. In one possible embodiment, the wake-up circuit 110 determines whether a wake-up event has occurred based on the level of the trigger signal sig. For example, if the level of the trigger signal sig does not meet a preset value, it indicates that no wake-up event has occurred. Therefore, the wake-up circuit 110 does not enable the wake-up signal WKUP. However, if the level of the trigger signal sig meets a preset value, it indicates that a wake-up event has occurred. The wake-up circuit 110 enables the wake-up signal WKUP.

[0043] In some embodiments, the level of the trigger signal sig is related to the state of a specific key. For example, when the specific key is not pressed, the level of the trigger signal sig is not equal to a preset value. However, when the key is pressed, the level of the trigger signal sig is equal to a preset value. In other embodiments, the level of the trigger signal sig is related to the output signal of a specific element. For example, when the specific element completes its action, the specific element may enable a completion signal. When the specific element has not yet completed its action, the specific element does not enable a completion signal. In this example, the completion signal serves as the trigger signal sig.

[0044] In other embodiments, the wake-up circuit 110 further determines whether to enable the wake-up signal WKUP based on a setting signal wken. In this example, the user may set the level of the setting signal wken through software or hardware architecture. When the setting signal wken is set to a first specific level (such as a low level), it indicates that the user does not want to wake up the operating system 120. Therefore, even if a wake-up event occurs, the wake-up circuit 110 does not enable the wake-up signal WKUP. However, when the setting signal wken is not equal to the first specific level, it indicates that the user wants to wake up the operating system 120 when a wake-up event occurs. Therefore, when a wake-up event occurs, the wake-up circuit 110 enables the wake-up signal WKUP.

[0045] In another possible embodiment, the wake-up circuit 110 determines whether to enable the interrupt signal INT based on a setting signal INTEN. In this example, the user may set the level of the interrupt signal INT through software or hardware architecture. For instance, when the setting signal INTEN is set to a second specific level (such as a low level), even if the wake-up circuit 110 enables the wake-up signal WKUP, the wake-up circuit 110 does not enable the interrupt signal INT. However, when the setting signal INTEN is not equal to the second specific level, it indicates that the user wants the wake-up circuit 110 to enable the interrupt signal INT after enabling the wake-up signal WKUP. Therefore, when a wake-up event occurs, the wake-up circuit 110 first enables the wake-up signal WKUP and then enables the interrupt signal INT.

[0046] In some embodiments, the wake-up circuit 110 clears previously recorded wake-up events based on a clear signal Sw_clr. In this example, when the clear signal Sw_clr is equal to a third specific level (e.g., a high level), the wake-up circuit 110 resets the wake-up signal WKUP. At this time, the wake-up signal WKUP is equal to an initial value, such as a low level. When the clear signal Sw_clr is not equal to the third specific level, the wake-up circuit 110 determines whether to enable the wake-up signal WKUP based on the level of the trigger signal sig. In one possible embodiment, when the wake-up circuit 110 enables the wake-up signal WKUP, the wake-up signal WKUP is equal to a high level. In this example, when the wake-up circuit 110 does not enable the wake-up signal WKUP, the wake-up signal WKUP is equal to a low level.

[0047] In other embodiments, the wake-up circuit 110 determines whether to enable the wake-up signal WKUP based on the power-down signal PWR_DN. For example, when the operating voltage of the operating system 120 is equal to a target value, it indicates that the operating system 120 is in a power-up state. When the operating voltage of the operating system 120 is lower than a threshold value, it indicates that the operating system 120 is in a power-down state. In this example, the power-down signal PWR_DN indicates whether the operating system 120 is in a power-down state. In one possible embodiment, when the power-down signal PWR_DN is equal to a fourth specific level (e.g., a low level), it indicates that the operating system 120 is in a power-up state. At this time, even if a wake-up event occurs, the wake-up circuit 110 does not enable the wake-up signal WKUP and the interrupt signal INT. However, when the power-down signal PWR_DN is not equal to the fourth specific level, it indicates that the operating system 120 is in a power-down state. At this time, the wake-up circuit 110 enables the wake-up signal WKUP and the interrupt signal INT based on the level of the trigger signal sig.

[0048] Operating system 120 receives a wake-up signal WKUP and an interrupt signal INT. After executing a power-down command, operating system 120 may leave normal mode and enter a power-saving mode. At the transition between normal mode and power-saving mode, if a wake-up event occurs, operating system 120 may not be able to detect the wake-up event. Therefore, by using wake-up circuit 110 to detect whether a wake-up event has occurred, it can be ensured that no wake-up event is missed. In this embodiment, wake-up circuit 110 does not detect wake-up events based on any clock signal. Since wake-up circuit 110 detects wake-up events asynchronously, whether operating system 120 has officially entered power-saving mode or is at the transition between normal mode and power-saving mode, wake-up circuit 110 will not miss any wake-up events and will wake up operating system 120 immediately when a wake-up event occurs. After operating system 120 is woken up, operating system 120 executes an interrupt routine based on interrupt signal INT.

[0049] This invention does not limit the architecture of the operating system 120. In one possible embodiment, the operating system 120 includes a power management circuit 121. The power management circuit 121 receives a wake-up signal WKUP. When the power management circuit 121 operates in a first normal mode, it provides an operating voltage PW1. At this time, the operating voltage PW1 is equal to a first target value. When the power management circuit 121 enters a first sleep mode, it reduces the operating voltage PW1. At this time, the operating voltage PW1 is lower than the first target value. In the first sleep mode, when the wake-up signal WKUP is enabled, the power management circuit 121 leaves the first sleep mode and enters a first normal mode. In other embodiments, when the power management circuit 121 enters the first sleep mode, it may stop providing the operating voltage PW1.

[0050] This invention does not limit the architecture of the power management circuit 121. The power management circuit 121 may have multiple power supply circuits to provide multiple operating voltages. In other embodiments, the power-down signal PWR_DN is enabled after the power management circuit 121 enters a first sleep mode and completes the reduction operation of the operating voltage PW1.

[0051] In other embodiments, the operating system 120 further includes a central processing unit (CPU) 122. The CPU 122 receives an operating voltage PW1 and an interrupt signal INT. When the operating voltage PW1 equals a first target value, the CPU 122 operates in a second normal mode. When the operating voltage PW1 falls below a first threshold value, the CPU 122 exits the second normal mode and enters a second sleep mode. In the second sleep mode, the CPU 122 may cease operation. However, when the operating voltage PW1 rises back to the first target value, the CPU 122 exits the second sleep mode and enters the second normal mode. In the second normal mode, when the interrupt signal INT is enabled, the CPU 122 executes the corresponding interrupt routine.

[0052] In some embodiments, the CPU 122 directly receives the wake-up signal WKUP. In this example, the CPU 122 controls the power management circuit 121 according to the wake-up signal WKUP. For instance, when the CPU 122 executes a power-saving instruction, the CPU 122 may command the power management circuit 121 to enter a first sleep mode. At this time, the power management circuit 121 reduces the operating voltage PW1. When the operating voltage PW1 is lower than a first threshold value, the CPU 122 enters a second sleep mode. When the wake-up signal WKUP is enabled, the CPU 122 wakes up the power management circuit 121. Therefore, the power management circuit 121 leaves the first sleep mode and enters a first normal mode. At this time, the power management circuit 121 increases the operating voltage PW1. When the operating voltage PW1 reaches a first target value, the CPU 122 leaves the second sleep mode and enters a second normal mode. In the second normal mode, when the interrupt signal INT is enabled, the CPU 122 executes the corresponding interrupt routine.

[0053] In other embodiments, the operating system 120 further includes a clock generation circuit 123. The clock generation circuit 123 generates a clock signal CKO. In this example, the power management circuit 121 provides an operating voltage PW2 to the clock generation circuit 123. When the operating voltage PW2 equals a second target value, the clock generation circuit 123 operates in a third normal mode. In the third normal mode, the clock signal CKO provided by the clock generation circuit 123 has a first frequency. However, when the power management circuit 121 enters a first sleep mode, the power management circuit 121 reduces the operating voltage PW2. Therefore, the clock generation circuit 123 reduces the clock signal CKO and enters a third sleep mode. At this time, the clock signal CKO has a second frequency. The second frequency is lower than the first frequency. In other embodiments, in the third sleep mode, the clock generation circuit 123 stops providing the clock signal CKO. When the power management circuit 121 enters the first normal mode, the power management circuit 121 increases the operating voltage PW2. Therefore, the clock generation circuit 123 leaves the third sleep mode and enters the third normal mode. In the third normal mode, the clock generation circuit 123 increases the frequency of the clock signal CKO so that the frequency of the clock signal CKO is equal to the first frequency.

[0054] In some embodiments, the clock generating circuit 123 directly receives the wake-up signal WKUP. In this example, when the wake-up signal WKUP is enabled, the clock generating circuit 123 leaves the third sleep mode and enters the third normal mode. In other embodiments, the clock generating circuit 123 provides a clock signal (not shown) to the power management circuit 121. In this example, the power management circuit 121 may adjust at least one of the operating voltages PW1 and PW2 according to the clock signal provided by the clock generating circuit 123.

[0055] Figure 2 This is a schematic diagram of the wake-up circuit of the present invention. The wake-up circuit 200 includes detection circuits 205 and 210, a synchronization circuit 220, a trigger 230, and logic circuits 240 and 250. Detection circuit 205 is used to detect whether a wake-up event has occurred and control the level of trigger signal sig according to the detection result. For example, when a wake-up event occurs, detection circuit 205 sets the level of trigger signal sig to be equal to a preset value (such as a high level). When a wake-up event does not occur, detection circuit 205 sets the level of trigger signal sig to be different from a preset value. In this case, detection circuit 205 may set the level of trigger signal sig to be equal to a low level. In one possible embodiment, the wake-up event is the pressing of a specific key or the completion of its operation by a specific element.

[0056] In some embodiments, the detection circuit 205 determines whether a wake-up event has occurred based on the frequency of an operating clock. For example, when the frequency of the operating clock is equal to a preset frequency, it indicates that a wake-up event has occurred. Therefore, the detection circuit 205 sets the level of the trigger signal sig to be equal to a preset value. When the frequency of the operating clock is not equal to the preset frequency, it indicates that no wake-up event has occurred. Therefore, the detection circuit 205 sets the level of the trigger signal sig to be not equal to the preset value.

[0057] The detection circuit 210 enables the detection signal SD based on the level of the trigger signal sig. For example, when the level of the trigger signal sig does not meet a preset value, it indicates that no wake-up event has occurred. Therefore, the detection circuit 210 does not detect the signal SD. However, when the level of the trigger signal sig meets a preset value, it indicates that a wake-up event has occurred. Therefore, the detection circuit 210 determines whether to detect the signal SD based on the setting signal wken. In this example, when the setting signal wken is equal to a first specific level (e.g., low level), the detection circuit 210 does not detect the signal SD even if the level of the trigger signal sig meets a preset value. At this time, the detection circuit 210 may set the detection signal SD to a low level. However, when the setting signal wken is not equal to the first specific level and the level of the trigger signal sig meets a preset value, the detection circuit 210 enables the detection signal SD. At this time, the detection circuit 210 may set the detection signal SD to a high level.

[0058] Logic circuit 240 enables the wake-up signal WKUP based on the detection signal SD and the power-down signal PWR_DN. For example, when the detection signal SD and the power-down signal PWR_DN are enabled, logic circuit 240 enables the wake-up signal WKUP. When the detection signal SD or the power-down signal PWR_DN is not enabled, logic circuit 240 does not enable the wake-up signal WKUP. This invention does not limit the architecture of logic circuit 240. In one possible embodiment, logic circuit 240 is an AND gate.

[0059] Synchronization circuit 220 generates a synchronization signal SS based on the detection signal SD. In one possible embodiment, the rising edge of the synchronization signal SS is aligned with the edge (such as a rising edge or a falling edge) of the operating clock CKO. In this embodiment, since the interrupt signal INT is provided to the central processing unit 122, the synchronization circuit 220 processes the detection signal SD according to the operating clock CKO of the central processing unit 122, such that the edge of the processed detection signal SD (i.e., the synchronization signal SS) is aligned with the edge of the operating clock CKO.

[0060] When the synchronization signal SS is enabled, flip-flop 230 enables an output signal SO1. In other embodiments, flip-flop 230 further receives a clear signal Sw_clr. When the clear signal Sw_clr is equal to a third specific level (e.g., high), flip-flop 230 resets the output signal SO1. At this time, the output signal SO1 may be equal to a low level. When the clear signal Sw_clr is not equal to the third specific level, flip-flop 230 determines whether to enable the output signal SO1 based on the synchronization signal SS. For example, when the synchronization signal SS is high, flip-flop 230 enables the output signal SO1. At this time, the output signal SO1 may be high.

[0061] Logic circuit 250 enables the interrupt signal INT based on the output signal SO1 and the setting signal INTEN. For example, when the output signal SO1 and the setting signal INTEN are enabled, logic circuit 250 enables the interrupt signal INT. However, when the output signal SO1 or the setting signal INTEN is not enabled, logic circuit 250 does not enable the interrupt signal INT. This invention does not limit the architecture of logic circuit 250. In one possible embodiment, logic circuit 250 is an AND gate.

[0062] Figure 3 This is another schematic diagram of the wake-up circuit of the present invention. Figure 3 resemblance Figure 2 The difference is that, Figure 3 The wake-up circuit has 300 more logic circuits than 360. Because... Figure 3 The characteristics of the detection circuits 305 and 310, the synchronization circuit 320, the flip-flop 330, and the logic circuits 340 and 350 are similar to those of... Figure 2 The characteristics of the detection circuits 205 and 210, the synchronization circuit 220, the flip-flop 230, and the logic circuits 240 and 250 are not described in detail here.

[0063] In this embodiment, logic circuit 360 generates an input signal SI for synchronization circuit 320. In this example, logic circuit 360 enables input signal SI when the level of trigger signal sig meets a preset value or when detection signal SD is enabled. At this time, input signal SI may be high. When the level of trigger signal sig does not meet the preset value and detection signal SD is not enabled, logic circuit 360 does not enable input signal SI. At this time, input signal SI may be low. Synchronization circuit 320 processes input signal SI to generate synchronization signal SS. In this example, the edge of synchronization signal SS is aligned with the edge of operating clock CKO. The present invention does not limit the architecture of logic circuit 360. In one possible embodiment, logic circuit 360 is an OR gate.

[0064] Figure 4This is another schematic diagram of the wake-up circuit of the present invention. In this embodiment, the wake-up circuit includes detection circuits 405A, 405B, 410A, 410B, synchronization circuits 420A, 420B, triggers 430A, 430B, and logic circuits 440, 450, 460A, 460B, 470, and 480. Detection circuit 405A detects whether a first wake-up event has occurred. In one possible embodiment, detection circuit 405A detects the voltage level of an input / output pad. When the voltage level of the input / output pad is not equal to a specific level, it indicates that a first wake-up event has occurred. Therefore, detection circuit 405A sets the level of trigger signal siga to be equal to a preset value. However, when the voltage level of the input / output pad is equal to the specific level, it indicates that the first wake-up event has not occurred. Therefore, detection circuit 405A sets the level of trigger signal siga to be not equal to the preset value.

[0065] Logic circuit 460A generates an input signal SIA based on the trigger signal siga and the detection signal SDA. Synchronization circuit 420A synchronizes the input signal SIA with the operating clock CKO to generate a synchronization signal SSA. Flip-flop 430A generates an output signal SO1A based on the synchronization signal SSA. Flip-flop 430A sets the level of the output signal SO1A based on the clear signal Sw_clr. Due to the characteristics of logic circuit 460A, synchronization circuit 420A, and flip-flop 430A... Figure 3 The characteristics of the logic circuit 360, the synchronous circuit 320 and the flip-flop 330 are similar, so they will not be described in detail.

[0066] The detection circuit 405B detects whether a second wake-up event has occurred. In one possible embodiment, the detection circuit 405B detects the frequency of the operating clock CKO. In this example, a second wake-up event is indicated when the frequency of the operating clock is equal to a preset frequency. Therefore, the detection circuit 405B sets the level of the trigger signal sigb to equal a preset value. When the frequency of the operating clock is not equal to a preset frequency, it indicates that a second wake-up event has not occurred. Therefore, the detection circuit 405B sets the level of the trigger signal sigb to not equal to the preset value.

[0067] Logic circuit 460B generates an input signal SIB based on the trigger signal sigb and the detection signal SDB. Synchronization circuit 420B synchronizes the input signal SIB with the operating clock CKO to generate a synchronization signal SSB. Flip-flop 430B generates an output signal SO1B based on the synchronization signal SSB. Flip-flop 430B sets the level of the output signal SO1B based on the clear signal Sw_clr. Due to the characteristics of logic circuit 460B, synchronization circuit 420B, and flip-flop 430B... Figure 3The characteristics of the logic circuit 360, the synchronous circuit 320 and the flip-flop 330 are similar, so they will not be described in detail.

[0068] Logic circuit 470 receives detection signals SDA and SDB. When either detection signal SDA or SDB is enabled, logic circuit 470 enables output signal SO2A. When neither detection signal SDA nor SDB is enabled, logic circuit 470 disables output signal SO2A. This invention does not limit the type of logic circuit 470. In one possible embodiment, logic circuit 470 is an OR gate.

[0069] Logic circuit 480 receives output signals SO1A and SO1B. When one of the output signals SO1A and SO1B is enabled, logic circuit 480 enables output signal SO2B. When neither output signal SO1A nor SO1B is enabled, logic circuit 480 disables output signal SO2B. This invention does not limit the type of logic circuit 480. In one possible embodiment, logic circuit 480 is an OR gate.

[0070] Logic circuit 440 enables the wake-up signal WKUP based on the output signal SO2A and the power-down signal PWR_DN. Logic circuit 450 enables the interrupt signal INT based on the output signal SO2B and the setting signal INTEN. Due to the characteristics of logic circuits 440 and 450... Figure 2 The characteristics of logic circuits 240 and 250 are similar, so they will not be described in detail here.

[0071] In this embodiment, detection circuits 405A and 405B detect different wake-up events. When any wake-up event detected by detection circuits 405A and 405B occurs, wake-up circuit 400 enables wake-up signal WKUP and interrupt signal INT. This invention does not limit the number of wake-up events. In other embodiments, wake-up circuit 400 detects more wake-up events.

[0072] Figure 5 This is a schematic diagram of the detection circuit of the present invention. The detection circuit 500 includes a multiplexer 510, a switching circuit 520, a flip-flop 530, and a logic circuit 540. The multiplexer 510 has input terminals IN1 and IN2. Input terminal IN1 is coupled to the output terminal Q of the flip-flop 530. Input terminal IN2 receives a preset level VL. In this embodiment, the preset level VL is a low level. The multiplexer 510 outputs the signal of input terminal IN1 or IN2 to the flip-flop 530 according to the clear signal Sw_clr. For example, when the clear signal Sw_clr is enabled, the multiplexer 510 outputs the signal of input terminal IN2. When the clear signal Sw_clr is not enabled, the multiplexer 510 outputs the signal of input terminal IN1.

[0073] Switching circuit 520 receives a clock signal clk and is coupled to the clock input CK of flip-flop 530. When the clear signal Sw_clr is enabled, switching circuit 520 outputs the clock signal clk to the clock input CK. When the clear signal Sw_clr is not enabled, switching circuit 520 stops outputting the clock signal clk to the clock input CK. In one possible embodiment, switching circuit 520 is an integrated clock gating (ICG).

[0074] In this embodiment, the trigger 530 is a D-type trigger. The trigger 530 has an input terminal D, an output terminal Q, a clock terminal CK, and a setting terminal SET. The input terminal D of the trigger 530 is coupled to the output terminal of the multiplexer 510. The output terminal Q of the trigger 530 is coupled to the input terminal IN1 of the multiplexer 510. The clock terminal CK of the trigger 530 is coupled to the output terminal of the switching circuit 520 to receive the clock signal clk. The setting terminal SET of the trigger 530 receives the trigger signal sig.

[0075] When the trigger signal sig is enabled, the voltage level at the output terminal Q of flip-flop 530 is equal to the voltage level at the setting terminal SET. When the switching circuit 520 outputs the clock signal clk, the voltage level at the output terminal Q of flip-flop 530 is equal to the voltage level at the input terminal D. At this time, the voltage level at the input terminal D is equal to the preset level VL.

[0076] Logic circuit 540 is coupled to the output Q of flip-flop 530 and receives a setting signal wken to generate a detection signal SD. When the flip-flop signal sig and the setting signal wken are enabled, logic circuit 540 enables the detection signal SD. When either the flip-flop signal sig or the setting signal wken is not enabled, logic circuit 540 does not enable the detection signal SD. In one possible embodiment, logic circuit 540 is an AND gate.

[0077] Since the SET terminal of trigger 530 receives the trigger signal sig, regardless of whether the external operating system (such as 120) is operating in a normal mode, a power-saving mode (sleep mode), or at the boundary between normal and power-saving modes, the wake-up circuit can immediately detect a wake-up event and determine whether to enable the wake-up signal WKUP based on the setting signals (such as wken, INTEN). In other embodiments, the interrupt signal INT is enabled later than the wake-up signal WKUP, thus ensuring that the operating system does not miss the interrupt signal INT.

[0078] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their relevant technical field, and not as idealized or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0079] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A wake-up circuit, characterized by, A wake-up signal and an interrupt signal are generated and include: a detection circuit, when a wake-up event occurs and a first set signal is enabled, enables a detection signal; a first logic circuit, when the detection signal and a low signal are enabled, enables the wake-up signal; a synchronization circuit, according to the detection signal, generates a synchronization signal, wherein an edge of the synchronization signal is aligned with an edge of an operation clock; a first flip-flop, when the synchronization signal is enabled, enables a first output signal; and a second logic circuit, when the first output signal and a second set signal are enabled, enables the interrupt signal.

2. The wake-up circuit of claim 1, wherein, The first logic circuit and the second logic circuit are AND gates.

3. The wake-up circuit of claim 1, wherein, When a clear signal is enabled, the detection circuit does not enable the detection signal, so that the first logic circuit does not enable the wake-up signal.

4. The wake-up circuit of claim 3, wherein, When the clear signal is enabled, the first flip-flop does not enable the first output signal, so that the second logic circuit does not enable the interrupt signal.

5. The wake-up circuit of claim 3, wherein, Further comprising: a third logic circuit for generating an input signal to the synchronization circuit, wherein when the wake-up event occurs or the detection signal is enabled, the third logic circuit enables the input signal, wherein the synchronization circuit processes the input signal to generate the synchronization signal.

6. The wake-up circuit of claim 5, wherein, The detection circuit includes: a second flip-flop having an input terminal, an output terminal and a clock terminal; a switch circuit receiving a clock signal, when the clear signal is enabled, outputs the clock signal to the clock terminal; a multiplexer coupled to the output terminal, when the clear signal is enabled, outputs a preset level to the input terminal, when the clear signal is not enabled, transmits the voltage of the output terminal to the input terminal; and a fourth logic circuit coupled to the output terminal and receiving the first set signal to generate the detection signal.

7. A processing circuit, characterized by, including: an operating system; and a wake-up circuit for providing a wake-up signal and an interrupt signal to the operating system, and including: a detection circuit, when a wake-up event occurs and a first set signal is enabled, enables a detection signal; a first logic circuit, when the detection signal and a low signal are enabled, enables the wake-up signal to wake up the operating system; a synchronization circuit, according to the detection signal, generates a synchronization signal, wherein an edge of the synchronization signal is aligned with an edge of an operation clock; a first flip-flop, when the synchronization signal is enabled, enables a first output signal; and a second logic circuit, when the first output signal and a second set signal are enabled, enables the interrupt signal. When a clear signal is enabled, the detection circuit does not enable the detection signal, so that the first logic circuit does not enable the wake-up signal.

8. The processing circuit of claim 7, wherein, Further comprising:

9. The processing circuit of claim 8, wherein, a third logic circuit for generating an input signal to the synchronization circuit, wherein when the wake-up event occurs or the detection signal is enabled, the third logic circuit enables the input signal, wherein the synchronization circuit processes the input signal to generate the synchronization signal. The detection circuit includes:

10. The processing circuit of claim 9, wherein, a second flip-flop having an input terminal, an output terminal and a clock terminal; a switch circuit receiving a clock signal, when the clear signal is enabled, outputs the clock signal to the clock terminal; a multiplexer coupled to the output terminal, when the clear signal is enabled, outputs a preset level to the input terminal, when the clear signal is not enabled, transmits the voltage of the output terminal to the input terminal; and a fourth logic circuit coupled to the output terminal and receiving the first set signal to generate the detection signal. a switch circuit receiving a clock signal and outputting the clock signal to the clock terminal when the clear signal is enabled; a multiplexer coupled to the output terminal and outputting a predetermined level to the input terminal when the clear signal is enabled and transmitting a voltage of the output terminal to the input terminal when the clear signal is not enabled; and a fourth logic circuit coupled to the output terminal and receiving the first set signal to generate the detection signal.

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