A SiC MOSFET device and its preparation method

Abstract

The present application discloses a SiC MOSFET device and a method for preparing the same. The SiC MOSFET device forms a plurality of inversion injection regions spaced apart in a drift region, so that any two adjacent inversion injection regions and the drift region between the two adjacent inversion injection regions constitute a JFET region. That is, the JFET region extends toward the substrate, thereby shifting the maximum electric field position away from the device surface and toward the interior of the drift region. This also separates the maximum electric field position from the channel region where the maximum current density is concentrated, and makes the current density distribution in the drift region more uniform. Therefore, after a short circuit, the hot spot of the device is no longer concentrated on the device surface near the channel, but is closer to the substrate and more evenly distributed in the drift region, thereby reducing the failure probability of the gate oxide layer and gate metal melting, delaying the occurrence of thermal runaway, reducing the hot spot temperature, improving the short-circuit withstand capability of the device, and increasing the short-circuit withstand time of the device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a SiC MOSFET device and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC) power devices belong to the third generation of semiconductor power devices. Compared with Si power devices, they have higher energy density and thermal conductivity. They are of great significance for promoting energy conservation and emission reduction and achieving carbon neutrality. The replacement of Si power devices with SiC power devices is the trend of the times.

[0003] Among SiC power devices, the SiC Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most widely used. However, the short-circuit withstand time of SiC MOSFETs is a serious problem in current applications. Short circuits are common in high-power applications such as motor drives. When a short circuit occurs, the power device is directly connected to an extremely high bus voltage. Typically, within a few microseconds, a large amount of heat is generated within the power device, leading to device failure. Due to the high energy involved in a short circuit, it can cause catastrophic damage to the power device and equipment, even causing serious damage to the equipment or fire. Short-circuit reliability is a measure of device reliability that measures the SiC MOSFET's ability to withstand high voltage and current simultaneously when the channel is open. To prevent serious damage caused by short circuits, equipment is often equipped with protection circuits to promptly shut down the SiC MOSFET to protect the load. However, before the protection circuit responds, the SiC MOSFET must have a certain short-circuit withstand time.

[0004] Due to the higher power density and denser cell arrangement of SiC MOSFET devices, the short-circuit withstand time of SiC MOSFET devices is significantly shorter than that of Si insulated gate bipolar transistor (IGBT) devices. Specifically, the short-circuit and resulting power loss of SiC MOSFET devices is typically in the range of 2-3μs, while the short-circuit withstand time of high-voltage Si IGBT devices is approximately 10μs. Therefore, how to improve the short-circuit withstand time of SiC MOSFET devices is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] To solve the above technical problems, the embodiments of the present application provide a SiC MOSFET device and a preparation method thereof, so as to improve the short-circuit withstand time of the SiC MOSFET device.

[0006] To achieve the above objectives, the present application provides the following technical solutions:

[0007] A SiC MOSFET device, comprising:

[0008] SiC substrate;

[0009] a first drift region located on one side of the SiC substrate, wherein both the SiC substrate and the first drift region are doped with a first type of doping;

[0010] Well regions are located on a side of the first drift region facing away from the SiC substrate and are spaced apart along a first direction, the well regions are doped with the second type, source regions are disposed within the well regions, the source regions are doped with the first type, and the first direction is parallel to the plane of the SiC substrate;

[0011] The first drift region includes a first region between two adjacent well regions and a second region located on a side of the first region and the well region close to the SiC substrate, wherein the second region is provided with a plurality of inversion injection regions spaced apart along the first direction, and the inversion injection regions are doped with the second type;

[0012] A gate oxide layer, a gate, an isolation dielectric layer and a source electrode are located on a side of the first drift region facing away from the SiC substrate, and a drain electrode is located on a side of the SiC substrate facing away from the first drift region.

[0013] Optionally, in the first direction, the distances between any two adjacent inversion injection regions are equal.

[0014] Optionally, a surface of the well region facing away from the SiC substrate is a channel region;

[0015] In the first direction, a distance between two adjacent inversion injection regions far away from the channel region is greater than a distance between two adjacent inversion injection regions close to the channel region.

[0016] Optionally, the doping concentration of the inversion injection region is greater than the doping concentration of the well region.

[0017] Optionally, the doping concentration of the inverted injection region is in the range of 1×10 17 cm -3 -1×10 22 cm -3 , including the endpoint values.

[0018] Optionally, also include:

[0019] A second drift region is located between the SiC substrate and the first drift region, the second drift region is doped with the first type of doping, and the doping concentration of the first drift region is greater than the doping concentration of the second drift region.

[0020] Optionally, the first drift region further includes a third region located between the inversion injection region and the second drift region.

[0021] Optionally, the well region, the source region, and the first drift region all extend along a second direction, and the second direction is parallel to a plane where the SiC substrate is located and perpendicular to the first direction;

[0022] The well region is also provided with a plurality of source contact regions spaced apart along the second direction, the source contact regions passing through the source region and the well region, the source contact regions being the second type doped, the doping concentration of the source contact regions being greater than the doping concentration of the well region, and the source contact regions forming an ohmic contact with the source electrode.

[0023] Optionally, the inversion implantation region extends along the second direction;

[0024] A common contact region is provided on at least one side of the first drift region along the second direction. The common contact region is doped with the second type and forms an ohmic contact with the source, so that each of the inversion injection regions is electrically connected to the source through the common contact region.

[0025] A method for preparing a SiC MOSFET device, comprising:

[0026] Providing a SiC substrate, forming an epitaxial layer on one side of the SiC substrate, wherein both the SiC substrate and the epitaxial layer are first-type doped;

[0027] Performing first-type ion implantation on the epitaxial layer to form a first drift region in at least a portion of the epitaxial layer;

[0028] Using a first preset mask, performing second-type ion implantation on the first drift region to form a plurality of inversion-type implantation regions spaced apart along a first direction in the first drift region, where the first direction is parallel to the plane of the SiC substrate;

[0029] Using a second preset mask, performing second-type ion implantation on a portion of the inversion implantation region in the first drift region on a side facing away from the SiC substrate to form well regions, wherein the well regions are arranged at intervals along the first direction, so that the first drift region includes a first region between two adjacent well regions and a second region located on a side of the first region and the well region close to the SiC substrate, wherein the inversion implantation region is provided in the second region;

[0030] Using a third preset mask, performing first-type ion implantation on the well region to form a source region in the well region;

[0031] forming a gate oxide layer and a gate in sequence on a side of the well region and the first region facing away from the SiC substrate;

[0032] forming an isolation dielectric layer, wherein the isolation dielectric layer has a through hole extending therethrough, and the through hole exposes the source region;

[0033] forming a source electrode, wherein the source electrode forms an ohmic contact with the source region through the through hole;

[0034] A drain is formed on a side of the SiC substrate away from the first drift region.

[0035] Compared with the existing SiC MOSFET device, only two adjacent well regions and the drift region between the two adjacent well regions constitute the JFET region, so that the maximum electric field position is concentrated at the corner of the well region and close to the channel region where the maximum current density is concentrated, resulting in the heat point of the device after a short circuit being concentrated on the device surface near the channel, and the short circuit withstand time is short. The SiC MOSFET device provided by the embodiment of the present application forms a plurality of spaced-apart inversion injection regions in the drift region close to the substrate side of the well region and the JFET region between the two adjacent well regions, and the doping types of the inversion injection region and the drift region are opposite, so that any two adjacent inversion injection regions and the drift region between the two adjacent inversion injection regions also constitute a JFET region, that is, the JFET region extends toward the substrate. At this time, on the one hand, the maximum electric field position will be located at the corner of the inversion injection region, that is, the maximum electric field position is away from the device surface and shifts toward the inside of the drift region. At the same time, the maximum electric field position is separated from the channel region where the maximum current density is concentrated. ; Secondly, after the carrier flow flows out of the channel, it will be dispersed by multiple inversion injection regions, flow through the JFET region between two adjacent inversion injection regions, and then expand to the drift region and flow out from the drain, that is, the current density distribution in the drift region is more uniform; since the heat generated in various places inside the device is proportional to the current density and electric field strength at that place, the hot spot of the device after a short circuit is no longer concentrated on the device surface near the channel, but is closer to the substrate and more evenly distributed in the drift region, thereby reducing the failure probability of gate oxide melting and gate metal melting, delaying the time for thermal runaway to occur, and reducing the temperature at the hot spot, thereby improving the short circuit tolerance capability of the SiC MOSFET device and increasing the short circuit tolerance time of the SiC MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 Schematic diagram of the cross-sectional structure of an existing SiC MOSFET device;

[0038] Figure 2 A schematic cross-sectional structure diagram of a SiC MOSFET device provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of the three-dimensional structure of a SiC MOSFET device provided in an embodiment of the present application;

[0040] Figure 4 Schematic diagram of current density distribution of a half-cell structure of an existing SiC MOSFET device at short-circuit time t = 1 μs;

[0041] Figure 5 Schematic diagram of current density distribution of a half-cell structure of a SiC MOSFET device provided in an embodiment of the present application at a short-circuit time of t=1 μs;

[0042] Figure 6 Schematic diagram of temperature distribution of a half-cell structure of an existing SiC MOSFET device at short-circuit time t = 1 μs;

[0043] Figure 7 Schematic diagram of temperature distribution of a half-cell structure of a SiC MOSFET device provided in an embodiment of the present application at a short-circuit time of t=1 μs;

[0044] Figure 8 The gate voltage V of the existing SiC MOSFET device and the SiC MOSFET device provided in the embodiment of the present application is gate , drain current I drain and the maximum temperature inside the device, T max Schematic diagram of the comparison of the relationship with short-circuit time t;

[0045] Figure 9 for Figure 3 Schematic cross-sectional view of the SiC MOSFET device along AA';

[0046] Figure 10(a)-Figure 10(i) Schematic diagram of the device structure corresponding to each process step in the method for preparing a SiC MOSFET device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0048] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0049] Secondly, this application is described in detail with reference to schematic diagrams. When describing the embodiments of this application, for ease of explanation, cross-sectional views of device structures may be partially enlarged and not to scale. Furthermore, these schematic diagrams are merely illustrative and should not limit the scope of protection of this application. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0050] It should be noted that the terms "first", "second" and "third" in the description and claims of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0051] Figure 1 A schematic diagram of a cross-sectional structure of an existing SiC MOSFET device is shown in FIG. Figure 1 As shown, existing SiCMOSFET devices include N + Substrate 01 and located in N + N arranged in sequence on one side of substrate 01 - Drift region 02, N drift region 03, P well region 04, P ++ Source contact area 05 and N + Source region 06, gate 07 and source 08 are located in N drift region 03 away from N + On one side of the substrate 01, there is a gate oxide layer 09 between the gate 07 and the P well region 04 and the N drift region 03, and an isolation dielectric layer 010 is provided between the gate 07 and the source 08. Both the gate oxide layer 09 and the isolation dielectric layer 010 can be SiO2 insulating layers. The drain 011 is located at the N + Substrate 01 faces away from N -One side of the drift region 02. Among them, two adjacent P-well regions 04 and the N-drift region 03 between the two adjacent P-well regions 04 form two back-to-back PN junctions, namely, junction field-effect transistor (JFET) regions, generating a JFET effect.

[0052] During the operation of the SiC MOSFET device, when the gate 07 is not forward biased and the drain 011 is forward biased, the SiC MOSFET is in the reverse off state. At this time, the two PN junctions in the JFET region are reverse biased, and the voltage applied between the drain 011 and the source 08 is N - Drift region 02 and N drift region 03 (mainly composed of N - Drift region 02) bears; when the gate 07 is applied with a forward bias and the drain 011 is also applied with a forward bias, the SiC MOSFET is in the forward conduction state. At this time, the two PN junctions in the JFET region are still in reverse bias, and the P well region 04 is away from the N + An inversion channel region is formed on the surface of the substrate 01. The electron flow flows from the source 08 through the channel region into the JFET region, and then extends downward through the JFET region to the N drift region 03 and N - Drift region 02 flows out from drain 011.

[0053] As mentioned in the background section, the short-circuit withstand time of SiC MOSFETs is a serious problem in current applications. The inventors have discovered that this is because, when a short circuit occurs, the primary heat generation point in existing SiC MOSFET devices is concentrated on the device surface near the channel, which can easily lead to gate oxide melting failure, source metal fracture and melting failure, and thermal runaway failure, resulting in a short short-circuit withstand time. Currently, short-circuit failures in SiC MOSFET devices primarily manifest as the following three types:

[0054] The first is gate oxide melting failure, which is prone to occur during the turn-off period of the SiC MOSFET device after a short circuit. At this time, the device loses control of the channel region, the current suddenly increases, and a large amount of heat is generated, causing the junction temperature to rise. The concentrated heat in the channel causes the gate oxide layer to melt and fail.

[0055] The second type is source metal melting failure. Since the source metal is usually aluminum, a short circuit can easily cause the device temperature to rise to the melting point of aluminum (about 660°C), causing the aluminum electrode to melt and break, resulting in failure.

[0056] The third type is thermal runaway failure. The heat released by the MOSFET channel region will increase the temperature, thereby increasing the temperature of the depletion region between the P-well region 04 and the N-drift region 03, and then sharply increasing the intrinsic carrier concentration. After the carrier drifts, a larger drain current is formed. The increased drain current generates more heat. If the heat generated per unit time is greater than the heat dissipation power of the device, then the device temperature will continue to rise. The higher temperature will cause the drain current to increase further, thus forming a positive temperature feedback effect between temperature and drain current. Due to the characteristics of SiC material, SiC power devices are much thinner and narrower than Si power devices, making SiC power devices have higher power density. The junction temperature during short circuit can even exceed 1000K. When the heat dissipation rate is slower than the heat increase rate brought by the drain current, thermal runaway failure is prone to occur. Local defects in the device or slight process differences can lead to uneven current density and temperature, thereby forming local hot spots that cause the structure to melt and lead to device failure.

[0057] The inventors further discovered that since the JFET effect of the existing SiC MOSFET device is generated between the P-well region 04 and the N-drift region 03, the maximum electric field is concentrated at the corner of the P-well region 04, and the maximum current density is concentrated in the channel region. Figure 1 It can be seen that the corner of the P-well region 04 where the maximum electric field is located is relatively close to the channel region where the maximum current density is concentrated. Since the heat generated at various locations within the device is proportional to the power at that location, the greater the power, the more heat generated and the higher the temperature. The power at that location is in turn proportional to the current density and electric field strength at that location. Therefore, the main heating points of existing SiC MOSFET devices are concentrated on the device surface near the channel, which can easily lead to gate oxide melting failure, source metal melting failure, and thermal runaway failure, thereby shortening the short-circuit withstand time of the device.

[0058] Based on the above research, an embodiment of the present application provides a SiC MOSFET device and a preparation method thereof, by forming a plurality of spaced-apart inversion injection regions in a well region and a drift region of a JFET region between two adjacent well regions close to the substrate side, and the doping types of the inversion injection region and the drift region are opposite, so that any two adjacent inversion injection regions and the drift region between the two adjacent inversion injection regions also constitute a JFET region, that is, the JFET region extends toward the substrate. At this time, on the first aspect, the maximum electric field position will be located at the corner of the inversion injection region, that is, the maximum electric field position is away from the device surface and shifted toward the inside of the drift region. At the same time, the channel region where the maximum electric field position and the maximum current density are concentrated is also made. Phase separation; secondly, after the carriers flow out of the channel, they will be dispersed by multiple inversion injection regions, flow through the JFET region between two adjacent inversion injection regions, and then expand to the drift region and flow out from the drain, that is, the current density distribution in the drift region is more uniform; since the heat generated in various places inside the device is proportional to the current density and electric field strength at that place, the hot spot of the device after a short circuit is no longer concentrated on the device surface near the channel, but is closer to the substrate and more evenly distributed in the drift region, thereby reducing the failure probability of gate oxide melting and gate metal melting, delaying the time for thermal runaway to occur, and reducing the temperature at the hot spot, thereby improving the short-circuit tolerance of the SiC MOSFET device and increasing the short-circuit tolerance time of the SiC MOSFET device.

[0059] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0060] Figure 2 FIG2 shows a schematic cross-sectional structure diagram of a SiC MOSFET device provided in an embodiment of the present application. Figure 3 A schematic diagram of the three-dimensional structure of a SiC MOSFET device provided in an embodiment of the present application is shown. Figure 2 and Figure 3 As shown, the SiC MOSFET device includes:

[0061] SiC substrate 1;

[0062] A first drift region 2 located on one side of the SiC substrate 1, wherein both the SiC substrate 1 and the first drift region 2 are doped with the first type;

[0063] Well regions 3 are located on the side of the first drift region 2 facing away from the SiC substrate 1 and are arranged at intervals along the first direction X. The well regions 3 are doped with the second type. Source regions 4 are disposed in the well regions 3 and are doped with the first type. The first direction X is parallel to the plane of the SiC substrate 1.

[0064] The first drift region 2 includes a first region 2a between two adjacent well regions 3 and a second region 2b located on the side of the first region 2a and the well region 3 close to the SiC substrate 1. The second region 2b is provided with a plurality of inversion injection regions 5 arranged at intervals along the first direction X. The inversion injection regions 5 are doped with the second type.

[0065] The gate oxide layer 6 , the gate electrode 7 , the isolation dielectric layer 8 and the source electrode 9 are located on the side of the first drift region 2 facing away from the SiC substrate 1 , and the drain electrode 10 is located on the side of the SiC substrate 1 facing away from the first drift region 2 .

[0066] In an embodiment of the present application, the first-type doping and the second-type doping are of different types. Optionally, if the first-type doping is N-type doping, the second-type doping is P-type doping. Conversely, if the first-type doping is P-type doping, the first-type doping is N-type doping.

[0067] In the embodiment of the present application, on the side of the first drift region 2 facing away from the SiC substrate 1, the gate oxide layer 6 and the gate 7 are arranged in a direction away from the SiC substrate 1 ( Figure 2 The gate oxide layer 6 and the gate electrode 7 cover the first region 2a of the first drift region 2 and at least a portion of the well region 3 facing away from the surface of the SiC substrate 1.

[0068] On the side of the first drift region 2 facing away from the SiC substrate 1, an isolation dielectric layer 8 covers the gate to isolate the gate 7 from the source 9. The isolation dielectric layer 8 has a through-hole extending therethrough, allowing the source 9 to form an ohmic contact with the source region 4 through the through-hole extending through the isolation dielectric layer 8. Furthermore, the source 9 is electrically connected to the well region 3 to transmit the potential of the source 9 to the surface of the well region 3 facing away from the SiC substrate 1 and covered by the gate 7 and gate oxide layer 6. When a corresponding bias is applied to the gate 7, an inversion channel region is formed on the surface of the well region 3 facing away from the SiC substrate 1, covered by the gate oxide layer 6 and the gate 7.

[0069] In the embodiment of the present application, the first drift region 2 is doped with the first type, and the well region 3 and the inversion injection region 5 are both doped with the second type. Therefore, not only do two adjacent well regions 3 and the drift region (first region 2a) between the two adjacent well regions 3 constitute a JFET region, as in the existing SiC MOSFET device, but also, unlike the existing SiC MOSFET device, any two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions also constitute a JFET region.

[0070] Then, compared with the existing SiC MOSFET device, only two adjacent well regions and the drift region between the two adjacent well regions constitute the JFET region, so that the maximum electric field position is concentrated at the corner of the well region and is close to the channel region where the maximum current density is concentrated, resulting in the heat point of the device after a short circuit being concentrated on the device surface near the channel, which easily causes the gate oxide layer and the source metal to melt, resulting in local failure of the device and a short short-circuit withstand time. In the SiCMOSFET device provided in the embodiment of the present application, the JFET region extends toward the substrate. At this time, the maximum electric field position will be located at the corner of the inversion injection region 5, that is, the maximum electric field position is away from the device surface and shifts toward the inside of the first drift region 2. At the same time, the maximum electric field position is separated from the channel region where the maximum current density is concentrated. Since the heat generated at various locations inside the device is proportional to the current density and electric field strength at that location, the hot spots of the device after a short circuit are no longer concentrated on the device surface near the channel, but are generated inside the drift region far away from the device surface, thereby reducing the failure probability of gate oxide melting and gate metal melting, improving the short-circuit tolerance of the SiC MOSFET device, and increasing the short-circuit withstand time of the SiC MOSFET device.

[0071] The following briefly describes the working process of the SiC MOSFET device provided in the embodiment of the present application, taking the case where the first type doping is N-type doping and the second type doping is P-type doping as an example.

[0072] During specific operation, when a forward bias is applied to the gate 7 and a forward bias is also applied to the drain 10, the SiC MOSFET is in a forward conduction state. At this time, the surface of the well region 3 facing away from the SiC substrate 1 and covered by the gate 7 and the gate oxide layer 6 forms an inversion channel region, and the JFET region composed of two adjacent well regions 3 and the drift region (first region 2a) between the two adjacent well regions 3, and the JFET region composed of two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 are all in reverse bias. The electron flow flows from the source 9 through the channel region into the JFET region between the two adjacent well regions 3, and is then dispersed by multiple inversion injection regions 5, flows through the JFET region between the two adjacent inversion injection regions 5, and then flows out from the drain.

[0073] When no forward bias is applied to the gate 7 and a forward bias is applied to the drain 10, the SiC MOSFET is in a reverse off state. At this time, the JFET region composed of two adjacent well regions 3 and the drift region (first region 2a) between the two adjacent well regions 3, and the JFET region composed of two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 are also in reverse bias. The voltage applied between the drain 10 and the source 9 is borne by the first drift region 2.

[0074] Among them, when the SiC MOSFET device is in the forward conduction state, in order to allow the electron current to flow through the JFET region, the two reverse-biased PN junctions in the JFET region need not be pinched off. When the SiC MOSFET device is in the reverse off state, in order to reduce the drain current and increase the reverse breakdown voltage of the device, it is hoped that the two reverse-biased PN junctions in the JFET region will be pinched off. Therefore, when the SiC MOSFET device is in the forward conduction state, the forward bias voltage applied to the drain 10 is small, and when it is in the reverse off state, the forward bias voltage applied to the drain 10 is large.

[0075] Thus, compared to the existing SiC MOSFET device, in which the carrier flow (such as electron flow) flows out of the channel, then expands to the drift region through the JFET region between the two adjacent well regions, and then flows out from the drain, in the SiCMOSFET device provided by the embodiment of the present application, the carrier flow (such as electron flow) flows out of the channel through the JFET region between the two adjacent well regions 3, and then is dispersed by multiple inversion injection regions 5, flows through the JFET region between the two adjacent inversion injection regions 5, and then flows out from the drain, that is, the current density distribution in the first drift region 2 is more uniform. Since the heat generated at various locations inside the device is proportional to the current density and electric field strength at that location, the current density and heat generated by the device after a short circuit are more evenly distributed in the first drift region 2, which can reduce the temperature at the hot spot.

[0076] It is understandable that after a short circuit occurs, the heat accumulated in the device reaches the short circuit critical energy E c After that, the device will fail locally. Specifically, the short-circuit critical energy E c It can be expressed as:

[0077]

[0078] Among them, t sc is the short-circuit withstand time, V ds is the drain voltage, I d is the drain current.

[0079] When the temperature at the hot spot drops, the device can reach the short-circuit critical energy E c The time is extended to improve the short-circuit withstand time of SiC MOSFET devices.

[0080] Moreover, as is known from the foregoing, when the device temperature rises to a certain level (for SiC MOSFET devices, up to 1000K), the intrinsic carrier concentration will increase exponentially with the temperature, causing the drain current to increase rapidly. The increased drain current will generate more heat. If the heat generated per unit time is greater than the heat dissipation power of the device, then the device temperature will continue to rise, and higher temperatures will cause the drain current to increase further, thereby forming a positive temperature feedback effect of temperature and drain current, and ultimately causing the device to thermally run away and fail. In the SiC MOSFET device provided in the embodiment of the present application, the hot spot of the device after short circuit is transferred to the inside of the first drift region 2 away from the surface of the device, and the current density and heat generated by the device after short circuit are more evenly distributed in the first drift region 2, which can also reduce the temperature rise rate of the device after short circuit, and overall reduce the maximum temperature and maximum current density of the device, thereby delaying the time when thermal runaway occurs, thereby increasing the short circuit withstand time of the SiC MOSFET device.

[0081] It is worth noting that the SiC MOSFET devices provided in the embodiments of the present application improve their short-circuit resistance and increase their short-circuit withstand time while, through optimized structure and doping design, not affecting other electrical properties of the device, such as the forward on-resistance and reverse breakdown voltage. This is described in detail below.

[0082] In the embodiment of the present application, since a plurality of spaced-apart inversion injection regions 5 are formed in the second region 2b of the first drift region 2, any two adjacent inversion injection regions 5 and the drift region between them also constitute a JFET region, thereby increasing the forward on-resistance of the device. Optionally, the doping concentration of the first drift region 2 can be increased to reduce the forward on-resistance of the device. However, it is understood that this results in a greater drain current when the drain is reverse biased, thereby reducing the reverse breakdown voltage of the device.

[0083] Alternatively, the spacing between two adjacent inversion injection regions 5 can be increased so that the carrier flow (such as electron flow) can flow more smoothly through the drift region between the two adjacent inversion injection regions 5, that is, the resistance of the JFET region formed by the two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 is reduced, thereby reducing the forward conduction resistance of the device. However, this will also cause the drain current to be larger when the drain is reverse biased, thereby causing a decrease in the reverse breakdown voltage of the device.

[0084] Therefore, by optimizing the doping concentration of the first drift region 2 and the spacing between two adjacent inversion injection regions 5 in the SiC MOSFET device, other electrical properties of the device (such as forward on-resistance and reverse breakdown voltage) can be made to meet the requirements. That is, while improving the short-circuit resistance of the device and increasing the short-circuit withstand time of the device, other electrical properties of the device will not be affected.

[0085] It should be noted that if Figure 2 and Figure 3 As shown, along the direction perpendicular to the plane of the SiC substrate 1 (Z direction), the drain 10, the SiC substrate 1, the first drift region 2, the well region 3, the source region 4, the gate oxide layer 6, the gate 7, the isolation dielectric layer 8 and the source 9 are arranged in sequence to form a cell structure. Figure 2 As shown in the solid box in Figure 2 The dotted box in the middle shows a half-cell structure. The present application does not limit the number of cell structures included in the SiC MOSFET device, which depends on the specific situation.

[0086] It should also be noted that the present application does not limit the number of inversion injection regions 5 provided in the second region 2b of the first drift region 2. It is understood that, along the first direction X, the greater the number of inversion injection regions 5 provided in the second region 2b of the first drift region 2, the more uniformly the carrier flow out of the channel is dispersed, the stronger the short-circuit resistance of the device is, and the longer the short-circuit withstand time of the device is. However, at the same time, the forward on-resistance of the device is relatively large.

[0087] The present application does not limit the doping concentration of the inversion injection region 5 provided in the second region 2b of the first drift region 2. It is understood that, the greater the doping concentration of the inversion injection region 5, the smaller the volume of the inversion injection region 5 required to achieve the same effect. Consequently, carriers can flow more smoothly through the drift region between two adjacent inversion injection regions 5, and the impact on the forward on-resistance of the device is reduced.

[0088] This application does not impose any restrictions on the depth of the inversion injection region 5 provided in the second region 2b of the first drift region 2. It should be understood that the injection depth of the inversion injection region 5 refers to the distance between the surface of the inversion injection region 5 on the side closest to the SiC substrate 1 and the surface of the first region 2a of the first drift region 2 facing away from the SiC substrate 1. Therefore, the deeper the injection depth of the inversion injection region 5, the further away the location of the maximum electric field is from the device surface, causing the hot spot of the device after a short circuit to be further away from the device surface.

[0089] In addition, the present application does not limit the doping concentration distribution of the first drift region 2 , which may be a uniform distribution or a non-uniform distribution, such as a superposition of multiple Gaussian distributions, etc., depending on the specific situation.

[0090] Furthermore, the inventors conducted TCAD simulation verification on the half-cell structure of the existing SiC MOSFET device and the half-cell structure of the SiC MOSFET device provided in the embodiment of the present application, wherein the half-cell structure of the existing SiC MOSFET device is as follows: Figure 1 As shown in the dotted box, the half-cell structure of the SiC MOSFET device provided in the embodiment of the present application is as follows Figure 2 As shown in the dotted box, it includes a drain, a SiC substrate, a drift region, a well region, a source region, a gate oxide layer, a gate, an isolation dielectric layer and a source electrode arranged in sequence.

[0091] Figure 4 and Figure 5 Schematic diagrams of current density distribution of the half-cell structure of the existing SiC MOSFET device and the half-cell structure of the SiC MOSFET device provided by the embodiment of the present application at the short-circuit time t = 1 μs are given respectively for comparison. Figure 4 and Figure 5 It can be seen that in the half-cell structure of the existing SiC MOSFET device, the maximum current density is concentrated near the channel and only slightly expands in the drift region; while in the half-cell structure of the SiC MOSFET device provided in the embodiment of the present application, although the maximum current density is still concentrated near the channel, the current density distribution in the first drift region 2 is more uniform due to the shunting effect of the multiple inversion injection regions 5.

[0092] Figure 6 and Figure 7 Schematic diagrams of the temperature distribution of the half-cell structure of the existing SiC MOSFET device and the half-cell structure of the SiC MOSFET device provided by the embodiment of the present application at the short-circuit time t = 1 μs are given respectively. Figure 6 and Figure 7 It can be seen that in the half-cell structure of the existing SiC MOSFET device, the hot spots are mainly concentrated on the device surface near the channel, which can easily cause gate oxide melting failure, source metal fracture and melting failure, and thermal runaway failure. However, in the half-cell structure of the SiC MOSFET device provided by the embodiment of the present application, the hot spots are no longer concentrated on the device surface near the channel, but are generated inside the drift region away from the device surface and are relatively evenly distributed inside the drift region. Therefore, the heat dissipation capacity of the entire device can be utilized, the failure probability of gate oxide melting and source metal melting is reduced, the time of thermal runaway occurrence is delayed, and the short-circuit tolerance capability of the device is improved, and the short-circuit tolerance time is increased.

[0093] Figure 8 The gate voltage V of the existing SiC MOSFET device and the SiC MOSFET device provided by the embodiment of the present application are given. gate , drain current Idrain and the maximum temperature inside the device, T max Schematic diagram comparing the relationship between the change with the short-circuit time t. At this time, the existing SiC MOSFET device and the SiC MOSFET device provided in the embodiment of the present application are both N-channel MOSFET devices. At time t=0, the device has been short-circuited, and the drain-source voltage V ds =800V, the gate starts to add positive voltage, when t=20ns, the gate voltage V gate =20V. Figure 8 It can be seen that the short-circuit time for thermal runaway of the existing SiC MOSFET device is about 1.7 μs after the short circuit is opened, while the short-circuit withstand time of the SiC MOSFET device provided in the embodiment of the present application is increased to 4.2 μs, which is about 2.5 times longer than the short-circuit withstand time of the existing SiC MOSFET device.

[0094] Regarding the spacing between two adjacent inversion injection regions 5, optionally, in one embodiment of the present application, as Figure 2 and Figure 3 As shown, the spacing between any two adjacent inversion implantation regions 5 in the first direction X can be equal. In an actual process, after forming the first-type doped first drift region 2 on one side of the first-type doped SiC substrate 1, a plurality of inversion implantation regions 5 spaced apart along the first direction X are formed in the first drift region 2 by an ion implantation process. In this embodiment, the spacing between any two adjacent inversion implantation regions 5 in the first direction X is equal.

[0095] Optionally, in another embodiment of the present application, considering that the surface of the well region 3 facing away from the SiC substrate 1 can be covered by the gate oxide layer 3 and the gate 7 to form a channel region, and the channel region is the region where the maximum current density is concentrated, in order to make the carrier flow expand as much as possible along the first direction X after flowing out of the channel region, so that the current density distribution of the first drift region 2 is more uniform, therefore, in this embodiment, the spacing between two adjacent inversion injection regions 5 away from the channel region can be set in the first direction X to be greater than the spacing between two adjacent inversion injection regions 5 close to the channel region.

[0096] It can be understood that when the carrier flow flows in the drift region between two adjacent inversion injection regions 5, since the two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 constitute a JFET region, that is, the two adjacent inversion injection regions 5 form a PN junction with the drift region between the two adjacent inversion injection regions 5, the carrier flow actually flows in the undepleted drift region between the depletion regions of the back-to-back PN junctions. Then, the smaller the spacing between the two adjacent inversion injection regions 5, the narrower the drift region between the two adjacent inversion injection regions 5 available for carrier flow, and the greater the resistance formed by the JFET region between the two adjacent inversion injection regions. Conversely, the larger the spacing between the two adjacent inversion injection regions 5, the wider the drift region between the two adjacent inversion injection regions 5 available for carrier flow, and the smaller the resistance formed by the JFET region between the two adjacent inversion injection regions 5.

[0097] In this embodiment, the spacing between two adjacent inversion injection regions 5 away from the channel region is set to be greater than the spacing between two adjacent inversion injection regions 5 close to the channel region. Since the carrier flow always tends to flow to a place with smaller resistance, after the carrier flow flows out of the channel region, it is more inclined to flow through the drift region between the two adjacent inversion injection regions 5 away from the channel region. After the carrier flow flows out of the channel region, it expands as much as possible along the first direction X, so that the current density distribution in the first drift region 2 is more uniform.

[0098] Regarding the doping concentration of the inversion injection region 5 , optionally, in one embodiment of the present application, the doping concentration of the inversion injection region 5 is greater than the doping concentration of the well region 3 .

[0099] Since the doping concentration of the inversion injection region 5 is greater, the volume of the inversion injection region 5 required to form a depletion region of the same width in the drift region between two adjacent inversion injection regions 5 will be smaller, thereby making the volume of all inversion injection regions 5 set in the second region 2b of the first drift region 2 smaller, and thus making the space of the drift region for carrier flow in the second region 2b of the first drift region 2 larger, and having less impact on the forward on-resistance of the device; and since the drift region between two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 and the drift region between two adjacent well regions 3 will all constitute a JFET region, and in the first direction X, the width of the drift region between two adjacent inversion injection regions 5 is smaller than the width of the drift region between two adjacent well regions 3, therefore, in this embodiment, the doping concentration of the inversion injection region 5 is set to be greater than the doping concentration of the well region 3, so that the space of the drift region for carrier flow in the second region 2b of the first drift region 2 is sufficiently large, and has less impact on the forward on-resistance of the device.

[0100] Since the doping concentration of the well region 3 is usually 1×1015 cm -3 -1×10 20 cm -3 Therefore, further optionally, in one embodiment of the present application, the doping concentration of the inversion injection region 5 is in the range of 1×10 17 cm -3 -1×10 22 cm -3 , including the endpoint values. In this case, the inversion injection region 5 provided in the second region 2b of the first drift region 2 not only effectively improves the short-circuit withstand capability of the device, but also ensures that the drift region space for carrier flow in the second region 2b of the first drift region 2 is sufficiently large, thereby having little effect on the forward on-resistance of the device.

[0101] Regarding the injection depth of the inversion injection region 5, optionally, in one embodiment of the present application, the injection depth of the well region 3 can be 0.1 μm-1 μm, including the endpoint values. Since the inversion injection region 5 is located on the side of the well region 3 close to the SiC substrate, the injection depth of the inversion injection region 5 can be 0.5 μm-1.5 μm, including the endpoint values.

[0102] In this embodiment, similar to the injection depth of the inversion injection region 5, the injection depth of the well region 3 refers to the distance between the surface of the well region close to the SiC substrate 1 and the surface of the first region 2a of the first drift region 2 facing away from the SiC substrate 1 (that is, the surface of the well region 3 facing away from the SiC substrate 1).

[0103] Based on any of the above embodiments, optionally, in one embodiment of the present application, Figure 2 and Figure 3 As shown, the SiC MOSFET device may further include: a second drift region 11 located between the SiC substrate 1 and the first drift region 2 , the second drift region 11 being first-type doped, and the doping concentration of the first drift region 2 is greater than the doping concentration of the second drift region 11 .

[0104] As is known from the foregoing, when the SiC MOSFET is in the reverse off state, the voltage applied between the drain 10 and the source 9 is borne by the first drift region 2. However, in reality, the reverse breakdown voltage that the first drift region 2 can withstand is still relatively small. Therefore, in this embodiment, a second drift region 11 is provided between the SiC substrate 1 and the first drift region 2. The second drift region 11 and the first drift region 2 have the same doping type, both being first-type doping, and the doping concentration of the first drift region 2 is greater than the doping concentration of the second drift region 11. Thus, the second drift region 11 with a lower doping concentration and the inversion injection region 5 are utilized to form a depletion region (mainly in the second drift region) to withstand a larger reverse voltage between the drain 10 and the source 9.

[0105] It should be noted that the second drift region 11 should be of sufficient thickness so that the depletion region formed by the multiple inversion injection regions 5 and the second drift region 11 (mainly in the second drift region 11) can withstand the reverse voltage between the drain 10 and the source 9 to prevent the device from being broken down.

[0106] As is known from the foregoing, after the carrier flow flows out of the channel, it flows through the drift region between the two adjacent inversion injection regions 5. In order to further expand the carrier flow flowing through the drift region between the two adjacent inversion injection regions 5 along the first direction X, optionally, in one embodiment of the present application, as Figure 2 As shown, the first drift region 2 further includes a third region 2c located between the inversion injection region 5 and the second drift region 11. In the embodiment of the present application, the third region 2c can serve as a current expansion region, so that the carrier flow flowing from the drift region between two adjacent inversion injection regions 5 expands along the first direction X and then flows out from the drain 10.

[0107] Based on any of the above embodiments, optionally, in one embodiment of the present application, Figure 2 and Figure 3 As shown, the well region 3, the source region 4 and the first drift region 2 all extend along the second direction Y, and the second direction Y is parallel to the plane where the SiC substrate 1 is located and perpendicular to the first direction X;

[0108] like Figure 3 As shown, the well region 3 is also provided with a plurality of source contact regions 12 arranged at intervals along the second direction Y. The source contact region 12 runs through the source region 4 and the well region 3. The source contact region 12 is second-type doped. The doping concentration of the source contact region 12 is greater than the doping concentration of the well region 3, and the source contact region 12 forms an ohmic contact with the source electrode 9.

[0109] As is known from the foregoing, the source electrode 9 and the well region 3 are electrically connected to transmit the potential of the source electrode 9 to the surface of the well region 3 facing away from the SiC substrate 1 and covered by the gate oxide layer 6 and the gate 7, so that when the gate 7 applies a corresponding bias, the well region 3 covered by the gate oxide layer 6 and the gate 7 facing away from the surface of the SiC substrate 1 forms an inversion channel region. In this embodiment, the well region 3, the source region 4 and the first drift region 2 all extend along the second direction Y, so that a plurality of source contact regions 12 arranged at intervals along the second direction Y are provided in the well region 3. Since the source contact regions 12 runs through the source region 4 and the well region 3, and the source contact region 12 and the well region 3 are both second-type doped. The doping concentration of the source contact region 12 is greater than the doping concentration of the well region 3, so that the source contact region 12 forms an ohmic contact with the source electrode 9. Therefore, the potential of the source electrode 9 can be transmitted through the highly doped source contact region 12 to the surface of the well region 3 away from the SiC substrate 1 and covered by the gate oxide layer 6 and the gate 7, thereby reducing the resistance of the source potential transmitted to the surface of the well region 3 away from the SiC substrate 1 and covered by the gate oxide layer 6 and the gate 7, thereby improving device performance.

[0110] Based on the above embodiment, optionally, in one embodiment of the present application, as Figure 3 As shown, the inversion injection region 5 extends along the second direction Y;

[0111] A common contact region 13 is provided on at least one side of the first drift region 2 along the second direction. The common contact region 13 is second-type doped and forms an ohmic contact with the source 9 , so that each inversion injection region 5 is electrically connected to the source 9 through the common contact region 13 .

[0112] As is known from the foregoing, two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 constitute a JFET region, that is, a back-to-back reverse-biased PN junction, and the drift region between the two adjacent inversion injection regions 5 is electrically connected to the drain 10. Therefore, in order to provide a potential to each inversion injection region 5, in this embodiment, a common contact region 13 is provided on at least one side of the first drift region 2 along the second direction Y. The common contact region 13 and the inversion injection region 5 are both second-type doped, and the common contact region 13 forms an ohmic contact with the source 9. Specifically, Figure 9 Shown Figure 3 AA' cross-sectional view, from Figure 9 As can be seen from the figure, at this time, each inversion injection region 5 is electrically connected to the source 9 through the common contact region 13, so that the potential of the source 9 is provided to each inversion injection region 5, so that two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 constitute a JFET region. At this time, the SiC MOSFET device structure is compact.

[0113] Of course, optionally, in other embodiments of the present application, a potential may be provided to each inversion injection region 5 by providing additional electrodes, etc., depending on the specific circumstances.

[0114] The present invention also provides a method for preparing a SiC MOSFET device, the method comprising:

[0115] S10: As shown in FIG10( a ), a SiC substrate 1 is provided, and an epitaxial layer is formed on one side of the SiC substrate 1 . Both the SiC substrate 1 and the epitaxial layer are first-type doped. The epitaxial layer is a SiC epitaxial layer.

[0116] S20: As shown in FIG10( a ), first-type ion implantation is performed on the epitaxial layer to form a first drift region 2 in at least a portion of the epitaxial layer. At this time, the first drift region 2 is also first-type doped, and the doping concentration of the first drift region 2 is greater than the doping concentration of the original epitaxial layer.

[0117] Optionally, in step S20 , after the first type ion implantation is performed on the epitaxial layer, a second drift region 11 is retained between the first drift region 2 and the SiC substrate 1 , and the doping concentration of the second drift region 11 is the same as that of the original epitaxial layer.

[0118] Specifically, taking an N-channel MOSFET device as an example, the first type doping is N-type doping, the first type ion implantation is N-type ion implantation, and the SiC substrate 1 is N + doping, the second drift region 11 is N - Doping: the first drift region 2 is N-doped.

[0119] S30: As shown in FIG10( b ), the first drift region 2 is implanted with second-type ions using the first preset mask 14 , thereby forming a plurality of inversion implantation regions 5 spaced apart along a first direction X in the first drift region 2 , where the first direction X is parallel to the plane of the SiC substrate 1 .

[0120] In step S30, the first preset mask 14 can be used to block the areas of the first drift region 2 that do not need to be ion implanted, so as to perform second-type ion implantation on the areas of the first drift region 2 that need to be ion implanted, thereby forming a plurality of inversion implantation regions 5 arranged at intervals along the first direction X in the first drift region 2.

[0121] Specifically, taking an N-channel MOSFET device as an example, since the first drift region 2 is N-doped, the second type ion implantation is P-type ion implantation, that is, the inversion implantation region 5 is P-doped.

[0122] S40: As shown in FIG10( c ), using a second preset mask 15 , second type ion implantation is performed on a portion of the inversion implantation region 5 in the first drift region 2 on a side facing away from the SiC substrate 1 to form a well region 3 , and the well regions 3 are arranged at intervals along the first direction X, so that the first drift region 2 includes a first region 2 a between two adjacent well regions 3 and a second region 2 b located on a side of the first region 2 a and the well region 3 close to the SiC substrate 1 , and the second region 2 b is provided with an inversion implantation region 5 .

[0123] In step S40 , the second preset mask plate 15 may be used to shield the area of ​​the first drift region 2 where ion implantation is not required, and the second type ion implantation is performed in the area of ​​the first drift region 2 where the well region 3 is required to be formed, so as to form the well regions 3 spaced apart along the first direction X.

[0124] Specifically, taking an N-channel MOSFET device as an example, since the first drift region 2 is N-doped, P-type ion implantation is performed on a portion of the inversion implantation region 5 in the first drift region 2 away from the SiC substrate 1 to form a P-doped well region 3.

[0125] Optionally, in the previous step S30 , the injection depth of the inversion injection region 5 may be controlled so that the first drift region 2 may further include a third region 2 c located between the inversion injection region 5 and the second drift region 11 to serve as a current spreading layer.

[0126] S50 : As shown in FIG. 10( d ), the first type ion implantation is performed on the well region 3 using the third preset mask 16 to form a source region 4 in the well region 3 .

[0127] In step S50 , the third preset mask 16 can be used to block areas of the well region 3 and the first drift region 2 where ion implantation is not required, and the first type ion implantation is performed in the area of ​​the well region 3 where the source region 4 is to be formed, thereby forming the source region 4 in the well region 3 .

[0128] Specifically, taking an N-channel MOSFET device as an example, since the well region 3 is P-doped, N-type ions are implanted into the well region 3 to form an N-type ion in the well region 3. + Source area 4.

[0129] Based on step S50, optionally, the method further includes:

[0130] S51: As shown in Figure 10(e), using the fourth preset mask 17, the second type ion implantation is performed on the source region 4 and the well region 3 to form a source contact region 12. The source contact region 12 runs through the source region 4 and the well region 3, and the doping concentration of the source contact region 12 is greater than the doping concentration of the well region 3.

[0131] In step S51, the fourth preset mask 17 can be used to block the well region 3, part of the source region 4 and the area of ​​the first drift region 2 that does not require ion implantation, and the source region 4 and the well region 3 are implanted with the second type of ions to form a source contact region 12, so that the source contact region 12 passes through the source region 4 and the well region 3.

[0132] Specifically, taking an N-channel MOSFET device as an example, since the well region 3 is P-doped and the source region 4 is N-doped + Therefore, in step S51, P-type ion implantation is performed on the source region 4 and the well region 3 to form P ++ Doped source contact region 12 .

[0133] It should be noted that the reference Figure 3 As shown, since the well region 3, the source region 4 and the first drift region 2 all extend along the second direction Y, the second direction Y is parallel to the plane where the SiC substrate 1 is located and perpendicular to the first direction X. Therefore, the multiple source contact regions 12 of the well region 3 are arranged at intervals along the second direction Y.

[0134] S60 : As shown in FIG10( f ), a gate oxide layer 6 and a gate 7 are sequentially formed on the side of the well region 3 and the first region 2 a facing away from the SiC substrate 1 .

[0135] Specifically, in step S60 , the fifth preset mask 18 may be used to block at least a portion of the source region 4 and the source contact region 12 , thereby sequentially depositing the gate oxide layer 6 and the gate 7 on the side of the well region 3 and the first region 2 a facing away from the SiC substrate 1 .

[0136] Optionally, the gate 7 is a polysilicon gate.

[0137] S70 : As shown in FIG. 10( g ), an isolation dielectric layer 8 is formed. The isolation dielectric layer 8 has a through hole extending therethrough. The through hole exposes the source region 4 and the source contact region 12 .

[0138] Specifically, in step S70 , the isolation dielectric layer 8 may be first deposited on the entire surface, and then etched to provide the isolation dielectric layer 8 with through holes that penetrate the isolation dielectric layer 8 , exposing the source region 4 and the source contact region 12 .

[0139] Optionally, both the gate oxide layer 6 and the isolation dielectric layer 8 may be SiO 2 layers.

[0140] S80: As shown in FIG10( h ), a source electrode 9 is formed. The source electrode 9 forms an ohmic contact with the source region 1 through the through hole, and the source electrode 9 forms an ohmic contact with the source contact region 12 through the through hole.

[0141] S90 : As shown in FIG. 10( i ), a drain 10 is formed on the side of the SiC substrate 1 away from the first drift region 2 .

[0142] refer to Figure 3 As shown, the inversion injection region 5 extends along the second direction Y. Since two adjacent inversion injection regions 5 and the drift region between the two adjacent inversion injection regions 5 constitute a JFET region, that is, a back-to-back reverse-biased PN junction, and the drift region between the two adjacent inversion injection regions 5 is electrically connected to the drain 10, in order to provide a potential to each inversion injection region 5, optionally, in one embodiment of the present application, a common contact region 13 is provided on at least one side of the first drift region 2 along the second direction Y, the common contact region 13 and the inversion injection region 5 are both second-type doped, and the common contact region 13 forms an ohmic contact with the source 9, so that each inversion injection region 5 is electrically connected to the source 9 through the common contact region 13.

[0143] Optionally, in step S30, while the second-type ion implantation is performed on the first-type drift region 2 to form the inversion implantation region 5, the second-type ion implantation may be performed on at least one side of the first drift region 2 along the second direction Y to form the common contact region 13. Alternatively, before forming the source 9, the second-type ion implantation may be performed on at least one side of the first drift region 2 along the second direction Y to form the common contact region 13. The specific method may depend on the specific situation.

[0144] Specifically, taking an N-channel MOSFET device as an example, the common contact region 13 may be P ++ Doping.

[0145] Since the structures of various parts of the SiC MOSFET device prepared by the preparation method provided in the embodiments of the present application have been described in detail in the aforementioned embodiments, they will not be repeated here.

[0146] The various parts in this manual are described in a combination of parallel and progressive manners. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0147] With respect to the above description of the disclosed embodiments, the features described in the various embodiments in this specification may be interchanged or combined with one another to enable those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SiC MOSFET device, characterized in that: include: SiC substrate; a first drift region located on one side of the SiC substrate, wherein both the SiC substrate and the first drift region are doped with a first type of doping; Well regions are located on a side of the first drift region facing away from the SiC substrate and are spaced apart along a first direction, the well regions are doped with the second type, source regions are disposed within the well regions, the source regions are doped with the first type, and the first direction is parallel to the plane of the SiC substrate; The first drift region includes a first region between two adjacent well regions and a second region located on a side of the first region and the well region close to the SiC substrate, wherein the second region is provided with a plurality of inversion injection regions spaced apart along the first direction, and the inversion injection regions are doped with the second type; A gate oxide layer, a gate, an isolation dielectric layer and a source electrode are located on a side of the first drift region facing away from the SiC substrate, and a drain electrode is located on a side of the SiC substrate facing away from the first drift region.

2. The SiC MOSFET device according to claim 1, wherein: In the first direction, the distances between any two adjacent inversion injection regions are equal.

3. The SiC MOSFET device according to claim 1, wherein: The surface of the well region facing away from the SiC substrate is a channel region; In the first direction, a distance between two adjacent inversion injection regions far away from the channel region is greater than a distance between two adjacent inversion injection regions close to the channel region.

4. The SiC MOSFET device according to claim 1, wherein: The doping concentration of the inversion implantation region is greater than the doping concentration of the well region.

5. The SiC MOSFET device according to claim 4, wherein: The doping concentration of the inversion injection region is in the range of 1×10 17 cm -3 -1×10 22 cm -3 , including the endpoint values.

6. The SiC MOSFET device according to claim 1, wherein: Also includes: A second drift region is located between the SiC substrate and the first drift region, the second drift region is doped with the first type of doping, and the doping concentration of the first drift region is greater than the doping concentration of the second drift region.

7. The SiC MOSFET device according to claim 6, wherein: The first drift region further includes a third region located between the inversion implantation region and the second drift region.

8. The SiC MOSFET device according to claim 1, wherein: The well region, the source region, and the first drift region all extend along a second direction, and the second direction is parallel to the plane where the SiC substrate is located and perpendicular to the first direction; The well region is also provided with a plurality of source contact regions spaced apart along the second direction, the source contact regions passing through the source region and the well region, the source contact regions being the second type doped, the doping concentration of the source contact regions being greater than the doping concentration of the well region, and the source contact regions forming an ohmic contact with the source electrode.

9. The SiC MOSFET device according to claim 8, wherein: The inversion implantation region extends along the second direction; A common contact region is provided on at least one side of the first drift region along the second direction. The common contact region is doped with the second type and forms an ohmic contact with the source, so that each of the inversion injection regions is electrically connected to the source through the common contact region.

10. A method for preparing a SiC MOSFET device, characterized in that: include: Providing a SiC substrate, forming an epitaxial layer on one side of the SiC substrate, wherein both the SiC substrate and the epitaxial layer are first-type doped; Performing first-type ion implantation on the epitaxial layer to form a first drift region in at least a portion of the epitaxial layer; Using a first preset mask, performing second-type ion implantation on the first drift region to form a plurality of inversion-type implantation regions spaced apart along a first direction in the first drift region, where the first direction is parallel to the plane of the SiC substrate; Using a second preset mask, performing second-type ion implantation on a portion of the inversion implantation region in the first drift region on a side facing away from the SiC substrate to form well regions, wherein the well regions are arranged at intervals along the first direction, so that the first drift region includes a first region between two adjacent well regions and a second region located on a side of the first region and the well region close to the SiC substrate, wherein the inversion implantation region is provided in the second region; Using a third preset mask, performing first-type ion implantation on the well region to form a source region in the well region; forming a gate oxide layer and a gate in sequence on a side of the well region and the first region facing away from the SiC substrate; forming an isolation dielectric layer, wherein the isolation dielectric layer has a through hole extending therethrough, and the through hole exposes the source region; forming a source electrode, wherein the source electrode forms an ohmic contact with the source region through the through hole; A drain is formed on a side of the SiC substrate away from the first drift region.

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