Sensor activation circuit, system, and method

Abstract

The application provides a sensor starting circuit, system and method. The sensor starting circuit comprises a clock circuit and a charge pump circuit. The clock circuit comprises at least two current sources. The clock circuit is configured to generate a frequency-boosted clock signal through the at least two current sources when starting the sensor, and output the frequency-boosted clock signal to the charge pump circuit. The charge pump circuit is configured to generate a starting bias voltage according to the frequency-boosted clock signal, and output the starting bias voltage to the sensor to start the sensor. In the application, the frequency-boosted driving signal is generated through the at least two current sources, and the sensor is started through the starting bias voltage generated rapidly by the frequency-boosted driving signal, so that the delay of the sensor during starting is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of sensors, in particular to a sensor starting circuit, system and method. BACKGROUND

[0002] Based on modern smart phones, TWS smart earphones and smart home and other consumer markets are widely used, so the demand for sensor microphone chips has increased relatively significantly. The sensor microphone is packaged together by a sensor and a chip; the sensor is responsible for receiving sound and converting it into a weak voltage signal, and the chip is responsible for impedance conversion, converting the weak voltage signal into a voltage signal with driving force output.

[0003] The clock of the traditional sensor microphone charge pump is always on after starting and works continuously, consuming power, so the clock is designed to be slow to reduce battery consumption; although the sensor microphone charge pump clock reduces power consumption, the circuit detects that the chip power supply is started and generates a reset signal to the related module, the clock module is reset and starts to generate a clock, and the charge pump is also reset and starts to work after receiving the clock, which cannot quickly generate a high bias voltage for the sensor, and needs to wait for a charge pump charging time, causing the traditional sensor microphone to have a delay in starting.

[0004] The above content is only used to assist in understanding the technical solutions of the present application and does not represent the acknowledgement of the above content as prior art. SUMMARY

[0005] The main purpose of the present application is to provide a sensor starting circuit, system and method, which aims to solve the technical problem of the existing sensor microphone starting with a certain delay.

[0006] To achieve the above purpose, the present application provides a sensor starting circuit, which comprises a clock circuit and a charge pump circuit; the clock circuit comprises at least two current sources;

[0007] The charge pump circuit is connected with the clock circuit and the sensor respectively;

[0008] The clock circuit is used to generate a frequency-raised clock signal through the at least two current sources when the sensor starts, and output the frequency-raised clock signal to the charge pump circuit;

[0009] The charge pump circuit is used to generate a starting bias voltage according to the frequency-raised clock signal, and output the starting bias voltage to the sensor to start the sensor.

[0010] Optionally, the sensor starting circuit further comprises a power reset circuit.

[0011] The power supply reset circuit is connected with a power supply and a clock circuit respectively.

[0012] The power supply reset circuit is configured to detect the power supply, and output a start signal to the clock circuit when a voltage value of the power supply is greater than a preset voltage value.

[0013] The clock circuit is further configured to generate a frequency-boosted clock signal through the at least two current sources when the start signal is received, and output the frequency-boosted clock signal to a charge pump circuit.

[0014] Optionally, the clock circuit comprises a first current source, a second current source, a first switch tube, a first capacitor and an odd number of first inverters.

[0015] The first inverters are connected in series, a control end of the first switch tube is connected with an output end of the power supply reset circuit, an input end of the first switch tube is connected with an output end of the second current source, an output end of the first switch tube is connected with a first end of the first capacitor, an output end of the first current source and the first inverters connected in series, an input end of the first current source is connected with the power supply and an input end of the second current source respectively, the first inverters connected in series are connected with the charge pump circuit, and a second end of the first capacitor is grounded.

[0016] Optionally, the clock circuit further comprises a second switch tube and a second inverter.

[0017] The control end of the second switch tube is connected with an output end of the second inverter, an input end of the second switch tube is connected with the first end of the first capacitor, the output end of the first switch tube, the output end of the second current source and the first inverters connected in series respectively, and an input end of the second inverter is connected with the first inverters connected in series.

[0018] Optionally, the charge pump circuit comprises a bias voltage circuit and a filter circuit.

[0019] The bias voltage circuit is connected with the clock circuit and the filter circuit respectively, and the filter circuit is connected with the sensor.

[0020] The bias voltage circuit is configured to generate a start bias voltage according to the frequency-boosted clock signal, and output the start bias voltage to the filter circuit.

[0021] The filter circuit is configured to filter the start bias voltage to obtain a standard start voltage, and output the standard start voltage to the sensor to start the sensor.

[0022] Optionally, the bias voltage circuit comprises a preset number of second capacitors, the preset number of first diodes, the preset number of third capacitors and the preset number of second diodes.

[0023] The first diodes and the second diodes are sequentially and alternately connected in series, the first ends of the second capacitors are connected to the cathodes of the corresponding first diodes, the second ends of the second capacitors are connected to the input ends of the first inverters connected in series, the first ends of the third capacitors are connected to the cathodes of the corresponding second diodes, and the second ends of the third capacitors are connected to the output ends of the first inverters connected in series.

[0024] Optionally, the bias voltage circuit further comprises a signal processing chip.

[0025] The input end of the signal processing chip is connected to the output end of the first inverters connected in series, the first output end of the signal processing chip is connected to the second ends of the second capacitors, and the second output end of the signal processing chip is connected to the second ends of the third capacitors.

[0026] Optionally, the filter circuit comprises a third diode and a fourth capacitor.

[0027] The input end of the third diode is connected to the output end of the last second diode and the first end of the last third capacitor, the second end of the third diode is connected to the first end of the fourth capacitor and the sensor respectively, and the second end of the fourth capacitor is grounded.

[0028] To achieve the above-mentioned purposes, the application further provides a sensor starting system comprising the sensor starting circuit.

[0029] To achieve the above-mentioned purposes, the application further provides a sensor starting method based on the sensor starting system, which comprises the following steps.

[0030] The clock signal with frequency raised is generated by simultaneously outputting currents by the at least two current sources when the sensor is started;

[0031] The starting bias voltage is generated according to the clock signal with frequency raised, and the starting bias voltage is output to the sensor to start the sensor.

[0032] The application provides a sensor starting circuit, system and method. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the drawings shown.

[0034] Figure 1 The structural schematic diagram of the first embodiment of the sensor starting circuit provided by the present application;

[0035] Figure 2 The variation line graph of the starting bias voltage of the sensor starting circuit provided by the present application;

[0036] Figure 3 The structural schematic diagram of the second embodiment of the sensor starting circuit provided by the present application;

[0037] Figure 4 The circuit diagram of the clock circuit of the second embodiment of the sensor starting circuit provided by the present application;

[0038] Figure 5 The circuit diagram of the charge pump circuit of the second embodiment of the sensor starting circuit provided by the present application;

[0039] Figure 6 The flowchart of the first embodiment of the sensor starting method provided by the present application.

[0040] BRIEF DESCRIPTION OF DRAWINGS

[0041] Reference Name Reference Name 10 Clock circuit VDD Power supply 20 Charge pump circuit C1-C4 First to fourth capacitors 30 Power reset circuit D1-D3 First to third diodes 101 First current source P1-P2 First to second inverters 102 Second current source T1-T2 First to second switches 201 Bias voltage circuit VREF Reference power supply 202 Filter circuit CLOCK1 First clock signal Vt1 First start-up bias voltage CLOCK2 Second clock signal Vt2 Second start-up bias voltage GND Ground

[0042] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the drawings. DETAILED DESCRIPTION

[0043] It should be understood that the specific embodiments described herein are merely exemplary in nature intended to explain the application and not to limit the application.

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0045] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, motion condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications will also change accordingly.

[0046] In addition, the description of "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor is it within the scope of protection claimed by the present application.

[0047] Referring to Figure 1 , Figure 1 The structure schematic diagram of the sensor starting circuit according to the first embodiment of the present application is shown in the figure. Based on Figure 1 , the first embodiment of the sensor starting circuit of the present application is proposed.

[0048] In the embodiment, the sensor starting circuit comprises a clock circuit 10 and a charge pump circuit 20; the clock circuit comprises at least two current sources;

[0049] The charge pump circuit 20 is connected with the clock circuit 10 and the sensor respectively.

[0050] It should be understood that the clock circuit 10 can be used to generate an output clock signal, which is used to control the output starting bias voltage of the charge pump circuit 20. The starting bias voltage is a voltage used to drive the sensor, and the generation rate of the starting bias voltage is positively correlated with the frequency of the clock signal. Referring to Figure 2 , the starting bias voltage is generated by the charge pump circuit 20 under the control of the clock signal. Figure 2The clock signal with higher intermediate frequency generates the start bias voltage faster, that is, the time for the multiple current sources to generate the start bias voltage corresponding to the clock signal is shorter, so that the sensor is started faster, and the delay of the sensor at the time of starting is reduced. The first start bias voltage Vt1 corresponding to the clock signal with frequency promotion, and the second start bias voltage Vt2 corresponding to the clock signal with normal frequency.

[0051] It should be noted that the current source can provide a certain current for the generation of the driving signal. In the clock circuit 10, the more the number of current sources participating in the generation of the clock signal, the greater the current value, and thus the higher the frequency of the output clock signal. In a conventional sensor, usually only one current source is provided, and the current output by the current source generates a normally driven clock signal, and the frequency of the normally driven clock signal is lower than the frequency of the driving signal output by the multiple current sources.

[0052] In a specific implementation, when the sensor needs to be driven, the clock circuit 10 can generate a clock signal with frequency promotion through the at least two current sources, and output the clock signal with frequency promotion to the charge pump circuit 20; the charge pump circuit 20 generates a start bias voltage quickly according to the clock signal with frequency promotion when receiving the clock signal with frequency promotion, and outputs the start bias voltage to the sensor to start the sensor.

[0053] The clock signal with frequency promotion is a signal for controlling the generation of the start bias voltage of the charge pump circuit 20. The start bias voltage is a driving voltage for driving the sensor. The faster the rate of generation of the start bias voltage, the lower the delay of the sensor start.

[0054] The embodiment provides a sensor starting circuit, which comprises a clock circuit and a charge pump circuit; the clock circuit comprises at least two current sources; the clock circuit is used for generating a clock signal with frequency promotion through the at least two current sources when the sensor starts, and outputting the clock signal with frequency promotion to the charge pump circuit; and the charge pump circuit is used for generating a start bias voltage according to the clock signal with frequency promotion, and outputting the start bias voltage to the sensor to start the sensor. In the embodiment, the driving signal with frequency promotion is generated through the at least two current sources, and the sensor is started quickly through the start bias voltage generated by the driving signal with frequency promotion, so that the delay of the sensor at the time of starting is effectively reduced.

[0055] Reference Figure 3 , Figure 3 The structure diagram of the second embodiment of the sensor starting circuit provided by the embodiment of the application is shown. The second embodiment of the sensor starting circuit of the application is proposed based on the first embodiment of the sensor starting circuit.

[0056] In the embodiment, the sensor start-up circuit further comprises a power reset circuit 30.

[0057] The power reset circuit 30 is connected with the power supply VDD and the clock circuit 10 respectively.

[0058] It should be noted that the power reset circuit 30 is a circuit for detecting sensor restart. When the sensor needs to be reset or started up, the power reset circuit 30 can output a driving signal to control the clock circuit 10 to generate a frequency-raised clock signal through multiple current sources. The power reset circuit 30 can collect driving voltage and driving current, and confirm whether the sensor is in a start-up state or a reset state through the change of the driving current or the driving voltage.

[0059] In a specific implementation, the power reset circuit 30 can detect the power supply VDD, and output a start-up signal to the clock circuit when the voltage value of the power supply VDD is greater than a preset voltage value. Of course, the current provided by the power supply VDD can also be collected during the collection process, and a start-up signal can also be output when the current value is greater than a certain value. The clock circuit 10 can generate a frequency-raised clock signal through the at least two current sources when receiving the start-up signal, and output the frequency-raised clock signal to the charge pump circuit 30.

[0060] The preset voltage value is the start-up voltage value of the sensor. The voltage value of the driving power supply VDD should be much smaller than the preset voltage value when the sensor is in a sleep or shutdown state. When the collected voltage value of the driving power supply VDD is greater than or equal to the preset voltage value, it indicates that the sensor is in a start-up state or a reset state. The start-up signal is a signal for starting up the sensor. The start-up signal can directly control the frequency of the clock signal output by the clock circuit 10. For example, when the start-up signal is input, multiple current sources in the clock circuit 10 simultaneously output current, thereby generating a frequency-raised clock signal. When the sensor is in a normal working state or a sleep state, the power reset circuit 30 does not output a start-up signal, and the clock circuit 10 outputs current through one current source to generate a clock signal with a normal frequency.

[0061] Referring to Figure 4 In the embodiment, the clock circuit 10 comprises a first current source 101, a second current source 102, a first switch tube T1, a first capacitor C1, and an odd number of first inverters P1.

[0062] The first switch tube T1 is connected between the first current source 101 and the first capacitor C1, and the control end of the first switch tube T1 is connected with the output end of the power supply reset circuit 30.

[0063] It should be noted that the current value output by the first current source 101 and the current value output by the second current source 102 are not necessarily the same, and the current values output by the two are not limited herein. In the embodiment, the current output by the first current source 101 is the current for generating a clock signal of normal frequency. When the sensor is started, the first current source 101 and the second current source 102 output currents at the same time, so as to generate a clock signal of increased frequency. The first capacitor C1 is an energy storage capacitor. In the process of generating a clock signal, the current source first charges the first capacitor C1, and then the first capacitor C1 outputs the stored energy to generate a clock signal. The first switch tube T1 is a switch tube for controlling whether the loop between the second current source 102 and the first capacitor C1 is turned on. The first switch tube T1 can be a transistor, a MOS tube, a magnetic switch, or any switch tube with a control end, and the specific type of the first switch tube T1 is not limited herein. In the process of generating a clock signal, the number of the first inverters P1 needs to be limited. An odd number of first inverters P1 in series can generate a cyclic oscillation signal, i.e., a clock signal, while an even number of first inverters P1 in series cannot generate a cyclic oscillation signal.

[0064] In a specific implementation, when a clock signal of normal frequency is needed to be output, the power supply reset circuit 30 does not output a start signal to the control end of the first switch tube T1, and the first switch tube T1 is not turned on. At this time, only the first current source 101 charges the first capacitor C1, and the energy storage rate of the first capacitor C1 is relatively slow. After passing through an odd number of first inverters P1, a clock signal of normal frequency is output. When the sensor is started, the power supply reset circuit 30 outputs a start signal to the control end of the first switch tube T1 to turn on the first switch tube T1, so that the first current source 101 and the second current source 102 can simultaneously charge the first capacitor C1. The charging rate of the first capacitor C1 is significantly increased, and the energy released by the first capacitor C1 is output as a clock signal of increased frequency after passing through an odd number of first inverters P1.

[0065] In the embodiment, the clock circuit 10 further comprises a second switch tube T2 and a second inverter P2.

[0066] The control end of the second switch tube T2 is connected with the output end of the second inverter T2, the input end of the second switch tube T2 is connected with the first end of the first capacitor C1, the output end of the first switch tube T1, the output end of the second current source 102 and the first inverter P1 connected in sequence respectively, and the input end of the second inverter P2 is connected with the first inverter P1 connected in sequence.

[0067] It should be noted that the second inverter P2 is an inverter for controlling the energy storage and release of the first capacitor C1. The second switch tube T2 is a switch tube for controlling the on-off between the first current source 101 and the first capacitor C1, and of course the second switch tube T2 also controls the on-off between the second current source 102 and the first capacitor C1.

[0068] In the specific implementation, when a high-level signal is input to the input end of the second inverter P2, that is, the first capacitor C1 is in the energy release state, a low-level signal is output to the second switch tube T2 from the output end of the second inverter P2 after a short energy release, so as to control the second switch tube T2 to be cut off, and the first current source 101 and the second current source 102 can charge the first capacitor C1. Similarly, when a low-level signal is input to the input end of the second inverter P2, a high-level signal is output to the control end of the second switch tube T2 from the output end of the second inverter P2, the second switch tube T2 is turned on, and at this time the first current source 101 and the second current source 102 will not continue to charge the first capacitor C1, and the first capacitor C1 starts to release energy.

[0069] In the embodiment, the charge pump circuit 20 comprises a bias voltage circuit 201 and a filter circuit 202.

[0070] The bias voltage circuit 201 is connected with the clock circuit 10 and the filter circuit 202 respectively, and the filter circuit 202 is connected with the sensor.

[0071] It should be understood that during the starting of the bias voltage output process, there may be certain fluctuations or noise interference in the generated starting bias voltage, at this time, in order to more accurately drive the sensor, the filter circuit 202 can be set to filter the starting bias voltage to reduce the interference.

[0072] It should be noted that the bias voltage circuit 201 is a circuit for outputting a starting bias voltage to drive the sensor. The filter circuit 202 is a circuit for filtering the starting bias voltage. The filter circuit 202 can be an RC filter circuit or a filter circuit composed of components, which is not limited here.

[0073] In specific implementation, the bias voltage circuit 201 generates a starting bias voltage according to the frequency-raised clock signal and outputs the starting bias voltage to the filter circuit 202; the filter circuit 202 filters the starting bias voltage to obtain a standard starting voltage when receiving the starting bias voltage, and outputs the standard starting voltage to the sensor to start the sensor. The standard starting voltage is a voltage obtained after filtering the starting bias voltage.

[0074] With reference to Figure 5 In the embodiment, the bias voltage circuit 201 comprises a preset number of second capacitors C2, a preset number of first diodes D1, a preset number of third capacitors C3 and a preset number of second diodes D2.

[0075] The first diodes D1 and the second diodes D2 are sequentially and alternately connected in series, the first ends of the second capacitors C2 are connected to the cathodes of the corresponding first diodes D1, the second ends of the second capacitors C2 are connected to the input ends of the first inverters P1 connected in series, the first ends of the third capacitors C3 are connected to the cathodes of the corresponding second diodes D2, the second ends of the third capacitors C3 are connected to the output ends of the first inverters P1 connected in series, and the anode of the first first diode D1 is connected to the reference power supply VREF.

[0076] It should be understood that, when the starting bias voltage is output according to the frequency-raised clock signal, the clock signal can be processed into two non-overlapping clock signals to charge the second capacitors C2 and the third capacitors C3 respectively, so as to avoid the leakage.

[0077] In specific implementation, the charging processes of the second capacitors C2 and the third capacitors C3 are controlled by two non-overlapping clock signals. When the first clock signal CLOCK1 is at low level, the reference power supply VREF can charge the second capacitors C2 through the first diodes D1, and at this time, the second clock signal CLOCK2 is at high level, so the reference power supply VREF will not charge the third capacitors C3. When the first clock signal CLOCK1 is at high level and the second clock signal CLOCK2 is at low level, the charging processes of the second capacitors C2 and the third capacitors C3 are completely opposite, which will not be described here.

[0078] In the embodiment, the bias voltage circuit 201 further comprises a signal processing chip.

[0079] The input end of the signal processing chip is connected with the output end of the first inverter P1 connected in series, the first output end of the signal processing chip is connected with the second end of each second capacitor C2, and the second output end of the signal processing chip is connected with the second end of each third capacitor C3.

[0080] It should be noted that the signal processing chip is a chip for processing the frequency-raised clock signal to obtain two non-overlapping clock signals. The frequency of the first clock signal CLOCK1 and the frequency of the second clock signal CLOCK2 are the same as the frequency of the frequency-raised clock signal.

[0081] In a specific implementation, when the signal processing chip receives the frequency-raised clock signal, the frequency-raised clock signal can be taken as the first clock signal CLOCK1, and then the frequency-raised clock signal is obtained through the inverter to obtain the second clock signal CLOCK2. Of course, in the processing process, the frequency-raised clock signal through the inverter can also be taken as the first clock signal CLOCK1, which is not limited here.

[0082] In the embodiment, the filter circuit 202 includes a third diode D3 and a fourth capacitor C4.

[0083] The input end of the third diode D3 is connected with the output end of the last second diode D2 and the first end of the last third capacitor C3, the second end of the third diode D3 is respectively connected with the first end of the fourth capacitor C4 and the sensor, and the second end of the fourth capacitor C4 is grounded.

[0084] It should be noted that in the embodiment, the filter circuit 202 adopts a filter circuit composed of a diode and a capacitor, and the filter circuit 202 filters the starting bias voltage to obtain a standard starting voltage through the charge and discharge characteristics of the fourth capacitor C4.

[0085] In the embodiment, when the sensor normally starts to complete, in order to avoid resource waste, the power supply reset circuit 30 can output a cutoff signal to the control end of the first switch tube T1 to disconnect the connection between the second current source 102 and the first capacitor C1, and the normal work of the sensor can be maintained through the first current source 101.

[0086] The sensor starting circuit in the embodiment comprises a clock circuit and a charge pump circuit; the clock circuit comprises at least two current sources; the clock circuit is configured to generate a frequency-boosted clock signal through the at least two current sources when starting the sensor, and output the frequency-boosted clock signal to the charge pump circuit; and the charge pump circuit is configured to generate a starting bias voltage according to the frequency-boosted clock signal, and output the starting bias voltage to the sensor to start the sensor. In the embodiment, whether to generate a frequency-boosted driving signal or a normal frequency driving signal is determined by controlling whether the second current source charges the first capacitor, and the sensor is started by quickly generating the starting bias voltage through the frequency-boosted driving signal, thereby effectively reducing the delay when starting the sensor.

[0087] To achieve the above object, the present application further provides a sensor starting system comprising the sensor starting circuit as described above. The specific structure of the sensor starting circuit is referred to the above embodiments. Since the sensor starting system device adopts all the technical solutions of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described here one by one.

[0088] To achieve the above object, the present application further provides a sensor starting method, which is referred to Figure 6 , Figure 6 The flowchart of the first embodiment of the sensor starting method provided by the embodiment of the present application is shown in FIG. 1.

[0089] In the embodiment, the sensor starting method comprises:

[0090] Step S10: generating a frequency-boosted clock signal through the at least two current sources when starting the sensor, and outputting the frequency-boosted clock signal to the charge pump circuit;

[0091] Step S20: generating a starting bias voltage according to the frequency-boosted clock signal, and outputting the starting bias voltage to the sensor to start the sensor.

[0092] It should be understood that the clock circuit can be used to generate an output clock signal for controlling the charge pump circuit to output the starting bias voltage. The starting bias voltage is a voltage for driving the sensor, and the generation rate of the starting bias voltage is positively correlated with the frequency of the clock signal. The higher the frequency of the clock signal, the faster the rate of generating the starting bias voltage, i.e., the shorter the time for the multiple current sources to generate the starting bias voltage corresponding to the clock signal, so that the sensor is started faster, and the delay when starting the sensor is reduced.

[0093] It should be noted that the current source can provide a certain current for the generation of the driving signal. In the clock circuit, the more the number of current sources participating in the generation of the clock signal, the greater the current value, and thus the higher the frequency of the output clock signal. In a conventional sensor, usually only one current source is provided, and a normally driven clock signal is generated by outputting current from the current source, and the frequency of the normally driven clock signal is lower than the frequency of the driving signal output by multiple current sources.

[0094] In a specific implementation, when the sensor needs to be driven, the clock circuit 10 can generate a frequency-raised clock signal through the at least two current sources and output the frequency-raised clock signal to the charge pump circuit; the charge pump circuit, upon receiving the frequency-raised clock signal, rapidly generates a start-up bias voltage according to the frequency-raised clock signal and outputs the start-up bias voltage to the sensor to start up the sensor.

[0095] The frequency-raised clock signal is a signal for controlling the generation of the start-up bias voltage of the charge pump circuit. The start-up bias voltage is a driving voltage for driving the sensor. The faster the start-up bias voltage is generated, the lower the sensor start-up delay.

[0096] The embodiment provides a sensor start-up method. The sensor start-up circuit method generates a frequency-raised clock signal through the at least two current sources when the sensor starts up through the clock circuit and outputs the frequency-raised clock signal to the charge pump circuit; the charge pump circuit generates a start-up bias voltage according to the frequency-raised clock signal and outputs the start-up bias voltage to the sensor to start up the sensor. In the embodiment, the frequency-raised driving signal is generated through the at least two current sources, and the sensor is started up through the frequency-raised driving signal to rapidly generate the start-up bias voltage, thereby effectively reducing the delay of the sensor start-up.

[0097] In addition, the sensor start-up method further includes other steps. Since the sensor start-up method is based on the above-described sensor start-up system, the related control logic involved in the sensor start-up system is within the protection scope of the sensor start-up method.

[0098] The above merely describes the preferred embodiments of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation based on the content of the specification and drawings of the present application, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A sensor activation circuit, characterized in that, The sensor startup circuit includes a clock circuit and a charge pump circuit; the clock circuit includes at least two current sources. The charge pump circuit is connected to both the clock circuit and the sensor. The clock circuit is used to generate a frequency-enhanced clock signal through the at least two current sources when the sensor is activated, and to output the frequency-enhanced clock signal to the charge pump circuit. The charge pump circuit is used to generate a start-up bias voltage based on a clock signal with increased frequency, and output the start-up bias voltage to the sensor to start the sensor. The sensor startup circuit also includes: a power reset circuit; The power reset circuit is connected to both the power supply and the clock circuit. The power reset circuit is used to detect the power supply and output a start signal to the clock circuit when the voltage value of the power supply is greater than a preset voltage value. The clock circuit is further configured to generate a frequency-enhanced clock signal through the at least two current sources upon receiving the start signal, and output the frequency-enhanced clock signal to the charge pump circuit.

2. The sensor activation circuit as described in claim 1, characterized in that, The clock circuit includes: a first current source, a second current source, a first switching transistor, a first capacitor, and an odd number of first inverters; In this configuration, each first inverter is connected in series. The control terminal of the first switching transistor is connected to the output terminal of the power reset circuit. The input terminal of the first switching transistor is connected to the output terminal of the second current source. The output terminal of the first switching transistor is connected to the first terminal of the first capacitor, the output terminal of the first current source, and the first inverters connected in series. The input terminal of the first current source is connected to the power supply and the input terminal of the second current source, respectively. The first inverters connected in series are connected to the charge pump circuit. The second terminal of the first capacitor is grounded.

3. The sensor activation circuit as described in claim 2, characterized in that, The clock circuit also includes: a second switching transistor and a second inverter; In this configuration, the control terminal of the second switching transistor is connected to the output terminal of the second inverter, the input terminal of the second switching transistor is connected to the first terminal of the first capacitor, the output terminal of the first switching transistor, the output terminal of the second current source, and the first inverter connected in series, respectively, and the input terminal of the second inverter is connected to the first inverter connected in series.

4. The sensor activation circuit as described in claim 3, characterized in that, The charge pump circuit includes: a bias voltage circuit and a filter circuit; The bias voltage circuit is connected to the clock circuit and the filter circuit respectively, and the filter circuit is connected to the sensor. The bias voltage circuit is used to generate a startup bias voltage according to the clock signal with increased frequency, and output the startup bias voltage to the filter circuit. The filtering circuit is used to filter the start-up bias voltage to obtain a standard start-up voltage, and output the standard start-up voltage to the sensor to start the sensor.

5. The sensor activation circuit as described in claim 4, characterized in that, The bias voltage circuit includes: a preset number of second capacitors, a preset number of first diodes, a preset number of third capacitors, and a preset number of second diodes; In this configuration, each first diode and each second diode are connected in series at intervals. The first terminal of each second capacitor is connected to the cathode of the corresponding first diode. The second terminal of each second capacitor is connected to the input terminal of the first inverter connected in series. The first terminal of each third capacitor is connected to the cathode of the corresponding second diode. The second terminal of each third capacitor is connected to the output terminal of the first inverter connected in series.

6. The sensor activation circuit as described in claim 5, characterized in that, The bias voltage circuit further includes: a signal processing chip; The input terminal of the signal processing chip is connected to the output terminal of the first inverter connected in series, the first output terminal of the signal processing chip is connected to the second terminal of each of the second capacitors, and the second output terminal of the signal processing chip is connected to the second terminal of each of the third capacitors.

7. The sensor activation circuit as described in claim 6, characterized in that, The filter circuit includes: a third diode and a fourth capacitor; The input terminal of the third diode is connected to the output terminal of the last second diode and the first terminal of the last third capacitor. The second terminal of the third diode is connected to the first terminal of the fourth capacitor and the sensor. The second terminal of the fourth capacitor is grounded.

8. A sensor activation system, characterized in that, The sensor activation system includes the sensor activation circuit as described in any one of claims 1-7.

9. A sensor activation method based on the sensor activation system of claim 8, characterized in that, The sensor activation method includes: When the sensor is activated, a clock signal with an increased current generation frequency is simultaneously output from the at least two current sources. A startup bias voltage is generated based on a clock signal with increased frequency, and the startup bias voltage is output to the sensor to start the sensor.

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