A single-edge master-slave trigger and trigger module based on TFET

Abstract

The present invention relates to the field of dynamic random access storage technology, and more specifically, to a single-edge master-slave trigger based on TFET, also known as TDFF, and a trigger module designed based on the TDFF. The TDFF of the present invention includes 12 PTFET transistors, 13 NTFET transistors, and an inverter INV. The present invention constructs a trigger based on TFET, and does not use a transmission gate or a transmission tube structure, thereby avoiding the problem of positive-biased P-I-N current caused by the transmission gate. Instead, the correct transmission of data is controlled by an intermediate node and a clock signal CLK. Although the CLK of the present invention is a single-phase clock, it is combined with the circuit design of the TFET transistor, and the trigger function can be realized without setting a clock inverter for CLK. And after simulation testing, the power consumption index of the present invention is low, which has a greater advantage.

Description

Technical Field

[0001] The present invention relates to the field of dynamic random access memory technology, and more specifically, to a single-edge master-slave trigger (TDFF) based on a TFET (Tunneling Field-Effect Transistor), and a trigger module designed based on the TDFF. Background Art

[0002] A flip-flop is a memory cell circuit that operates only when triggered by a clock signal, unlike a latch, which is not controlled by a clock signal. Generally, flip-flops are designed using CMOS (e.g., Metal Oxide Semiconductor Field Effect Transistor, MOSFET) technology.

[0003] Ideally, a MOSFET has a high on-state current when operating and little or no leakage current when off. However, as device dimensions continue to shrink, secondary effects become increasingly apparent, leakage current increases, and power consumption per unit area also increases, making this ideal state increasingly difficult to achieve. At 65nm, the static and dynamic power consumption of chips is already quite close. Increased power consumption in CMOS circuits can cause fluctuations in device operating conditions, affecting chip quality. Furthermore, increased leakage current significantly impacts the static power consumption of circuits. Reducing static power consumption requires reducing the supply voltage (VDD) and off-state current (Ioff), which necessitates a higher on-off ratio and smaller subthreshold swing (SS).

[0004] To address the issue of reducing chip power consumption, researchers have proposed techniques such as gated clocks and multiple power supply voltages. These technologies can reduce circuit power consumption to a certain extent, but they also increase circuit complexity. Because the conduction mechanism of MOSFET devices relies on carrier drift diffusion, the subthreshold swing (SS) of MOSFETs is difficult to break through the 60mV / dec limit at room temperature. The most direct way to reduce power consumption is to lower the power supply voltage, but lowering the power supply voltage will reduce the current on / off ratio and even make the circuit difficult to operate normally. This led to the emergence of the Fin Field Effect Transistor (FinFET), which has attracted widespread attention for its large gate-to-channel contact area and excellent gate control capability. However, it still struggles to break through 60mV / edc at room temperature. As transistor size decreases, leakage power becomes a major issue in the design of energy-efficient, high-performance circuits.

[0005] Therefore, the inventors have adopted the tunnel field-effect transistor (TFET) as a new alternative device. TFET has attracted much attention due to its band-to-band tunneling working mechanism: for N-type TFET, it is not affected by thermal electron emission, and the tunneling of electrons occurs between energy bands. There is no Fermi tailing effect, so its subthreshold swing can be lower than 60mv / dec. Compared with MOSFET, under the condition of a smaller gate-source voltage (Vgs), TFET has a larger on-current than MOSFET and a stronger driving capability. In addition, TFET has the process of manufacturing of traditional MOSFET, can work at low voltage, has a higher switching ratio, and thus can reduce circuit power consumption, so under low voltage, the performance of TFET is better than MOSFET. However, for TFET, when it forms a transmission gate structure, it is easy to have a PIN current that is not gate-controlled, which may cause transmission errors. Summary of the Invention

[0006] Based on this, it is necessary to provide a single-edge master-slave trigger and trigger module based on TFET to address the problem that the existing trigger has high power consumption when designed based on MOSFET and is prone to PIN current when designed based on TFET.

[0007] The present invention is achieved by adopting the following technical solutions:

[0008] In a first aspect, the present invention provides a TFET-based single-edge master-slave trigger, comprising 12 PTFET transistors (P1-P12), 13 NTFET transistors (N1-N13), and an inverter INV.

[0009] An input terminal of the inverter INV is connected to the input signal D, and an output terminal is connected to the inverted signal DB.

[0010] The source of P1 is connected to the power supply VDD, and the gate is connected to the clock signal CLK. The source of P2 is connected to the drain of P1, and the gate is connected to the input signal D. The source of P3 is connected to the power supply VDD, and the gate is connected to the inverted signal DB. The source of P4 is connected to the drain of P3, and the gate is connected to the clock signal CLK. The source of P5 is connected to the power supply VDD, the gate is connected to the drain of P2, and an intermediate node DN is provided.

[0011] The drain of N1 is connected to the drain of P2, and its gate is connected to the drain of P4, with an intermediate node A provided. The source of N2 is grounded GND, its gate is connected to the input signal D, and its drain is connected to the source of N1. The drain of N3 is connected to the drain of P4, and its gate is connected to the inverted signal DB. The source of N4 is grounded GND, its gate is connected to the clock signal CLK, and its drain is connected to the source of N3. The source of N5 is connected to the drain of N4, its gate is connected to the drain of P5, with an intermediate node B provided. The drain of N5 is connected to the gate of P5, with an intermediate node DN provided.

[0012] The source of P6 is connected to power supply VDD, and its gate is connected to clock signal CLK. The source of P7 is connected to power supply VDD, and its gate is connected to intermediate node A. The source of P8 is connected to the drain of P7, and its gate is connected to intermediate node B. The source of P9 is connected to power supply VDD, its gate is connected to the drain of P6, and intermediate node C is provided. The source of P10 is connected to power supply VDD, its gate is connected to clock signal CLK. The source of P11 is connected to the drain of P10, its drain is connected to the drain of P9, and output node Q is provided. The source of P12 is connected to power supply VDD, and its gate is connected to the drain of P9.

[0013] The source of N6 is connected to ground GND, its gate is connected to the gate of P5, and its drain is connected to the drain of P5. The source of N7 is connected to the drain of N4, its gate is connected to the gate of N6, and its drain is connected to the drain of P5. The drain of N8 is connected to the drain of P6, and its gate is connected to the clock signal CLK. The source of N9 is connected to ground GND, its gate is connected to the intermediate node B, and its drain is connected to the source of N8. The drain of N10 is connected to the drain of P9, and its gate is connected to the clock signal CLK. The source of N11 is connected to ground GND, its gate is connected to the gate of P9, and its drain is connected to the source of N10. The source of N12 is connected to the drain of N11, its gate is connected to the gate of P11, and its drain is connected to the drain of P11. The source of N13 is connected to ground GND, its gate is connected to the gate of P12, and it has an intermediate node QN, and its drain is connected to the drain of P12.

[0014] The implementation of the TFET-based single-edge master-slave trigger is a method or process according to an embodiment of the present disclosure.

[0015] In a second aspect, the present invention discloses a trigger module that adopts the circuit layout of a single-edge master-slave trigger based on TFET as disclosed in the first aspect. The pins of this trigger module include 5 pins. Among them, the first pin is connected to the gates of P2 and N2 for transmitting the input signal D. The second pin is connected to the gates of P1, P4, N4, P6, N8, P10, and N10 for transmitting the clock signal CLK. The third pin is connected to the source of P1, P3, P5, P6, P7, P9, P10, and P12 for connecting to the power supply VDD. The fourth pin is connected to the source of N2, N4, N6, N9, N11, and N13 for grounding GND. The fifth pin is connected to the output node Q for outputting data.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention uses a TFET-based trigger, without using a transmission gate or transmission tube structure, thus avoiding the forward-biased PIN current problem caused by the transmission gate. Instead, the correct transmission of data is controlled through an intermediate node and a clock signal CLK. Although the CLK of the present invention is a single-phase clock, the circuit design of the TFET transistor does not require a clock inverter for CLK to achieve the trigger function. Furthermore, simulation tests have shown that the present invention has low power consumption indicators, which is a significant advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A circuit structure diagram of a TFET-based single-edge-triggered master-slave trigger (TDFF) provided in Example 1 of the present invention;

[0020] Figure 2 for Figure 1 The simulation waveform of TDFF in ;

[0021] Figure 3 The circuit structure diagram of the first single-edge-triggered master-slave trigger (TSPC) in the prior art;

[0022] Figure 4 It is the second single edge master-slave trigger (S 2 CFF) circuit structure diagram;

[0023] Figure 5The circuit structure diagram of the third single edge-triggered master-slave trigger (ESRFF) in the prior art;

[0024] Figure 6 1 is a circuit diagram of a fourth type of single-edge-triggered master-slave trigger (CSRFF) in the prior art;

[0025] Figure 7 for Figure 1 Comparison waveform of dynamic power consumption of TDFF and four types of triggers in the prior art;

[0026] Figure 8 This is a structural diagram of the trigger chip provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0028] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0030] Example 1

[0031] See Figure 1 , is a circuit structure diagram of a single-edge-triggered master-slave trigger (TDFF) based on TFET provided in this embodiment 1. Figure 1 As shown, the TDFF includes 12 PTFET transistors (P1 to P12), 13 NTFET transistors (N1 to N13), and an inverter INV.

[0032] An input terminal of the inverter INV is connected to the input signal D, and an output terminal is connected to the inverted signal DB.

[0033] The source of P1 is connected to the power supply VDD, and the gate is connected to the clock signal CLK. The source of P2 is connected to the drain of P1, and the gate is connected to the input signal D. The source of P3 is connected to the power supply VDD, and the gate is connected to the inverted signal DB. The source of P4 is connected to the drain of P3, and the gate is connected to the clock signal CLK. The source of P5 is connected to the power supply VDD, the gate is connected to the drain of P2, and an intermediate node DB is provided.

[0034] The drain of N1 is connected to the drain of P2, and its gate is connected to the drain of P4, with an intermediate node A provided. The source of N2 is grounded GND, its gate is connected to the input signal D, and its drain is connected to the source of N1. The drain of N3 is connected to the drain of P4, and its gate is connected to the inverted signal DB. The source of N4 is grounded GND, its gate is connected to the clock signal CLK, and its drain is connected to the source of N3. The source of N5 is connected to the drain of N4, its gate is connected to the drain of P5, with an intermediate node B provided. The drain of N5 is connected to the gate of P5, with an intermediate node DN provided.

[0035] The source of P6 is connected to power supply VDD, and its gate is connected to clock signal CLK. The source of P7 is connected to power supply VDD, and its gate is connected to intermediate node A. The source of P8 is connected to the drain of P7, and its gate is connected to intermediate node B. The source of P9 is connected to power supply VDD, its gate is connected to the drain of P6, and intermediate node C is provided. The source of P10 is connected to power supply VDD, its gate is connected to clock signal CLK. The source of P11 is connected to the drain of P10, its drain is connected to the drain of P9, and output node Q is provided. The source of P12 is connected to power supply VDD, and its gate is connected to the drain of P9.

[0036] The source of N6 is connected to ground GND, its gate is connected to the gate of P5, and its drain is connected to the drain of P5. The source of N7 is connected to the drain of N4, its gate is connected to the gate of N6, and its drain is connected to the drain of P5. The drain of N8 is connected to the drain of P6, and its gate is connected to the clock signal CLK. The source of N9 is connected to ground GND, its gate is connected to the intermediate node B, and its drain is connected to the source of N8. The drain of N10 is connected to the drain of P9, and its gate is connected to the clock signal CLK. The source of N11 is connected to ground GND, its gate is connected to the gate of P9, and its drain is connected to the source of N10. The source of N12 is connected to the drain of N11, its gate is connected to the gate of P11, and its drain is connected to the drain of P11. The source of N13 is connected to ground GND, its gate is connected to the gate of P12, and it has an intermediate node QN, and its drain is connected to the drain of P12.

[0037] The above connection relationship can also be expressed as:

[0038] The input signal D is connected to the gate of P2, the gate of N2, and the input terminal of INV.

[0039] The inverted signal DB is connected to the output of INV, the gate of P3, and the gate of N3.

[0040] The clock signal CLK is connected to the gate of P1 , the gate of P4 , the gate of N4 , the gate of P6 , the gate of N8 , the gate of N10 , and the gate of P10 .

[0041] The source of P1 , the source of P3 , the source of P5 , the source of P6 , the source of P7 , the source of P9 , the source of P10 , and the source of P12 are connected to the power supply VDD.

[0042] The source of N2, the source of N4, the source of N6, the source of N9, the source of N11, and the source of N13 are grounded GND.

[0043] The drain of P1 is connected to the source of P2.

[0044] The drain of P2 is connected to the drain of N1, the gate of P5, the gate of N6, the drain of N5, and the gate of N7, and the node therebetween is defined as an intermediate node DN.

[0045] The gate of N1 is connected to the drain of P4, the drain of N3, the gate of P7, the drain of N2, and the gate of P7, and the node therebetween is defined as an intermediate node A.

[0046] The drain of P3 is connected to the source of P4.

[0047] The drain of N4 is connected to the source of N3, the source of N5, and the source of N7.

[0048] The drain of P5 is connected to the drain of N6, the gate of N5, the drain of N7, the gate of N9, and the gate of P8, and the node therebetween is defined as an intermediate node B.

[0049] The drain of P6 is connected to the drain of N8, the drain of P8, the gate of P9 and the gate of N11, and the node therebetween is defined as an intermediate node C.

[0050] The drain of N9 is connected to the source of N8.

[0051] The drain of P7 is connected to the drain of P8.

[0052] The drain of P9 is connected to the drain of N10, the drain of P11, the gate of P12, the gate of N13, and the drain of N12, and the node therebetween is defined as the output node Q.

[0053] The drain of N11 is connected to the source of N10 and the source of N12.

[0054] The drain of P10 is connected to the source of P11.

[0055] The drain of P12 is connected to the gate of P11, the gate of N12, and the drain of N13, and the node therebetween is defined as an intermediate node QN.

[0056] The above circuit structure can be divided into master and slave stages. The master stage includes N1, N2, N3, N4, N5, N6, N7, P1, P2, P3, P4, P5, and INV. The slave stage includes P6, P7, P8, P9, P10, P11, P12, N8, N9, N10, N11, and N12.

[0057] In general, TDFF works periodically. The CLK state in each cycle includes a low level in the first stage and a high level in the second stage. CLK is triggered by a rising single edge.

[0058] If the current cycle CLK is in the first phase, the master stage transmits the data of the input signal D, and the slave stage stores the data transmitted by the master stage when CLK was in the second phase in the previous cycle.

[0059] If the current cycle CLK is in the second phase, the master stage stores the data of the input signal D transmitted when the current cycle CLK is in the first phase, and the slave stage transmits the data transmitted from the master stage when CLK is in the first phase in the previous cycle.

[0060] Of course, when TDFF starts working, the output node Q of the slave stage is initially pre-stored with "0" or "1". As the periodic work starts, the pre-stored data of the output node Q will be overwritten by the data transmitted from the master stage in the previous cycle.

[0061] Simply put, if the current cycle CLK is in the first phase, the input signal D is high, and the middle node B is correspondingly high. Then, when the current cycle CLK is in the second phase, regardless of whether the input signal D is high or low, the middle node B remains high. Correspondingly, if the current cycle CLK is in the first phase, the output node Q stores the data transmitted from the master when CLK was in the second phase in the previous cycle. Then, when the current cycle CLK is in the second phase, the middle node B is high, and the output node Q is correspondingly high.

[0062] If the current CLK cycle is in the first phase, input signal D is low, and intermediate node B is correspondingly low. Next, when the current CLK cycle is in the second phase, regardless of whether input signal D is high or low, intermediate node B remains low. Accordingly, if the current CLK cycle is in the first phase, output node Q stores the data transmitted from the master during the previous cycle when CLK was in the second phase. Next, when the current CLK cycle is in the second phase, intermediate node B is low, and output node Q is correspondingly low.

[0063] See Figure 2 Taking the output node Q as an example, several working situations are explained in detail, which is also the working principle of TDFF:

[0064] (1) The output node Q flips from 0 to 1, meaning that Q already stores “0” and is about to be written with “1”.

[0065] The input signal D is "1" (high level), DB is the inverted version of D and is low level, N2 is turned on, and P3 is turned on.

[0066] If the clock signal CLK is at a low level, for the master stage, P1 and P4 are turned on, A is connected to VDD through P3 and P4 and charged, and A is at a high level; the high-level A turns on N1, and DN is grounded to GND through N1 and N2, so that DN is discharged to a low level; the low-level DN turns on P5, and B is connected to VDD through P5 and charged, and B is at a high level; in the above process, for the slave stage, P6 is turned on, and C is connected to VDD through P6 and charged, and C is at a high level. The high-level C turns on N11, and Q stores "0" (low level), QN is at a high level, N12 is turned on, and Q is grounded through N11 and N12 and maintained at a low level.

[0067] Then, when the clock rising edge arrives (CLK becomes high level), for the main stage, P1 and P4 are closed and N4 is opened;

[0068] If the input signal D remains high, DB is low, N2 is open, N3 is closed, A maintains its original state at a high level, N1 is open, DN is discharged to a low level through N1 and N2, and B is high, consistent with the input signal D; the high-level B opens N5, DN is grounded through N5 and N4 and maintained at a low level, thereby maintaining B at a high level;

[0069] If the input signal D jumps and becomes a low level, A remains in its original state (that is, the state when D is high and CLK is low), P3 and P4 are turned on, A is high, DN is low, and B is high, which means that the change of the input signal D will not affect B.

[0070] For the slave stage, N8 is turned on, N9 is turned on, C is discharged to the ground through N8 and N9 to a low level, the low level C turns on P9, Q is connected to VDD through P9 and charged, Q is a high level, consistent with the input signal D.

[0071] (2) The output node Q changes from 0 to 0, which means that Q has stored “0” and is about to be written with “0”.

[0072] The input signal D is "0" (low level), DB is the inverted signal of D and is high level, P2 is turned on, and N3 is turned on.

[0073] If the clock signal CLK is at a low level, for the master stage, P1 and P4 are turned on, DN is connected to VDD through P1 and P2 and charged, DN is at a high level, and B is at a low level; in the above process, for the slave stage, P6 is turned on, C is connected to VDD through P6 and charged, C is at a high level, the high level C turns on N11, Q stores "0" (low level), QN is at a high level, N12 is turned on, Q is grounded through N11 and N12, and maintained at a low level.

[0074] Then, when the clock rising edge arrives (CLK becomes high level), for the main stage, P1 and P4 are closed and N4 is opened;

[0075] If the input signal D remains at a low level, DB is at a high level, N2 is closed, N3 is open, and A is discharged to a low level through N3 and N4. The low level A closes N1, and the input signal D cannot be input to the main stage. DN maintains its original state at a high level, and B is at a low level, consistent with the input signal D; the high level DN opens N7, and B is grounded through N7 and N4 and maintained at a low level;

[0076] If the input signal D jumps and becomes high, A remains in its original state (that is, the state when D is low and CLK is high), N3 and N4 are turned on, A is low, DN remains in its original state at high, and B is low, which means that the change of the input signal D will not affect B.

[0077] For the slave stage, N8 is turned on, N9 is turned off, N10 is turned on, P8 is turned on, P7 is turned on, C is connected to VDD through P8 and P7 and charged, C is high level, the high level C turns on N11, Q is discharged to the ground through N10 and N11; Q is low level, which is consistent with the input signal D.

[0078] (3) The output node Q flips from 1 to 0, that is, Q has stored "1" and is about to be written to "0".

[0079] The input signal D is "0" (low level), DB is inverted from D and is high level, P2 is turned on, and N3 is turned on; if the clock signal CLK is low level, for the master stage, P1 and P4 are turned on, DN is connected to VDD through P1 and P2 and charged, DN is high level, and B is low level; in the above process, for the slave stage, P6 and P10 are turned on, C is connected to VDD through P6 and charged, C is high level, the high level C turns on N11, Q stores "1" (high level), QN is low level, P11 is turned on, Q is connected to VDD through P11 and P10 and charged, and maintained at a high level.

[0080] Then, when the clock rising edge arrives (CLK becomes high level), for the main stage, P1 and P4 are closed and N4 is opened;

[0081] If the input signal D remains at a low level, DB is at a high level, N3 is turned on, A is grounded through N3 and N4 and discharged to a low level, the low-level A turns off N1, the input signal D cannot be input to the main stage, DN maintains its original state at a high level, and B is at a low level; the high-level DN turns on N7, and B is grounded through N7 and N4 and maintained at a low level;

[0082] If the input signal D jumps and becomes high, A remains in its original state (that is, the state when D is low and CLK is high), N3 and N4 are turned on, A is low, DN remains in its original state at high, and B is low, which means that the change of the input signal D will not affect B.

[0083] For the slave stage, N8 is turned on, N9 is turned off, N10 is turned on, P7 is turned on, P8 is turned on, C is connected to VDD through P8 and P7 and charged, C is high level, the high level C turns on N11, Q is discharged to the ground through N10 and N11; Q is low level, consistent with the input signal D.

[0084] (4) The output node Q changes from 1 to 1, which means that Q has stored "1" and is about to be written with "1".

[0085] The input signal D is "1" (high level), DB is inverted from D and is low level, N2 is turned on, P3 is turned on; if the clock signal CLK is low level, for the master stage, P1 and P4 are turned on, A is connected to VDD through P3, P4 and charged, and A is high level; the high level A turns on N1, DN is grounded to GND through N1 and N2, so that DN is discharged to a low level; the low level DN turns on P5, B is connected to VDD through P5 and charged, and B is high level; in the above process, for the slave stage, P6 and P10 are turned on, C is connected to VDD through P6 and charged, C is high level, the high level C turns on N11, Q stores "1" (high level), QN is low level, P11 is turned on, Q is connected to VDD through P11 and P10 and charged, and maintained at a high level.

[0086] Then, when the clock rising edge arrives (CLK becomes high level), for the main stage, P1 and P4 are closed and N4 is opened;

[0087] If the input signal D remains at a high level, DB is at a low level, N2 is open, N3 is closed, and A maintains its original state (that is, the state when D is high and CLK is low). At this time, A is high, N1 and N2 are open, DN is low, and B is high.

[0088] If the input signal D jumps and becomes low, N2 is closed. Since P1 is also closed, DN maintains its original state at a low level and B is high, which means that the change of the input signal D does not affect B.

[0089] For the slave stage, N8 is turned on, N9 is turned on, C is discharged to the ground through N8 and N9 to a low level, the low level C turns on P9, Q is connected to VDD and charged, Q is a high level, which is consistent with the input signal D.

[0090] From the above, it can be seen that the present TDFF can correctly transmit and store data.

[0091] In order to verify the power consumption of TDFF, this embodiment 1 also compares TDFF with four single-edge master-slave triggers (TSPC, S 2 CFF, ESRFF, CSRFF) were simulated and compared, and the simulation conditions were Corner: TT; Temperature: 27℃; VDD: 0.6V. Among them, the circuit of TSPC is shown in Figure 3 , S 2 CFF circuit reference Figure 4 , ESRFF circuit see Figure 5 , CSRFF circuit see Figure 6 Among them, the frequency of the input signal D is adjustable, and the switching factor α is generally used. D Characterization. α D The larger the value, the greater the input signal D D The higher the frequency of change. D The smaller it is, the smaller the frequency of change of the input signal D is. Theoretically, α D Positively correlated with power consumption.

[0092] See Figure 7 , is the power consumption comparison chart of the simulation, and each single-edge master-slave trigger takes multiple averages. It can be seen that TDFF is D = 0, the power consumption is slightly greater than CSREF and ESREF, and significantly less than TSPC and S 2 CFF. TDFF in α D = 20%, 50%, 100%, the power consumption is significantly less than CSREF, ESREF, TSPC, S 2 Therefore, it can be said that TDFF has the greater advantage of low power consumption.

[0093] The low power consumption advantage of TDFF can also be analyzed from the principle:

[0094] Because it uses TFET tubes, it can reduce power consumption compared to CMOS technology. For the intermediate node C, its charging only requires P7~P8 or P6 to be turned on, avoiding the redundant charging process of C, thereby reducing power consumption. In addition, the frequency of the clock signal CLK changes using the switching factor α CLK If a two-phase clock is used, a clock inverter needs to be introduced inside the trigger to generate the clock inversion signal CLKB. This can reduce the clock load and the switching factor α CLK However, the TDFF only uses a single-phase clock and, in combination with the circuit design of the TFET transistor described above, can realize the trigger function without setting a clock inverter for CLK, thus reducing power consumption.

[0095] Example 2

[0096] This embodiment 2 discloses a trigger module, which adopts the circuit layout of the TFET-based single-edge master-slave trigger of embodiment 1. The module packaging mode makes it easier to promote and apply the above-mentioned TDFF.

[0097] This trigger module has five pins. The first pin is connected to the gates of P2 and N2 for transmitting the input signal D. The second pin is connected to the gates of P1, P4, N4, P6, N8, P10, and N10 for transmitting the clock signal CLK. The third pin is connected to the sources of P1, P3, P5, P6, P7, P9, P10, and P12 for connection to the power supply VDD. The fourth pin is connected to the sources of N2, N4, N6, N9, N11, and N13 for ground GND. The fifth pin is connected to the output node Q for outputting data.

[0098] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A single-edge-triggered master-slave trigger based on TFET, characterized in that: include: The inverter INV has an input terminal connected to the input signal D and an output terminal connected to the inverted signal DB; A PTFET transistor P1, having a source connected to a power supply VDD and a gate connected to a clock signal CLK; PTFET transistor P2, whose source is connected to the drain of P1 and whose gate is connected to the input signal D; A PTFET transistor P3, whose source is connected to the power supply VDD and whose gate is connected to the inverting signal DB; PTFET transistor P4, whose source is connected to the drain of P3 and whose gate is connected to the clock signal CLK; a PTFET transistor P5 , whose source is connected to the power supply VDD, whose gate is connected to the drain of P2 and which is provided with an intermediate node DN; NTFET transistor N1, whose drain is connected to the drain of P2, whose gate is connected to the drain of P4 and which is provided with an intermediate node A; NTFET transistor N2, with its source connected to the ground GND, its gate connected to the input signal D, and its drain connected to the source of N1; NTFET transistor N3, whose drain is connected to the drain of P4 and whose gate is connected to the inverting signal DB; An NTFET transistor N4 has a source connected to the ground GND, a gate connected to the clock signal CLK, and a drain connected to the source of N3; NTFET transistor N5, with its source connected to the drain of N4, its gate connected to the drain of P5 and provided with an intermediate node B, and its drain connected to the gate of P5 and provided with an intermediate node DN; A PTFET transistor P6 , having a source connected to a power supply VDD and a gate connected to a clock signal CLK; a PTFET transistor P7 , having a source connected to the power supply VDD and a gate connected to the intermediate node A; a PTFET transistor P8 , having a source connected to the drain of P7 and a gate connected to the intermediate node B; a PTFET transistor P9 , having a source connected to the power supply VDD, a gate connected to the drain of P6 and an intermediate node C; A PTFET transistor P10 , having a source connected to a power supply VDD and a gate connected to a clock signal CLK; a PTFET transistor P11 , whose source is connected to the drain of P10 , whose drain is connected to the drain of P9 and which is provided with an output node Q; a PTFET transistor P12, having a source connected to the power supply VDD and a gate connected to the drain of P9; an NTFET transistor N6 , having a source connected to the ground GND, a gate connected to the gate of P5 , and a drain connected to the drain of P5 ; NTFET transistor N7, with its source connected to the drain of N4, its gate connected to the gate of N6, and its drain connected to the drain of P5; NTFET transistor N8, having a drain connected to the drain of P6 and a gate connected to the clock signal CLK; an NTFET transistor N9 , having a source connected to the ground GND, a gate connected to the intermediate node B, and a drain connected to the source of N8 ; NTFET transistor N10, having a drain connected to the drain of P9 and a gate connected to the clock signal CLK; NTFET transistor N11, whose source is connected to ground GND, whose gate is connected to the gate of P9, and whose drain is connected to the source of N10; NTFET transistor N12, whose source is connected to the drain of N11, whose gate is connected to the gate of P11, and whose drain is connected to the drain of P11; and The NTFET transistor N13 has a source connected to the ground GND, a gate connected to the gate of P12 and provided with an intermediate node QN, and a drain connected to the drain of P12.

2. The TFET-based single-edge-triggered master-slave trigger according to claim 1, characterized in that: N1, N2, N3, N4, N5, N6, N7, P1, P2, P3, P4, P5, and INV constitute the master stage, and P6, P7, P8, P9, P10, P11, P12, N8, N9, N10, N11, and N12 constitute the slave stage.

3. The TFET-based single-edge-triggered master-slave trigger according to claim 2, characterized in that: The single-edge master-slave trigger works periodically, and the CLK state in each cycle includes a low level in the first stage and a high level in the second stage, and CLK performs rising single-edge triggering; If the current cycle CLK is in the first stage, the master stage transmits the data of the input signal D, and the slave stage stores the data transmitted by the master stage when CLK was in the second stage in the previous cycle; If the current cycle CLK is in the second phase, the master stage stores the data of the input signal D transmitted when the current cycle CLK is in the first phase, and the slave stage transmits the data transmitted from the master stage when CLK is in the first phase in the previous cycle.

4. The TFET-based single-edge-triggered master-slave trigger according to claim 3, characterized in that: The output node Q of the slave stage is initially pre-stored with "0" or "1".

5. The TFET-based single-edge-triggered master-slave trigger according to claim 3, characterized in that: If the current cycle CLK is in the first stage, the input signal D is high, and the middle node B is correspondingly high; then, the current cycle CLK is in the second stage, regardless of whether the input signal D is high or low, the middle node B is still high.

6. The TFET-based single-edge-triggered master-slave trigger according to claim 5, characterized in that: If the current cycle CLK is in the first stage, the output node Q stores the data transmitted from the master when CLK was in the second stage in the previous cycle; then, the current cycle CLK is in the second stage, the middle node B is high, and the output node Q is correspondingly high.

7. The TFET-based single-edge-triggered master-slave trigger according to claim 3, characterized in that: If the current cycle CLK is in the first stage, the input signal D is low, and the middle node B is correspondingly low; then, the current cycle CLK is in the second stage, regardless of whether the input signal D is high or low, the middle node B is still low.

8. The TFET-based single-edge-triggered master-slave trigger according to claim 7, characterized in that: If the current CLK is in the first stage, the output node Q stores the data transmitted from the master when the CLK was in the second stage in the previous cycle; then, the current CLK is in the second stage, the middle node B is low, and the output node Q is correspondingly low.

9. A trigger module, characterized in that: A circuit layout of a TFET-based single-edge-triggered master-slave trigger as described in any one of claims 1-8 is adopted.

10. The trigger module according to claim 9, characterized in that: The pins of the trigger module include: The first pin is connected to the gates of P2 and N2 and is used to transmit the input signal D; The second pin is connected to the gates of P1, P4, N4, P6, N8, P10, and N10 and is used to transmit a clock signal CLK; The third pin is connected to the source of P1, P3, P5, P6, P7, P9, P10, and P12 and is used to connect to the power supply VDD; A fourth pin is connected to the sources of N2, N4, N6, N9, N11, and N13 and is used for grounding GND; and The fifth pin is connected to the output node Q and is used to output data.

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