Clock offset correction circuit and method

Abstract

The present invention provides a clock offset correction circuit, which includes a variable delay unit, a clock offset detection unit, a filtering unit, a comparison unit, and a correction unit. The correction unit is connected to the comparison unit and the variable delay unit, and is used to output a correction polarity signal and a control signal according to a comparison result signal, and then perform time delay control on the variable delay unit through the correction polarity signal and the control signal to form a negative feedback adjustment, thereby reducing or eliminating clock offset. The present invention also provides a clock offset correction method.

Description

Technical Field

[0001] The present invention relates to the technical field of data recovery, and in particular to a clock skew correction circuit and method. Background Art

[0002] The function of clock data recovery (CDR) is to extract clock information from the edge transition information of data and find the optimal data sampling position. However, in traditional designs, there is a certain clock skew between the edge clock and the data clock, which causes the data to be sampled at non-optimal positions, increasing the symbol error rate (SER) of data transmission.

[0003] Figure 1 is the eye diagram of non-return-to-zero coding. Refer to Figure 1 , in the figure, CLK_EDGE is the edge clock generated by the CDR, and CLK_DATA is the data clock used for data sampling. In the front-end circuit of a receiver with a decision feedback equalizer (DFE), CLK_DATA is the clock of the data slicer in the DFE. Ideally, the rising edge spacing T BD between CLK_EDGE and CLK_DATA is 1 / 2 of the clock frequency to ensure that the data is sampled at the optimal position, that is, the eye height reaches the highest position. However, due to the asymmetry of the clock paths of CLK_EDGE and CLK_DATA and duty cycle distortion in the prior art, T BD deviates from the optimal value.

[0004] Figure 2 is a circuit diagram for generating an edge clock and a data clock in the prior art. Refer to Figure 2 , in the figure, CLK_SRC is the source clock, CLK_EDGE is the edge clock generated by the CDR, CLK_DATA is the data clock used for data sampling, C PE and C PD are the equivalent load capacitances on the clock lines, and I0, I1, I2, and I3 are inverters. It can be clearly seen from Figure 2 that there is circuit asymmetry between the two clock paths, that is, the CLK_DATA path has one more inverter than the CLK_EDGE path. Coupled with C PE and C PDThere may be differences, resulting in a clock skew greater than one inverter delay between CLK_EDGE and CLK_DATA. In the 28nm CMOS process, the typical delay of an inverter is more than 10ps, which is equivalent to 10% of one UI in a 10Gb / s transmission system. A 10% UI clock skew will cause a significant increase in SER due to the limited eye height of the eye diagram in the case of large channel attenuation, thus affecting the system performance.

[0005] Figure 3 is another circuit diagram for generating edge clock and data clock in the prior art. Referring to Figure 3 , in the figure, CLK_SRC is the source clock, CLK_EDGE is the edge clock generated by the CDR, CLK_DATA is the data clock used for data sampling, C PE and C PD are the equivalent load capacitances on the clock line, I4, I5, I6 and I7 are inverters, and I8 is a transmission gate. The transmission gate I8 is used to cancel the delay brought by CLK_EDGE on I7. Although this method reduces the clock skew to a certain extent, due to the asymmetry of the two clock paths, non-negligible clock skew will still occur under different process corners, voltages and temperatures.

[0006] Figure 4 is a clock schematic diagram of the prior art due to the duty cycle imbalance of the source clock. Referring to Figure 4 , it can be seen that the rising edge spacing T BD between CLK_EDGE and CLK_DATA is not 1 / 2 of the clock frequency T clk .

[0007] Therefore, it is necessary to provide a new clock skew correction circuit and method to solve the above problems existing in the prior art. SUMMARY OF THE INVENTION

[0008] The object of the present invention is to provide a clock skew correction circuit and method to reduce or eliminate clock skew.

[0009] To achieve the above object, the clock skew correction circuit of the present invention includes a variable delay unit, a clock skew detection unit, a filtering unit, a comparison unit and a correction unit;

[0010] The variable delay unit is used to receive a first clock signal and a second clock signal, adjust the delay of the first clock signal and the second clock signal, and output a first corrected clock signal and a second corrected clock signal;

[0011] The clock offset detection unit is connected to the variable delay unit and is used to detect the time delay between the first corrected clock signal and the second corrected clock signal, so as to output a first time delay detection signal and a second time delay detection signal;

[0012] The filtering unit is connected to the clock offset detection unit and is used to filter the first time delay detection signal and the second time delay detection signal to obtain a first DC signal and a second DC signal;

[0013] The comparison unit is connected to the filtering unit and is used to compare the first DC signal and the second DC signal to output a comparison result signal;

[0014] The correction unit is connected to the comparison unit and the variable delay unit and is used to output a correction polarity signal and a control signal according to the comparison result signal, and then perform time delay control on the variable delay unit through the correction polarity signal and the control signal.

[0015] The beneficial effect of the clock offset correction circuit is that the clock offset correction circuit includes a variable delay unit, a clock offset detection unit, a filtering unit, a comparison unit and a correction unit. The correction unit is connected to the comparison unit and the variable delay unit and is used to output a correction polarity signal and a control signal according to the comparison result signal, and then perform time delay control on the variable delay unit through the correction polarity signal and the control signal to form negative feedback regulation, thereby reducing or eliminating clock offset.

[0016] Optionally, the clock offset detection unit includes a negative resistance module, a third NMOS transistor and a fourth NMOS transistor. The negative resistance module is used for voltage regulation. The drain of the third NMOS transistor is connected to the negative resistance module and serves as the first output end of the clock offset detection unit for outputting the first time delay detection signal. The drain of the fourth NMOS transistor is connected to the negative resistance module and serves as the first output end of the clock offset detection unit for outputting the second time delay detection signal. The sources of the third NMOS transistor and the fourth NMOS transistor are grounded. The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the variable delay unit and respectively receive the first corrected clock signal and the second corrected clock signal.

[0017] Optionally, the negative resistance module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to a power supply voltage. The drain of the first PMOS transistor is connected to the drains of the first NMOS transistor, the third NMOS transistor, the gate of the second NMOS transistor, and the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the drains of the second NMOS transistor, the fourth NMOS transistor, the gate of the first NMOS transistor, and the gate of the first PMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are both grounded.

[0018] Optionally, the correction unit includes an initialization module for initializing the control signal.

[0019] Optionally, the comparison result signal includes an initial comparison result signal, and the correction unit further includes an assignment module for replacing the correction polarity signal with the initial comparison result signal.

[0020] Optionally, the comparison result signal further includes a subsequent comparison result signal, and the correction unit further includes a first determination module for determining whether the subsequent comparison result signal is the same as the correction polarity signal.

[0021] Optionally, the correction unit further includes an accumulation module for incrementing the control signal by 1 after the first determination module determines that the subsequent comparison result signal is the same as the correction polarity signal.

[0022] Optionally, the correction unit further includes a second determination module for determining whether the correction polarity signal is 0.

[0023] Optionally, the correction unit further includes a decrementation module for decrementing the control signal by 1 after the second determination module determines that the correction polarity signal is 0.

[0024] The present invention also provides a clock offset correction method for the clock offset correction circuit, including the following steps:

[0025] S1: Receiving a first clock signal and a second clock signal through the variable delay unit, and performing time delay control on the first clock signal and the second clock signal to output a first corrected clock signal and a second corrected clock signal;

[0026] S2: Detecting the time delay between the first corrected clock signal and the second corrected clock signal through the clock offset detection unit to output a first time delay detection signal and a second time delay detection signal;

[0027] S3: Filter the first delay detection signal and the second delay detection signal through the filtering unit to obtain a first DC signal and a second DC signal;

[0028] S4: Compare the first DC signal and the second DC signal through the comparison unit to output a comparison result signal;

[0029] S5: Output a correction polarity signal and a control signal through the correction unit according to the comparison result, and then perform delay control on the variable delay unit through the correction polarity signal and the control signal.

[0030] The beneficial effect of the clock offset correction method is that: the correction unit outputs a correction polarity signal and a control signal according to the comparison result, and then performs delay control on the variable delay unit through the correction polarity signal and the control signal to form a negative feedback regulation, thereby reducing or eliminating the clock offset.

[0031] Optionally, the comparison result signal includes an initial comparison result signal and a subsequent comparison result signal. The step of outputting a correction polarity signal and a control signal through the correction unit according to the comparison result includes the following steps:

[0032] S11: Initialize the control signal to 0;

[0033] S12: Replace the correction polarity signal with the initial comparison result signal;

[0034] S13: Determine whether the subsequent comparison result signal is the same as the correction polarity signal;

[0035] S14: If it is determined that the subsequent comparison result signal is the same as the correction polarity signal, increment the control signal by 1, and then execute S3; if it is determined that the subsequent comparison result signal is different from the correction polarity signal, output the control signal.

[0036] Optionally, the step of outputting a correction polarity signal and a control signal through the correction unit according to the comparison result includes:

[0037] S21: Initialize the control signal to 0;

[0038] S22: Replace the correction polarity signal with the initial comparison result signal;

[0039] S23: Determine whether the subsequent comparison result signal is the same as the correction polarity signal;

[0040] S24: If it is determined that the subsequent comparison result signal is the same as the correction polarity signal, increment the control signal by 1, and then execute S23; if it is determined that the subsequent comparison result signal is different from the correction polarity signal, execute S25;

[0041] S25: Determine whether the control signal is 0;

[0042] S26: If the control signal is 0, execute S22; if the control signal is not 0, decrement the control signal by 1, and then execute S23. Description of the Drawings

[0043] Figure 1 is a non-return-to-zero encoded eye diagram;

[0044] Figure 2 is a circuit diagram for generating an edge clock and a data clock in the prior art;

[0045] Figure 3 is another circuit diagram for generating an edge clock and a data clock in the prior art;

[0046] Figure 4 is a clock schematic diagram of the source clock duty cycle mismatch in the prior art;

[0047] Figure 5 is a block diagram of a clock offset correction circuit in some embodiments of the present invention;

[0048] Figure 6 is a circuit diagram of a clock offset detection unit in some embodiments of the present invention;

[0049] Figure 7 is a timing diagram of a clock offset detection unit in some embodiments of the present invention;

[0050] Figure 8 is a flowchart of a clock offset correction method in some embodiments of the present invention;

[0051] Figure 9 is a flowchart of a single correction in some embodiments of the present invention;

[0052] Figure 10 is a flowchart of multiple corrections in some embodiments of the present invention. Detailed Description of the Invention

[0053] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein are intended to mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0054] In view of the problems existing in the prior art, an embodiment of the present invention provides a clock offset correction circuit, which is applied to a CDR and a DFE. Referring to Figure 5 , the clock offset correction circuit includes a variable delay unit, a clock offset detection unit, a filtering unit, a comparison unit and a correction unit. The clock offset detection unit is connected to the variable delay unit, the filtering unit is connected to the clock offset detection unit, the comparison unit is connected to the filtering unit, and the correction unit is connected to the comparison unit and the variable delay unit.

[0055] Referring to Figure 5 , the variable delay unit is configured to receive a first clock signal CLK_EDGE_PRE and a second clock signal CLK_DATA_PRE, adjust the time delays of the first clock signal CLK_EDGE_PRE and the second clock signal CLK_DATA_PRE, and output a first corrected clock signal and a second corrected clock signal; the clock offset detection unit is configured to detect the time delay between the first corrected clock signal and the second corrected clock signal, and output a first time delay detection signal and a second time delay detection signal; the filtering unit is configured to filter the first time delay detection signal and the second time delay detection signal to obtain a first DC signal and a second DC signal, wherein the first DC signal and the second DC signal can indicate the offset direction and offset amount of the clock; the comparison unit is configured to compare the first DC signal and the second DC signal and output a comparison result signal; the correction unit is configured to output a correction polarity signal POL and a control signal CTRL according to the comparison result signal, and then perform time delay control on the variable delay unit through the correction polarity signal POL and the control signal CTRL. Wherein, CLK_EDGE_POST is the signal finally corrected from the first clock signal CLK_EDGE_PRE, and CLK_DATA_POST is the signal finally corrected from the second clock signal CLK_DATA_PRE.

[0056] In some specific embodiments, the variable delay unit includes a variable delay line (VDL), the filtering unit includes a low pass filter (LPF), and the comparison unit includes a low offset comparator (LOC).

[0057] Figure 6 It is a circuit diagram of a clock offset detection unit in some embodiments of the present invention. Refer to Figure 6 , the clock offset detection unit includes a negative resistance module, a third NMOS transistor MN3, and a fourth NMOS transistor MN4. The negative resistance module is used for voltage regulation. The drain of the third NMOS transistor MN3 is connected to the negative resistance module, serving as the first output terminal of the clock offset detection unit for outputting the first delay detection signal OUT1. The drain of the fourth NMOS transistor MN4 is connected to the negative resistance module, serving as the first output terminal of the clock offset detection unit for outputting the second delay detection signal OUT2. The sources of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are grounded. The gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are both connected to the variable delay unit, respectively receiving the first corrected clock signal CK1 and the second corrected clock signal CK2.

[0058] Refer to Figure 6 , the negative resistance module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply voltage. The drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, the drain of the third NMOS transistor MN3, the gate of the second NMOS transistor MN2, and the gate of the second PMOS transistor MP2. The drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, the drain of the fourth NMOS transistor MN4, the gate of the first NMOS transistor MN1, and the gate of the first PMOS transistor MP1. The sources of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both grounded.

[0059] Figure 7 It is a timing diagram of a clock offset detection unit in some embodiments of the present invention. Refer to Figure 6 and Figure 7, the first delay detection signal OUT1 is reset to a low potential at the rising edge of the first calibration clock signal CK1 and reset to a high potential at the rising edge of the second calibration clock signal CK2; the second delay detection signal OUT2 is reset to a low potential at the rising edge of the second calibration clock signal CK2 and reset to a high potential at the rising edge of the first calibration clock signal CK1. The high potential maintenance time of the second delay detection signal OUT2 is exactly the time interval between the first calibration clock signal CK1 and the second calibration clock signal CK2. Since the first calibration clock signal CK1 and the second calibration clock signal CK2 are derived from the same clock, the clock frequencies of the first delay detection signal OUT1 and the second delay detection signal OUT2 must be the same as those of the first calibration clock signal CK1 and the second calibration clock signal CK2. Therefore, as long as the duty cycles of the first delay detection signal OUT1 and the second delay detection signal OUT2 are 50%, the rising edge spacing T of the first calibration clock signal CK1 and the second calibration clock signal CK2 can be made BD 1 / 2 of the clock frequency, so as to achieve the purpose of calibration.

[0060] In some embodiments, the calibration unit includes an initialization module, an assignment module, a subsequent comparison result signal, and an accumulation module. Among them, the comparison result signal is a continuous signal, the comparison result signal includes an initial comparison result signal and a subsequent comparison result signal, the initialization module is used to initialize the control signal; the assignment module is used to replace the calibration polarity signal with the initial comparison result signal; the first judgment module is used to judge whether the subsequent comparison result signal is the same as the calibration polarity signal; the accumulation module is used to add 1 to the control signal after the first judgment module judges that the subsequent comparison result signal is the same as the calibration polarity signal. The initialization module is also used to initialize the calibration polarity signal.

[0061] In some other embodiments, the correction unit includes an initialization module, an assignment module, a subsequent comparison result signal, an accumulation module, a second determination module, and a subtraction module. Among them, the comparison result signal is a continuous signal, and the comparison result signal includes an initial comparison result signal and a subsequent comparison result signal. The initialization module is used to initialize the control signal; the assignment module is used to replace the correction polarity signal with the initial comparison result signal; the first determination module is used to determine whether the subsequent comparison result signal is the same as the correction polarity signal; the accumulation module is used to add 1 to the control signal after the first determination module determines that the subsequent comparison result signal is the same as the correction polarity signal; the second determination module is used to determine whether the correction polarity signal is 0; the subtraction module is used to subtract 1 from the control signal after the second determination module determines that the correction polarity signal is 0. The initialization module is also used to initialize the correction polarity signal.

[0062] Figure 8 It is a flowchart of the clock offset correction method in some embodiments of the present invention. Refer to Figure 8 , the clock offset correction method is applied to the clock offset correction circuit, and the clock offset correction method includes the following steps:

[0063] S1: Receive a first clock signal and a second clock signal through the variable delay unit, and perform delay control on the first clock signal and the second clock signal to output a first corrected clock signal and a second corrected clock signal;

[0064] S2: Detect the delay between the first corrected clock signal and the second corrected clock signal through the clock offset detection unit to output a first delay detection signal and a second delay detection signal;

[0065] S3: Filter the first delay detection signal and the second delay detection signal through the filtering unit to obtain a first DC signal and a second DC signal;

[0066] S4: Compare the first DC signal and the second DC signal through the comparison unit to output a comparison result signal;

[0067] S5: Output a correction polarity signal and a control signal according to the comparison result through the correction unit, and then perform delay control on the variable delay unit through the correction polarity signal and the control signal.

[0068] Figure 9 It is a flowchart of single - time correction in some embodiments of the present invention. Refer to Figure 9 , the outputting a correction polarity signal and a control signal according to the comparison result through the correction unit includes the following steps:

[0069] S11: Initialize the control signal to 0;

[0070] S12: Replace the correction polarity signal with the initial comparison result signal;

[0071] S13: Determine whether the subsequent comparison result signal is the same as the correction polarity signal;

[0072] S14: If it is determined that the subsequent comparison result signal is the same as the correction polarity signal, increment the control signal by 1, and then execute S3; if it is determined that the subsequent comparison result signal is different from the correction polarity signal, output the control signal. <s

[0073] In some embodiments, when performing step S11, it further includes initializing the correction polarity signal to 0.

[0074] Figure 10 This is a flowchart of multiple corrections in some embodiments of the present invention. Refer to Figure 10 , the correction unit outputs a correction polarity signal and a control signal according to the comparison result, including:

[0075] S21: Initialize the control signal to 0;

[0076] S22: Replace the correction polarity signal with the initial comparison result signal;

[0077] S23: Determine whether the subsequent comparison result signal is the same as the correction polarity signal;

[0078] S24: If it is determined that the subsequent comparison result signal is the same as the correction polarity signal, increment the control signal by 1, and then execute S23; if it is determined that the subsequent comparison result signal is different from the correction polarity signal, execute S25;

[0079] S25: Determine whether the control signal is 0;

[0080] S26: If the control signal is 0, execute S22; if the control signal is not 0, decrement the control signal by 1, and then execute S23.

[0081] In some embodiments, when performing step S21, it further includes initializing the correction polarity signal to 0.

[0082] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are all within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A clock offset correction circuit, characterized in that, It includes a variable delay unit, a clock offset detection unit, a filtering unit, a comparison unit, and a correction unit; The variable delay unit is used to receive a first clock signal and a second clock signal, perform time delay adjustment on the first clock signal and the second clock signal, and output a first corrected clock signal and a second corrected clock signal; The clock offset detection unit is connected to the variable delay unit and is used to detect the time delay between the first corrected clock signal and the second corrected clock signal, and output a first time delay detection signal and a second time delay detection signal; The filtering unit is connected to the clock offset detection unit and is used to filter the first time delay detection signal and the second time delay detection signal to obtain a first DC signal and a second DC signal; The comparison unit is connected to the filtering unit and is used to compare the first DC signal and the second DC signal to output a comparison result signal; The correction unit is connected to the comparison unit and the variable delay unit, and is used to output a correction polarity signal and a control signal according to the comparison result signal, and then perform time delay control on the variable delay unit through the correction polarity signal and the control signal.

2. The clock offset correction circuit according to claim 1, wherein The clock offset detection unit includes a negative resistance module, a third NMOS transistor, and a fourth NMOS transistor. The negative resistance module is used for voltage regulation. The drain of the third NMOS transistor is connected to the negative resistance module and serves as the first output terminal of the clock offset detection unit for outputting the first time delay detection signal. The drain of the fourth NMOS transistor is connected to the negative resistance module and serves as the first output terminal of the clock offset detection unit for outputting the second time delay detection signal. The sources of the third NMOS transistor and the fourth NMOS transistor are grounded. The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the variable delay unit and respectively receive the first corrected clock signal and the second corrected clock signal.

3. The clock offset correction circuit according to claim 2, wherein, The negative resistance module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply voltage. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the third NMOS transistor, the gate of the second NMOS transistor, and the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the fourth NMOS transistor, the gate of the first NMOS transistor, and the gate of the first PMOS transistor. The sources of the first NMOS transistor and the second NMOS transistor are both grounded.

4. The clock offset correction circuit according to claim 1, characterized in that, The correction unit includes an initialization module for initializing the control signal.

5. The clock offset correction circuit according to claim 4, characterized in that, The comparison result signal includes an initial comparison result signal. The correction unit further includes an assignment module for replacing the correction polarity signal with the initial comparison result signal.

6. The clock offset correction circuit according to claim 5, characterized in that The comparison result signal further includes a subsequent comparison result signal, and the correction unit further includes a first determination module for determining whether the subsequent comparison result signal is the same as the correction polarity signal.

7. The clock offset correction circuit according to claim 6, wherein The correction unit further includes an accumulation module for adding 1 to the control signal after the first determination module determines that the subsequent comparison result signal is the same as the correction polarity signal.

8. The clock offset correction circuit according to claim 6, wherein The correction unit further includes a second determination module for determining whether the correction polarity signal is 0.

9. The clock offset correction circuit according to claim 8, wherein The correction unit further includes a subtraction module for subtracting 1 from the control signal after the second determination module determines that the correction polarity signal is 0.

10. A clock offset correction method applying the clock offset correction circuit according to any one of claims 1 to 9, characterized in that, It includes the following steps: S1: Receive a first clock signal and a second clock signal through the variable delay unit, perform delay control on the first clock signal and the second clock signal to output a first corrected clock signal and a second corrected clock signal; S2: Detect the delay between the first corrected clock signal and the second corrected clock signal through the clock offset detection unit to output a first delay detection signal and a second delay detection signal; S3: Filter the first delay detection signal and the second delay detection signal through the filtering unit to obtain a first DC signal and a second DC signal; S4: Compare the first DC signal and the second DC signal through the comparison unit to output a comparison result signal; S5: Output a correction polarity signal and a control signal according to the comparison result through the correction unit, and then perform delay control on the variable delay unit through the correction polarity signal and the control signal.

11. The clock offset correction method according to claim 10, characterized in that, The comparison result signal includes an initial comparison result signal and a subsequent comparison result signal. The step of outputting a correction polarity signal and a control signal according to the comparison result through the correction unit includes the following steps: S11: Initialize the control signal to 0; S12: Replace the correction polarity signal with the initial comparison result signal; S13: Determine whether the subsequent comparison result signal is the same as the correction polarity signal; S14: If it is determined that the subsequent comparison result signal is the same as the correction polarity signal, add 1 to the control signal, and then execute S3; if it is determined that the subsequent comparison result signal is different from the correction polarity signal, output the control signal.

12. The clock offset correction method according to claim 11, wherein The step of outputting a correction polarity signal and a control signal according to the comparison result through the correction unit includes: S21: Initialize the control signal to 0; S22: Replace the correction polarity signal with the initial comparison result signal; S23: Determine whether the subsequent comparison result signal is the same as the correction polarity signal; S24: If it is determined that the subsequent comparison result signal is the same as the correction polarity signal, add 1 to the control signal, and then execute S23; if it is determined that the subsequent comparison result signal is different from the correction polarity signal, execute S25; S25: Determine whether the control signal is 0; S26: If the control signal is 0, execute S22; if the control signal is not 0, subtract 1 from the control signal, and then execute S23.

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