Detection circuit and power management system including the detection circuit

Abstract

The present invention discloses a detection circuit and a power management system including the detection circuit. The detection circuit also includes: a threshold voltage generation circuit for generating a threshold voltage; a voltage-current conversion circuit for converting an offset voltage of a signal to be detected relative to the threshold voltage into a proportional current; and a current-type successive approximation quantizer for obtaining a comparison result between the signal to be detected and the threshold voltage or a windowed quantization result of the signal to be detected based on the proportional current quantization, and the circuit structure is simpler and the cost is lower.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and more particularly to a detection circuit and a power management system including the detection circuit. Background Art

[0002] In systems with complex power supply requirements, multiple DC / DC converters are usually used to generate the power supply requirements of different semiconductor devices. An obvious result is that controlling and monitoring these power supplies will become more complicated during product design, production testing and daily use.

[0003] At present, many high-performance DC / DC converters are still controlled by analog signals generated by passive components. Even with the most advanced power circuit topology, external potentiometers and capacitors have to be used to adjust parameters such as start-up time, output voltage value and switching frequency, and these parameters cannot be changed at any time.

[0004] The PMBus (Power Management Bus) open standard specification defines a digital communication protocol for controlling power conversion and management devices, which can realize the communication between the converter and other devices by defining the transmission and physical interface and command language. Existing DC / DC converters, such as IR35201 and PXE1610, integrate a large number of different types of ADCs (Analog to Digital Converters) and DACs (Digital to Analog Converters) to realize the function of monitoring multiple parameters. It is necessary to integrate a large number of devices in the circuit, which greatly increases the chip area and cost. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a detection circuit with a simple structure and a power management system including the detection circuit. The detection circuit takes demand-oriented optimization as a starting point and completes the monitoring and setting needs of all parameters with a single structure, which greatly reduces the area and cost of the circuit.

[0006] According to one aspect of an embodiment of the present invention, a detection circuit is provided, comprising: a threshold voltage generating circuit for generating a threshold voltage; a voltage-current conversion circuit for converting an offset voltage of a signal to be detected relative to the threshold voltage into a proportional current; and a current-type successive approximation quantizer for obtaining a detection result based on the proportional current quantization.

[0007] Optionally, the detection result is a comparison result between the signal to be detected and the threshold voltage or a quantization result of a portion of the signal to be detected that enters a window defined by the threshold voltage.

[0008] Optionally, the detection circuit further includes: a differential sampling switch configured to provide an offset voltage or a reference ground voltage to the voltage-current conversion circuit.

[0009] Optionally, the voltage-to-current conversion circuit includes: a storage capacitor, a first end of which is used to couple with the output end of the threshold generating circuit and the input end of the signal to be detected; a first transistor, a control end of which is used to couple with the second end of the storage capacitor; a first resistor, a first end of which is used to couple with the second end of the first transistor, and a second end of which is used to couple with the offset voltage or the reference ground voltage via the differential sampling switch; and a second transistor, a control end of which is used to receive a bias voltage, a second end of which is used to couple with the first end of the first transistor, and a first end of which is used to output the proportional current.

[0010] Optionally, the current-type successive approximation quantizer includes: an operational amplifier, a first input terminal coupled to the first terminal of the second transistor, and a second input terminal coupled to a clamping voltage; a current source array, used to generate a reference current based on the clamping voltage and provide it to the first input terminal of the operational amplifier; and a comparator, coupled to the output terminal of the operational amplifier, for quantizing the output of the operational amplifier into the comparison result.

[0011] Optionally, when the detection result is a comparison result between the signal to be detected and the threshold voltage, the reference current provided by the current source array is a fixed current value.

[0012] Optionally, when the detection result is a quantization result of the signal to be detected within the window defined by the threshold voltage, the reference current provided by the current source array is a variable current value, and the quantization result is obtained by adjusting the current value of the reference current.

[0013] Optionally, the current-type successive approximation quantizer further includes: a SAR logic circuit, configured to control the switching of the current source array according to the comparison result, and adjust the current value of the reference current in a successive approximation manner until the quantization is completed.

[0014] Optionally, the detection circuit also includes: a first switch configured to couple the first end of the storage capacitor to the output end of the threshold voltage generating circuit during the threshold establishment phase; and a second switch configured to couple the first end of the storage capacitor to the input end of the signal to be detected during the detection phase.

[0015] Optionally, the detection circuit further includes: a third switch configured to ground the first end of the storage capacitor in the first sub-stage of the threshold establishment stage to achieve charge resetting.

[0016] Optionally, the threshold establishing phase further includes a second sub-phase after the first sub-phase, and the threshold voltage generating circuit is configured to generate the threshold voltage in the second sub-phase.

[0017] Optionally, the voltage-current conversion circuit further includes: a fourth switch configured to couple the control terminal and the first terminal of the first transistor during the threshold establishment phase.

[0018] Optionally, the detection circuit includes multiple input terminals, and the detection circuit is configured to detect the signals to be detected at the multiple input terminals in a time-sharing manner.

[0019] Optionally, the detection circuit further includes a register array for storing a plurality of control codes corresponding to the signals to be detected at the plurality of input terminals, and the threshold voltage generating circuit generates a corresponding threshold voltage based on the control codes provided by the register array.

[0020] Optionally, the threshold voltage generating circuit is a capacitive digital-to-analog converter.

[0021] According to another aspect of an embodiment of the present invention, a power management system is provided, comprising the above-mentioned detection circuit.

[0022] To summarize, the detection circuit of the present invention adopts a capacitive DAC to generate a window lower limit voltage, converts the offset voltage of the signal to be detected relative to the lower limit voltage into a current through a voltage-current conversion circuit, and then uses a current-type successive approximation quantizer to quantize the current, and finally obtains a comparison result between the signal to be detected and the lower limit voltage or a quantization result of the signal to be detected in the window, and the circuit structure is simpler, thereby greatly reducing the area of ​​the power management system using the detection circuit and reducing the circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0024] Figure 1 A schematic diagram showing the structure of a detection circuit according to a first embodiment of the present invention is shown;

[0025] Figure 2 Shows Figure 1 A circuit diagram of the current source array 131 in FIG.

[0026] Figure 3 A timing diagram of a detection circuit according to a first embodiment of the present invention is shown;

[0027] Figure 4 A schematic diagram showing the structure of a detection circuit according to a second embodiment of the present invention is shown;

[0028] Figure 5 A schematic diagram showing the structure of a detection circuit according to a third embodiment of the present invention is shown;

[0029] Figure 6 FIG. 4 is a timing diagram of a detection circuit according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0031] Many specific details of the present invention are described below, such as component structures, materials, dimensions, processing techniques and technologies, in order to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0032] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits and / or elements that can store instructions executed by programmable circuits. When an element or circuit is said to be "connected to" or "coupled to" another element, or an element / circuit is said to be "connected to" or "coupled between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element between the two, and the connection or coupling between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0033] Figure 1 FIG. 2 shows a schematic diagram of the structure of the detection circuit of the first embodiment of the present invention. Figure 1 As shown, the detection circuit 100 includes a threshold voltage generating circuit 110, a voltage-current conversion circuit 120, a current-type successive approximation register quantizer (SAR ADC) 130, and switches S1 to S5. The threshold voltage generating circuit 120 is used to generate a threshold voltage Vb, the voltage-current conversion circuit 120 converts the offset voltage of the signal to be detected Vx relative to the threshold voltage Vb into a proportional current Ir by using a time-sharing subtraction method, and the current-type successive approximation register quantizer 130 is used to receive the proportional current Ir and quantize the proportional current Ir to obtain a detection result, wherein the detection result is characterized as a comparison result between the signal to be detected Vx and the threshold voltage Vb.

[0034] The voltage-current conversion circuit 120 includes a storage capacitor CH, transistors Q1 and Q2, and a resistor R1. The first end of the storage capacitor CH is coupled to the threshold voltage generation circuit 110 via a switch S1, and is coupled to the input end of the signal to be detected Vx via a switch S2, and the second end of the storage capacitor CH is coupled to the control end of the transistor Q1. The switch S4 is coupled between the control end and the first end of the transistor Q1, the second end of the transistor Q1 is coupled to the first end of the resistor R1, and the second end of the resistor R1 is coupled to the offset voltage Vos or the ground via a switch S5. The control end of the transistor Q2 is used to receive a bias voltage Vbias, the second end of the transistor Q2 is coupled to the first end of the transistor Q1, and the first end is used to output the proportional current Ir.

[0035] Among them, switches S1 and S2 are turned on in sequence to provide the threshold voltage Vb and the signal to be detected Vx to the first end of the storage capacitor CH respectively, and the threshold voltage Vb and the offset voltage of the signal to be detected Vx are stored in the capacitor CH. Transistor Q1 and resistor R1 are used to convert the offset voltage on the storage capacitor CH into a current signal, and output it through transistor Q2. Among them, the cascade structure of transistors Q2 and Q1 is used to increase the source impedance of the current signal Ir, and the selection of the bias voltage Vbias needs to ensure that the transistor Q2 still works in a linear state when the current signal Ir is at the maximum design value. It should be noted that transistor Q2 is mainly used to improve the performance of the voltage-current conversion circuit 120. In some other embodiments, transistor Q2 can also be removed, and the embodiments of the present invention are not limited to this.

[0036] In addition, the first end of the storage capacitor CH is also used to be coupled to the ground via the switch S3. The switch S3 is used to connect the storage capacitor CH to the ground to reset the charge on the capacitor.

[0037] In this embodiment, the transistors Q1 and Q2 are, for example, NMOS transistors, and the first terminal, the second terminal and the control terminal thereof are respectively the drain, the source and the gate of the NMOS transistor.

[0038] The current-type successive approximation quantizer 130 includes a current source array (also called a weighted current array or a current steering DAC) 131, an operational amplifier AMP1, and a comparator COMP. The current source array 131 is used to generate a reference current Ic. The operational amplifier AMP1 has two input terminals and one output terminal, wherein the first input terminal is coupled to the first terminal of the transistor Q2 and the output terminal of the current source array 131, the second input terminal is coupled to the clamping voltage Vforce, and the output terminal is coupled to the input terminal of the comparator COMP. The comparator COMP is used to quantize the output of the operational amplifier AMP1 into the comparison result. The operational amplifier AMP1 uses the reference current Ic output by the current source array 131 as a load (the transistor Q2 is a current sink, and the current source array 131 is a current source, and the two are mutually loaded at the first input terminal of the operational amplifier AMP1), amplifies and outputs the voltage difference between the junction point of the proportional current Ir and the reference current Ic and the clamping voltage Vforce, and the comparator COMP outputs the final comparison result "0" or "1" based on the voltage difference amplified by the operational amplifier AMP1.

[0039] Further, such as Figure 2 As shown, the current source array 131 of this embodiment includes an operational amplifier AMP2, a resistor R2, transistors Q3 and Q4, and a plurality of switch branches S31 to S3n. Among them, the transistor Q3 and the resistor R2 are coupled between the power supply terminal Vcs and the ground. The operational amplifier AMP2 has two input terminals and one output terminal, wherein the first input terminal is coupled to the first terminal of the resistor R2, the second input terminal is coupled to the clamping voltage Vforce, and the output terminal is coupled to the control terminal of the transistor Q3. When the operational amplifier AMP2 works in a negative feedback loop, a current Iref=Vforce / R2 is obtained in the transistor Q3. The transistor Q4 and the transistor Q3 form a current mirror for mirroring the current Iref to the switch branches S31 to S3n. The first terminal of the transistor Q4 is coupled to the power supply terminal Vcs, the second terminal is coupled to a common terminal of the switch branches S31 to S3n, and the control terminal is coupled to the control terminal of the transistor Q3. The switch branches S31-S3n are, for example, binary-weighted current source arrays composed of MOS tubes with binary-weighted width-to-length ratios. The required reference current Ic can be obtained at the other common end thereof by switching the switch branches S31-S3n. In the present embodiment, the reference current Ic is a fixed current value, and the selection of the current value is mainly set according to the detection environment. For example, when in a fast and high-precision comparison environment, the current value of the reference current Ic is relatively large; when in a power-saving comparison environment, the current value of the reference current Ic is relatively small.

[0040] In this embodiment, the transistors Q3 and Q4 are, for example, PMOS transistors, and the first terminal, the second terminal and the control terminal thereof are the source, the drain and the gate of the PMOS transistors, respectively.

[0041] Continue to refer Figure 1 In some embodiments, the threshold voltage generating circuit 110 may be implemented by a capacitive DAC (digital-to-analog converter), which may include a plurality of weighted capacitors, such as binary weighted capacitors 2 N C···C and multiple switches, by controlling the switching of multiple switches in the capacitive DAC, a threshold voltage Vb corresponding to the signal to be detected Vx is generated. In other embodiments, the detection circuit 100 may also include a register array 140, and the register array 140 is used to store a binary control code corresponding to the signal to be detected Vx, and the binary control code controls the switching of switches in the capacitive DAC110 to generate a corresponding threshold voltage. It can be understood that the circuit structure of the capacitive DAC and the circuit principle of converting the binary control code into the corresponding analog voltage are conventional technologies in the art and will not be repeated here.

[0042] Figure 3 FIG. 1 shows a timing diagram of the detection circuit of the first embodiment of the present invention. Figure 3 in,signal Used to control the on and off of switches S1 and S4, signal Used to control the on and off of switch S3, signal The detection circuit of this embodiment is operated on the signal The threshold buildup phase and signal at high level The detection phase when the signal is at a high level. The threshold detection phase further includes the signal The first sub-stage and signal of high level The second sub-stage is high level. Figure 3 The working principle of the detection circuit of this embodiment is further explained.

[0043] First, the signal is flipped to a high level, switches S1 and S4 are turned on, switch S1 couples the first end of storage capacitor CH to the output end of capacitive DAC110, and switch S4 couples the control end and the first end of transistor Q1. is flipped to a high level, the switch S3 is turned on, and the first end of the storage capacitor CH is grounded to reset the charge in the capacitor. When it turns low, the signal When the voltage is flipped to a high level, the capacitive DAC 110 switches according to the control code provided by the register array 140 , outputs the threshold voltage Vb, and stores it on the storage capacitor CH.

[0044] Afterwards, the signal Flip to a high level, switch S2 is turned on, switch S2 couples the first end of the storage capacitor CH to the input end of the signal to be detected Vx, and the signal to be detected Vx is provided to the storage capacitor CH. Since the threshold voltage Vb has been stored on the storage capacitor CH, the offset voltage of the signal to be detected Vx relative to the threshold voltage Vb is converted into a proportional current through the transistor Q1 and the resistor R1, and the comparison result is output based on the proportional current quantization output by the subsequent current-type successive approximation quantizer 130. Furthermore, when further differentiation is required in addition to windowing when acquiring the signal to be detected Vx, for example, when collecting the working voltage of the load point, it is necessary to immediately deduct the voltage drop of the return path, which can be done during the detection stage. The corresponding offset voltage Vos is connected to the voltage-current conversion circuit 120 through the differential sampling switch S5.

[0045] Furthermore, Figure 3 Also included is the signal Previous delayed signal Delayed signal Used to prevent switch shoot-through in a circuit.

[0046] Figure 4 The schematic diagram of the structure of the detection circuit of the second embodiment of the present invention is shown. The difference between the detection circuit 200 of this embodiment and the detection circuit 100 of the first embodiment is that the output detection result is the quantization result of the part of the signal Vx to be detected that enters the window defined by the threshold voltage Vb, that is, the digital result of the part of the signal Vx to be detected that is within the window. In this embodiment, the reference current Ic provided by the current source array 131 is a variable current value, and the current value of the reference current Ic is adjusted by successive approximation to finally obtain the quantization result.

[0047] Furthermore, compared with the detection circuit 100 of the first embodiment, the detection circuit 200 of the present embodiment has a current-type successive approximation quantizer 130 further including a SAR logic circuit 132, which is used to control the SAR (successive approximation) conversion in the current source array 131 according to the comparison results "0" and "1" output by the comparator COMP, and continuously generate each bit output of the SAR ADC from high to low in a successive approximation manner until the entire quantization is completed, and finally obtain the digital result of the signal to be detected Vx within the window. It can be understood that the principle of the SAR logic circuit 132 controlling the SAR conversion in the current source array 131 according to the output of the comparator COMP is a conventional technology in the art and will not be repeated here.

[0048] It should be noted that the detection circuit 200 of this embodiment can also be used Figure 3 The timing diagram in the embodiment is controlled, and the difference between the detection circuit 100 and the first embodiment is only that the signal In the detection phase when the signal is high When at a high level, the signal to be detected Vx is also provided to the storage capacitor CH, and then the offset voltage of the signal to be detected Vx relative to the threshold voltage Vb is converted into a proportional current through the transistor Q1 and the resistor R1, and the comparison result is output through the comparator AMP1 and the amplifier COMP with the current source array 131 as the load. After that, the detection circuit 200 of this embodiment further includes controlling the current source array 131 to perform SAR conversion according to the comparison result through the SAR logic circuit 132, and finally obtaining the quantization result of the signal to be detected Vx.

[0049] It should be noted that the detection circuit 200 of this embodiment, as a further improved solution of the detection circuit 100, can have both the functions of threshold comparison and signal quantization. When used for threshold comparison, it is only necessary to disconnect the SAR logic circuit 132 so that the current source array 131 outputs a reference current Ic with a fixed current value. When used for signal quantization, it is only necessary to connect the SAR logic circuit 132 to the circuit again. Finally, the two functions of threshold comparison and quantization are realized in one circuit, which can greatly reduce the scale and cost of the circuit.

[0050] Figure 5 and Figure 6 The schematic diagrams respectively show the structure of the detection circuit of the third embodiment of the present invention.

[0051] The detection circuit 300 of this embodiment is different from the detection circuit 200 of the second embodiment.

[0052] The difference is that the detection circuit 300 includes multiple input terminals and multiple switches S21-S2n. The detection circuit 300 detects the detection signals Vx1-Vxn of the multiple input terminals in a certain rhythm and performs threshold comparison or quantization operations on the input detection signals according to specific requirements. Figure 6 As shown, the timing signal CLK includes the first time slot to the nth time slot, and the detection circuit 300 is configured to detect the signal to be detected of the corresponding input port in each time slot. Further, the operation of the detection circuit 300 in each time slot also includes the signal The threshold for the high level establishes the phase and signal The detection phase is high level, and the threshold establishment phase also includes the signal The first sub-stage and signal of high level The second sub-stage is high level.

[0053] Furthermore, the register array 140 of the detection circuit 300 of this embodiment also stores a plurality of binary control codes, which correspond one-to-one to the signals to be detected at a plurality of input terminals, and the capacitive DAC 110 is configured to generate a threshold voltage Vb corresponding to the currently input signal to be detected based on the binary control code provided by the register array 140 during the threshold establishment phase.

[0054] Take the signal Vx1 to be detected as an example. When the detection circuit 300 is at a high level, the detection circuit 300 is in the threshold establishment stage, the switch S1 couples the first end of the storage capacitor CH to the output end of the capacitive DAC 110, and the switch S4 couples the first end of the transistor Q1 to the control end. At a high level, the storage capacitor CH discharges to ground to reset the charge on the capacitor. When it turns low, the signal Flipped to high level, the capacitive DAC 110 generates a threshold voltage Vb corresponding to the signal to be detected Vx1 according to the binary control code provided by the register array 140. After turning to low level, after a dead time Signal Flipped to high level, the detection circuit 300 enters the detection phase, the switch S21 is turned on, the signal to be detected Vx1 is coupled to the storage capacitor CH, and at the same time, a comparator or current-type SAR conversion is established in the subsequent circuit according to the specific requirements of the signal to be detected Vx1, and the comparison result of the signal to be detected Vx1 and the threshold voltage Vb or the quantization result of the signal to be detected Vx1 within the window defined by the threshold voltage Vb is output. Similarly, if the signal to be detected Vx1 needs to be differentiated in addition to the windowing, it can be used in the detection phase. A certain offset voltage Vos is provided to the voltage-current conversion circuit 120 through the differential sampling switch S5.

[0055] In some other embodiments, the present invention also provides a power management system, which includes the above-mentioned detection circuit, which is connected to the power supply unit through a power management bus (PMBus) interface to read various parameters of the power supply unit, such as input voltage, output voltage or output voltage offset, and perform threshold comparison and quantification on these parameters, thereby completing the monitoring and setting requirements of all parameters with a single circuit structure, greatly reducing the circuit cost of power management.

[0056] To summarize, the detection circuit of the present invention adopts a capacitive DAC to generate a window lower limit voltage, converts the offset voltage of the signal to be detected relative to the lower limit voltage into a current through a voltage-current conversion circuit, and then uses a current-type successive approximation quantizer to quantize the current, and finally obtains a comparison result between the signal to be detected and the lower limit voltage or a quantization result of the signal to be detected in the window, and the circuit structure is simpler, thereby greatly reducing the area of ​​the power management system using the detection circuit and reducing the circuit cost.

[0057] In a further embodiment, the detection circuit reuses the current source array in the current-type successive approximation quantizer as a load to perform threshold comparison or quantize proportional current, which is beneficial to saving circuit elements and further reducing circuit area.

[0058] In a further embodiment, the detection circuit uses a combination of a capacitive DAC and a current SAR ADC to perform window quantization on the parameters. Since the quantization range of the current SAR ADC covers different quantization bits of the capacitive DAC, multiple quantizations can be performed for the same parameter through different combinations of DAC bits and ADC bits, so that multiple quantizations can be averaged to reduce the quantization error and improve the quantization accuracy.

[0059] It will be understood by those skilled in the art that the words "during", "when" and "when..." used in this article in connection with the operation of the circuit are not strict terms indicating an action that occurs immediately when the start-up action begins, but that there may be some small but reasonable delay or delays between it and the reaction action initiated by the start-up action, such as various transmission delays, etc. The words "approximately" or "substantially" used in this article mean that the element value has a parameter that is expected to be close to the declared value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (for semiconductor doping concentrations, at least twenty percent (20%)) is a reasonable deviation from the accurate ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0060] In addition, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0061] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A detection circuit, comprising: A threshold voltage generating circuit, used for generating a threshold voltage; A voltage-current conversion circuit, used for converting an offset voltage of a signal to be detected relative to the threshold voltage into a proportional current; as well as A current-type successive approximation quantizer is used to obtain a detection result based on the proportional current quantization, Wherein, the current-mode successive approximation quantizer comprises: An operational amplifier having a first input terminal coupled to the proportional current and a second input terminal coupled to a clamping voltage; a current source array, used for generating a reference current based on the clamping voltage and providing the reference current to the first input terminal of the operational amplifier; a comparator coupled to the output terminal of the operational amplifier, and configured to quantize the output of the operational amplifier into a comparison result; and The SAR logic circuit is used to control the switching of the current source array according to the comparison result, and adjust the current value of the reference current in a successive approximation manner until the quantization is completed.

2. The detection circuit according to claim 1, wherein: The detection result is a comparison result between the signal to be detected and the threshold voltage or a quantization result of a portion of the signal to be detected that enters a window defined by the threshold voltage.

3. The detection circuit according to claim 2, wherein: Also includes: A differential sampling switch is configured to provide an offset voltage or a reference ground voltage to the voltage-to-current conversion circuit.

4. The detection circuit according to claim 3, wherein: The voltage-current conversion circuit comprises: A storage capacitor, a first end of which is used to couple with the output end of the threshold voltage generating circuit and the input end of the signal to be detected; A first transistor, a control terminal of which is used to couple with the second terminal of the storage capacitor; a first resistor, a first end of which is used to couple with the second end of the first transistor, and a second end of which is used to couple with the offset voltage or the reference ground voltage via the differential sampling switch; and The second transistor has a control terminal for receiving a bias voltage, a second terminal for coupling with the first terminal of the first transistor, and a first terminal for outputting the proportional current.

5. The detection circuit according to claim 4, wherein: When the detection result is a comparison result between the signal to be detected and the threshold voltage, the reference current provided by the current source array is a fixed current value.

6. The detection circuit according to claim 4, wherein: When the detection result is a quantization result of the signal to be detected within the window defined by the threshold voltage, the reference current provided by the current source array is a variable current value, and the quantization result is obtained by adjusting the current value of the reference current.

7. The detection circuit according to claim 4, wherein: Also includes: a first switch configured to couple a first end of the storage capacitor and an output end of the threshold voltage generating circuit during a threshold establishing phase; The second switch is configured to couple the first end of the storage capacitor to the input end of the signal to be detected during the detection phase.

8. The detection circuit according to claim 7, wherein: Also includes: The third switch is configured to ground the first end of the storage capacitor in the first sub-phase of the threshold establishment phase to achieve charge resetting.

9. The detection circuit according to claim 8, wherein: The threshold establishing phase further includes a second sub-phase after the first sub-phase, and the threshold voltage generating circuit is configured to generate the threshold voltage in the second sub-phase.

10. The detection circuit according to claim 7, wherein: The voltage-current conversion circuit also includes: The fourth switch is configured to couple the control terminal and the first terminal of the first transistor in the threshold establishment phase.

11. The detection circuit according to claim 1, wherein: The detection circuit includes a plurality of input terminals, and the detection circuit is configured to detect the signals to be detected at the plurality of input terminals in a time-sharing manner.

12. The detection circuit according to claim 11, wherein: It also includes a register array for storing a plurality of control codes corresponding to the signals to be detected at the plurality of input terminals, and the threshold voltage generating circuit generates a corresponding threshold voltage based on the control codes provided by the register array.

13. The detection circuit according to claim 12, wherein: The threshold voltage generating circuit is a capacitive digital-to-analog converter.

14. A power management system, comprising the detection circuit according to any one of claims 1 to 13.

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