Select gate reliability

Abstract

This application relates to select gate reliability. A method includes determining a programmed threshold voltage of a select gate of a memory string, and assigning a programmed reliability class to the select gate based on the programmed threshold voltage. The programmed reliability class indicates that hot data, warm data, and / or cold data is programmable to the memory string. The method further includes incrementing a quality characteristic count to a first verify voltage value, determining a first verified threshold voltage of the select gate at the first verify voltage value, and assigning a first reliability class to the select gate based on the first verified threshold voltage. The first reliability class indicates that the warm data or the cold data, or both, is programmable to the memory string.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to select gate reliability. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] An embodiment of the present disclosure provides a method for select gate reliability, comprising: determining a programmed threshold voltage of a select gate of a memory string; assigning a programmed reliability level to the select gate based on the programmed threshold voltage, wherein the programmed reliability level indicates that hot data, warm data, or cold data, or any combination thereof, is programmable to the memory string; incrementing a quality characteristic count to a first verify voltage value; determining a first verified threshold voltage of the select gate at the first verify voltage value; and assigning a first reliability level to the select gate based on the first verified threshold voltage, wherein the first reliability level indicates that the warm data, the cold data, or both are programmable to the memory string.

[0004] Another embodiment of the present disclosure provides an apparatus for select gate reliability, comprising: a memory cell block comprising a plurality of memory strings; and a memory subsystem reliability component coupled to the memory cell block, wherein the memory subsystem reliability component is configured to: assign respective first select gate programmed reliability levels and second select gate programmed reliability levels to first select gates and second select gates of a memory string in the plurality of memory strings based on respective programmed threshold voltages of the first select gates and the second select gates, wherein the programmed reliability levels indicate that hot data, warm data, or cold data, or any combination thereof, is programmable to the memory string; increment a quality characteristic count of the first select gates and the second select gates to a first verify voltage value; determine a first verify threshold voltage of the first select gate and a second verify threshold voltage of the second select gate at the first verify voltage value; compare the first verify threshold voltage of the first select gate and the second verify threshold voltage to determine that the first select gate and the second select gate have a common first verify threshold voltage reliability; and assign a first reliability level to the first select gate and the second select gate based on the first verify threshold voltage, wherein the first reliability level indicates that the warm data, the cold data, or both are programmable to the memory string.

[0005] Yet another embodiment of the present disclosure provides a system for select gate reliability, comprising: a memory cell block comprising a plurality of memory strings; and a processor coupled to the memory cell block, wherein the processor is configured to: assign a respective first select gate programmed reliability level and a second select gate programmed reliability level to first select gates and second select gates of a memory string in the plurality of memory strings based on respective programmed threshold voltages of the first select gates and the second select gates, wherein the programmed reliability level indicates that hot data, warm data, or cold data, or any combination thereof, is programmable to the memory string; increment a quality characteristic count of the first select gate and the second select gate to a first verify voltage value; determine a first verify threshold voltage of a first select gate and a second verify threshold voltage of a second select gate at the first verify voltage value; compare the first verify threshold voltage of the first select gate and the second verify threshold voltage to determine that the first select gate and the second select gate do not have a common first verify threshold voltage reliability; and assign a first reliability level to the first select gate or the second select gate based on a lower first verify threshold voltage reliability, wherein the first reliability level indicates that the warm data or the cold data, or both, is programmable to the memory string. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2 An example of a memory string including select gates according to some embodiments of the present disclosure is shown.

[0009] Figure 3 shows the threshold voltage (V T ) distribution plot example.

[0010] Figure 4 is a flow chart corresponding to a method for select gate reliability according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Various aspects of the present disclosure relate to select gate reliability in a memory subsystem, and more particularly to a memory subsystem comprising memory strings, wherein each memory string comprises multiple select gates. The memory subsystem may be a memory system, a memory device, a memory module, or a combination thereof. An example of a memory subsystem is a memory system such as a solid-state drive (SSD). Figure 1 , and other figures describe examples of storage devices and memory modules. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as a memory device that stores data (e.g., memory objects). The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] The memory device may be a non-volatile memory device. An example of a non-volatile memory device is a NAND memory device (also known as flash technology). Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. A block, hereinafter, refers to a unit of a memory device for storing data and may include a group of memory cells, a group of word lines, a word line, or an individual memory cell. For some memory devices, a block (hereinafter also referred to as a "memory block") is the smallest area that can be erased. Pages cannot be erased individually, and only entire blocks can be erased.

[0014] Each memory device may include one or more memory cell arrays. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states related to the number of bits being stored. The logical states may be represented by binary values ​​such as "0" and "1," or a combination of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC may store one bit of information and have two logical states.

[0015] Some NAND memory devices employ a floating gate architecture, in which memory access is controlled based on relative voltage changes between a bit line and a word line. Other examples of NAND memory devices may employ a replacement gate architecture that may include the use of a word line layout that may allow for the capture of charge corresponding to the data value within the memory cell based on the properties of the material used to construct the word line. While both floating gate and replacement gate architectures employ the use of select gates (e.g., select gate transistors), replacement gate architectures may include multiple select gates coupled to a string of NAND memory cells. Furthermore, replacement gate architectures may include programmable select gates, whereas floating gate architectures generally do not allow for programming of the select gates. Embodiments provide that the select gates are programmable and, therefore, may be deployed in a replacement gate memory architecture.

[0016] Because the select gates of a replacement gate NAND architecture can be programmed (e.g., can be biased to a logic high (HIGH) or logic low (LOW) state, or states therebetween), such select gates can be susceptible to shifts or "drifts" in the voltage corresponding to the state programmed to the select gate. For example, the threshold voltage (V ) of the select gate of a replacement gate NAND architecture can shift due to physical degradation from the amount of program-erase cycles (PECs) and / or the amount of sensing operations performed by the memory string associated with the select gate. T ) distribution may shift or "drift." That is, the V T can change over time so that the actual V T distribution is different from the expected V corresponding to the select gate T Physical degradation can cause charge loss or charge gain by the select gate over time (eg, over the lifetime of a NAND device employing a replacement gate architecture).

[0017] Some approaches attempt to mitigate the effects of charge loss, charge gain, and / or other voltage drift phenomena experienced by programmable select gates over time by periodically performing select gate scan operations in which the V T The distribution is reset to the expected V Tdistribution. However, such methods perform such select gate scanning operations on all select gates of the entire memory die or all memory dies of a memory device or memory subsystem without taking into account the characteristics of the memory dies of the memory device or memory subsystem. While such methods can correct for the effects of charge loss, charge gain, and / or other voltage drift phenomena experienced by programmable select gates over time, these methods may fail to account for the adverse effects of process variations in the memory dies of the memory device or memory subsystem, as well as for memory die degradation caused by program-erase cycles experienced by the memory cells of the memory die due to the workload distributed to the memory die. Due to the failure to account for these and other real-world characteristics of the memory die, such methods may result in the need to invoke a deep error recovery process in order to correct for the effects of charge loss, charge gain, and / or other voltage drift phenomena experienced by the programmable select gates over time, which may cause an increase in latency experienced by the memory device and / or memory subsystem, and therefore cause a decrease in the quality of service (QoS) provided by the memory device and / or memory subsystem.

[0018] Aspects of the present disclosure address the above and other deficiencies by assigning select gate reliability levels based on threshold voltage values ​​to the respective select gates of respective memory strings. These select gate levels can be utilized to determine which type of data can be programmed into the respective memory strings. This can provide improved end-of-life reliability (e.g., by mitigating physical degradation on the select gates) and reduce degradation-related failures. The select gate reliability levels can be represented by flags, bit patterns, and / or flags, as well as other indicators that can be written to be stored and / or monitored by the memory subsystem.

[0019] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110, according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of these.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a combination of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0021] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a server, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0023] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0025] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of nonvolatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of nonvolatile memory cells. Nonvolatile memory cross-point arrays can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point nonvolatile memories can perform write-in-place operations, where nonvolatile memory cells can be programmed without previously erasing the nonvolatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Each of the memory devices 130, 140 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each memory device 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. For some types of memory (such as NAND), pages may be grouped to form blocks.

[0028] Although nonvolatile memory components such as a three-dimensional cross-point array of nonvolatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory or storage device, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0029] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0030] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0031] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0032] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses, physical media locations, etc.) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0033] Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from memory subsystem controller 115 and decode the addresses to access memory device 130 and / or memory device 140.

[0034] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0035] The memory subsystem 110 may include a select gate reliability component 113. Although Figure 1Although not shown in the figures to avoid obscuring the diagram, the select gate reliability component 113 may include various circuitry to facilitate the execution of select gate reliability operations. As described in greater detail herein, the select gate reliability operations may be performed on respective select gates of respective memory strings of the memory subsystem 110. By performing the select gate reliability operations, the end-of-life reliability of the memory subsystem 110 may be improved and degradation-related failures thereof may be reduced. In some embodiments, the select gate reliability component 113 may include specialized circuitry in the form of an ASIC, an FPGA, a state machine, and / or other logic circuitry that may allow the select gate reliability component 113 to orchestrate and / or execute the operations described herein involving the memory devices 130 and / or 140.

[0036] In some embodiments, the memory subsystem controller 115 includes at least a portion of the select gate reliability component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the select gate reliability component 113 is part of the host system 110, an application, or an operating system.

[0037] In some embodiments, the memory subsystem 110, and therefore the select gate reliability component 113, the processor 119, and the memory devices 130 / 140, may reside on a mobile computing device such as a smartphone, a laptop computer, or a tablet phone, as well as other similar computing devices. As used herein, the term "mobile computing device" generally refers to a handheld computing device having a tablet or tablet phone form factor. Generally speaking, a tablet form factor may include a display screen between approximately 3 inches and 5.2 inches (measured diagonally), while a tablet form factor may include a display screen between approximately 5.2 inches and 7 inches (measured diagonally). However, examples of "mobile computing devices" are not limited thereto, and in some embodiments, a "mobile computing device" may refer to an IoT device or any other type of edge computing device.

[0038] Additionally, the select gate reliability component 113 may reside on the memory subsystem 110. As used herein, the term "resides on" refers to something being physically located on a particular component. For example, the select gate reliability component 113 being "resident" on the memory subsystem 110 refers to a situation where the hardware circuitry comprising the select gate reliability component 113 is physically located on the memory subsystem 110. The term "resides on" may be used interchangeably herein with other terms such as "deployed on" or "located on."

[0039] Figure 2An example of a memory string 231 including select gates 232, 233 according to some embodiments of the present disclosure is shown. In a NAND architecture memory device, a memory block may be organized into strings of memory cells, e.g. Figure 2 , 231. Each respective memory string may include a number of flash memory cells coupled to word lines 234-0 through 234-n coupled in series from drain to source between respective select gates 232, 233 (e.g., transistors). The select gates 232, 233 may represent multiple select gates and / or multiple drains and / or sources of multiple select gates, as described in more detail herein. Embodiments provide that n may have different values ​​for various applications. The memory device may include different numbers of memory strings 231 for various applications.

[0040] The memory string 231 can be turned on using the select gate drain (SGD) 232 and the select gate source (SGS) 233 connected in series to perform operations, such as programming or reading the memory cells coupled to the word lines 234-0 to 234-n. Embodiments of the present disclosure provide that the select gates 232, 233 are processed (e.g., manufactured) as the memory cells coupled to the word lines 234-0 to 234-n are processed. In other words, the select gates 232, 233 are cells of the same type as the memory cells coupled to the word lines 234-0 to 234-n. For example, the select gates 232, 233 are formed by transistors of the same type as the NAND flash memory cells coupled to the word lines 234-0 to 234-n. Although shown Figure 2 2. Although only one select gate 232, 234 is shown, it is contemplated within the scope of the present disclosure that the memory string 231 may be coupled to multiple select gates, each of which may include a respective SGD and SGS.

[0041] Since the select gates 232, 233 initially behave the same as the memory cells coupled to the word lines 234-0 to 234-n, the select gates 232, 233 can also be programmed and erased. Thus, prior to initial use of the memory device, the select gates 232, 233 can be programmed to a specific programmed threshold voltage (e.g., an initial threshold voltage) to enable proper operation of each memory string 231 of the memory cells coupled to the word lines 234-0 to 234-n. Whenever the threshold voltage is applied to the Figure 2 When the control gates of one or more of the transistors shown in are turned on, the select gates 232, 233 may then be turned on.

[0042] Figure 3 shows the threshold voltage (V T ) distribution plot example. Figure 3As shown in FIG. 1 , the select gates of the memory strings (eg, select gate 232 and / or select gate 233 of memory string 231, as shown in FIG. Figure 2 ) can have a programmed threshold voltage within a programmed threshold voltage distribution 341. As mentioned, the programmed threshold voltage can be programmed to a specific threshold voltage prior to initial use of the memory device. The programmed threshold voltage can have different values ​​for various applications.

[0043] An embodiment provides that select gates are assigned select gate reliability levels based on the threshold voltage values ​​of the respective select gates of the respective memory strings.These select gate reliability levels can be utilized to determine which type of data can be programmed into the respective memory strings.

[0044] A select gate having a programmed threshold voltage can be assigned a programmed threshold voltage reliability level. A select gate having a programmed threshold voltage reliability level (i.e., a select gate having a programmed threshold voltage) is in a least physically degraded state compared to other select gates having increased and / or decreased threshold voltages due to program-erase cycles (PECs) and / or sensing operations performed by the memory string associated with the select gate. Because the select gate having the programmed threshold voltage reliability level is in the least physically degraded state (e.g., the healthiest), hot data, warm data, cold memory data, or any combination thereof can be programmed into a memory string that includes a select gate having a programmed threshold voltage.

[0045] Embodiments provide that data (e.g., memory objects) may be assigned corresponding flags. As used herein, a "memory object" refers to data that can be written to and / or read from a memory device. Herein, data may have one of three or more flags. A first flag may be referred to as generally "hot" (e.g., a hot memory object and / or hot data). A second flag may be referred to as generally "warm" (e.g., a warm memory object and / or warm data). A third flag may be referred to as generally "cold" (e.g., a cold memory object and / or cold data). Other flags may include combinations of the three listed flags.

[0046] As used herein, "cold data" means that particular data or a particular memory object has not been accessed for a long duration relative to other data or memory objects read from a memory device. As used herein, "hot data" means that particular data or a particular memory object has been frequently accessed relative to other data or memory objects read from a memory device. As used herein, "warm data" means that particular data or a particular memory object has been accessed more frequently than "cold data," but less frequently than "hot data." As mentioned above, intermediate "temperatures" of data are considered, such that there may be flags that fall between the first, second, and / or third flags described herein.

[0047] Thus, the first sign (hot sign) can be considered hotter than the second sign (warm sign), and both the first sign and the second sign can be considered hotter than the third sign (cold sign). Similarly, the third sign (cold) can be considered colder than either the second sign (warm) or the first sign (hot).

[0048] Several parameters may be utilized in marking data as hot, warm, or cold. Embodiments provide that the number of parameters may be weighted differently for various applications.

[0049] Access frequency can be used when marking data as hot, warm, or cold. Access frequency indicates how often the associated address space is accessed during a specific time interval. Generally, a greater access frequency will make data hotter than other data with a lower access frequency. In other words, data with the highest access frequency will generally be marked as hot, and data with the lowest access frequency will generally be marked as cold. Data marked as warm will generally have a lower access frequency than data marked as hot, but a higher access frequency than data marked as cold.

[0050] The size of the data can be used when marking data as hot, warm, or cold. The size of the data can correspond to the number of bits or other information contained within the data. Generally, a smaller size will make the data hotter than other data with a larger size. In other words, data with the smallest size will generally be marked as hot, and data with the largest size will generally be marked as cold. Data marked as warm will generally have a larger size than data marked as hot, and a smaller size than data marked as cold.

[0051] The amount of large sequential write traffic relative to the amount of small non-sequential write traffic can be used when marking data as hot, warm, or cold. Data with a large amount of small non-sequential write traffic will generally be hotter than other data (i.e., data accessed sequentially or serially) with a large amount of large sequential write traffic. In other words, data with a large amount of small non-sequential write traffic will generally be marked as hot, and data with a large amount of large sequential write traffic will generally be marked as cold, while data marked as warm will have a smaller amount of small non-sequential write traffic than data marked as hot.

[0052] The amount of error correction performed on data can be used to mark data as hot, warm, or cold. Generally, fewer error corrections during a time interval will make the data hotter than other data with more error corrections during the time interval. Similarly, more error corrections during a time interval will make the data colder than other data with fewer error corrections during the time interval.

[0053] The amount of read / write disturb operations involving the memory cells in which data is stored can be used when marking data as hot, warm, or cold. Generally, less read / write disturb during a time interval will make the data hotter than other data with more read / write disturb during the time interval. Similarly, more read / write disturb during a time interval will make the data colder than other data with less read / write disturb during the time interval.

[0054] Embodiments provide that data may change signs over time. For example, hot data may later become warm data, and warm data may later become cold data. Similarly, cold data may later become warm data, and warm data may later become hot data.

[0055] As mentioned, due to physical degradation, the threshold voltage distribution 341 of the select gate may shift or "drift." This physical degradation may occur due to operations related to the quality characteristics performed by the memory string including the select gate. For example, as more operations related to the quality characteristics performed by the memory string including the select gate are performed, the physical degradation of the select gate increases. As used herein, "quality characteristics" generally refers to the number of program-erase cycles (PECs) and / or the number of sensing operations performed involving the memory cells and / or select gates of the memory string.

[0056] As used herein, the term "quality characteristic" and variations thereof generally refer to quantifiable properties of a memory die and / or its constituent components (e.g., select gates) that affect the performance of the memory die and / or constituent components, and therefore, the performance of the memory device or memory subsystem in which the memory die is deployed. Non-limiting examples of quality characteristics may include: the number of program-erase cycles (PECs) experienced by the memory cells of the memory die; the operating temperature to which the memory die has been subjected; physical age (e.g., the number of months or years that the device has been in the field independent of PECs); workload, which may be measured by the number of read, write, and / or erase operations; disturb effects; charge loss, charge gain, and / or other voltage drift phenomena experienced by the programmable select gates of the memory die; and the presence of other errors in the memory device and / or memory subsystem.

[0057] Several embodiments of the present disclosure provide that a quality characteristic is based at least in part on a number of program-erase cycles (PECs) and / or a number of sensing operations (e.g., read operations) performed by a memory string associated with a select gate. For example, a combination (e.g., a sum) of the number of program-erase cycles (PECs) and / or the number of sensing operations performed by a memory string associated with a select gate may be used to count the quality characteristic.

[0058] One or more embodiments provide that a quality characteristic count may be incremented (e.g., increased) from a starting value (e.g., zero) at each instance of a program-erase cycle (PEC) and / or a sense operation performed by a memory string associated with a select gate. Embodiments provide that a respective quality characteristic count may exist for each respective memory string of a memory device.

[0059] One or more embodiments provide that the quality characteristic count may be incremented to a first verify voltage value 343. The first verify voltage value may have different values ​​for various applications. When the quality characteristic count equals the first verify voltage value 343, the threshold voltage of the select gate of the memory string may be determined.

[0060] When the threshold voltage of one or more of the select gates of the memory string is determined at the first verify voltage value 343 and the determined threshold voltage of the select gate is within a predetermined range of the programmed threshold voltage of the select gate of the memory string, the select gate reliability level of the programmed threshold voltage reliability level is maintained. The predetermined range can have different values ​​for various applications. For example, the predetermined range can vary from the programmed threshold voltage by ±5%, ±10%, or ±15%, among other values.

[0061] When the threshold voltage of one or more of the select gates of the memory string is determined at the first verify voltage value 343 and the determined threshold voltage of the select gate is within a predetermined range of the programmed threshold voltage of the select gate of the memory string, the quality characteristic count can continue to be incremented from the first verify voltage value 343 to a predetermined value, from which the threshold voltage of the select gate of the memory string can be re-determined. The predetermined value can have different values ​​for various applications. For example, the predetermined value can be 5, 10, or 15 instances of program-erase cycles (PEC) and / or sensing operations, among other values. This incrementing and re-determining of the threshold voltage of the select gate can be repeated (while maintaining the programmed threshold voltage reliability level) until the determined threshold voltage of the select gate of the memory string shifts beyond the predetermined range of the programmed threshold voltage.

[0062] When the threshold voltage of a select gate of a memory string shifts (ie, increases or decreases) beyond a predetermined range of programmed threshold voltages, the select gate may be assigned a first reliability level. Figure 3 , shifted threshold voltage distribution 342 has increased compared to threshold voltage distribution 341. Shifted threshold voltage distribution 342 indicates that physical degradation has occurred compared to the state of the select gate with threshold voltage distribution 341 (e.g., the select gate with shifted threshold voltage distribution 342 is less healthy (more degraded) than the select gate with threshold voltage distribution 341). Although Figure 3Shifted threshold voltage distribution 342 is shown as being increased compared to threshold voltage distribution 341, but embodiments are not limited. For example, several embodiments provide that shifted threshold voltage distribution 342 can be decreased compared to threshold voltage distribution 341.

[0063] The first reliability level indicates that warm data or cold data or both can be programmed to the memory string.In contrast to the programmed threshold voltage reliability level, hot data cannot be programmed to a memory string including at least one select gate having the first reliability level.

[0064] One or more embodiments provide that the quality characteristic count may be incremented to a second verify voltage value 344. The second verify voltage value may have different values ​​for various applications. When the quality characteristic count equals the second verify voltage value 344, the threshold voltage of the select gate of the memory string may be determined.

[0065] When the threshold voltage of one or more of the select gates of the memory string is determined at the second verify voltage value 344 and the determined threshold voltage of the select gate is within a predetermined range of the threshold voltage of the select gate associated with the first reliability level, the select gate reliability level of the first reliability level is maintained. The predetermined range can have different values ​​for various applications. For example, the predetermined range can vary from the first threshold voltage by ±5%, ±10%, or ±15%, among other values.

[0066] When the threshold voltage of one or more of the select gates of the memory string is determined at the second verify voltage value 344 and the determined threshold voltage of the select gate is within the predetermined range of the threshold voltage of the select gate associated with the first reliability level, the quality characteristic count can continue to be incremented from the second verify voltage value 344 to a predetermined value, from which the threshold voltage of the select gate of the memory string can be re-determined. The predetermined value can have different values ​​for various applications. For example, the predetermined value can be 5, 10, or 15 instances of program-erase cycles (PEC) and / or sensing operations, among other values. This incrementing and re-determining of the threshold voltage of the select gate can be repeated (while maintaining the first reliability level) until the determined threshold voltage of the select gate of the memory string shifts beyond the predetermined range of the threshold voltage of the select gate associated with the first reliability level.

[0067] When the threshold voltage of the select gate of a memory string shifts (i.e., increases or decreases) beyond a predetermined range of the threshold voltage of the select gate associated with the first reliability level, the select gate may be assigned a second reliability level. This shifted threshold voltage indicates that physical degradation has occurred compared to the state of the select gate having the first reliability level (e.g., the select gate having the shifted second reliability level is less healthy (more degraded) than the select gate having the first reliability level). The shifted threshold voltage of the select gate having the second reliability level may be increased or decreased compared to the select gate having the first reliability level.

[0068] The second reliability level indicates that cold data may be programmed into the memory string. In contrast to the first reliability rating, warm data may not be programmed into a memory string including at least one select gate having the second reliability level.

[0069] One or more embodiments provide that the quality characteristic count may be incremented to a third verify voltage value 345. The third verify voltage value may have different values ​​for various applications. When the quality characteristic count equals the third verify voltage value 345, the threshold voltage of the select gate of the memory string may be determined.

[0070] When the threshold voltage of one or more of the select gates of the memory string is determined at the third verify voltage value 345 and the determined threshold voltage of the select gate is within a predetermined range of the threshold voltage of the select gate associated with the second reliability level, the select gate reliability level of the second reliability level is maintained. The predetermined range can have different values ​​for various applications. For example, the predetermined range can vary from the second threshold voltage by ±5%, ±10%, or ±15%, among other values.

[0071] When the threshold voltage of one or more of the select gates of the memory string is determined at the third verify voltage value 345 and the determined threshold voltage of the select gate is within the predetermined range of the threshold voltage of the select gate associated with the second reliability level, the quality characteristic count can continue to be incremented from the third verify voltage value 344 to a predetermined value, from which the threshold voltage of the select gate of the memory string can be re-determined. The predetermined value can have different values ​​for various applications. For example, the predetermined value can be 5, 10, or 15 instances of program-erase cycles (PEC) and / or sensing operations, among other values. This incrementing and re-determining of the threshold voltage of the select gate can be repeated (while maintaining the second reliability level) until the determined threshold voltage of the select gate of the memory string shifts beyond the predetermined range of the threshold voltage of the select gate associated with the second reliability level.

[0072] When the threshold voltage of the select gate of a memory string shifts (i.e., increases or decreases) beyond a predetermined range of the threshold voltage of the select gate associated with the second reliability level, the select gate may be assigned a third reliability level. This shifted threshold voltage indicates that physical degradation has occurred compared to the state of the select gate having the second reliability level (e.g., the select gate having the shifted third reliability level is less healthy (more degraded) than the select gate having the second reliability level). The shifted threshold voltage of the select gate having the third reliability level may be increased or decreased compared to the select gate having the second reliability level.

[0073] A third reliability level indicates that hot, warm, or cold data, or any combination thereof, cannot be programmed to the memory string.A third reliability level indicates that the memory string including at least one select gate having the third reliability level is approaching or at end of useful life.

[0074] The select gates of a particular memory string may have the same select gate reliability rating. For example, the select gates of the particular memory string may each have a programmed reliability rating indicating that hot data, hot data and cold data, or any combination thereof, may be programmed into the memory string; the select gates of the particular memory string may each have a first reliability rating indicating that warm data and cold data, or any combination thereof, may be programmed into the memory string; the select gates of the particular memory string may each have a second reliability rating indicating that cold data may be programmed into the memory string; or the select gates of the particular memory string may each have a third reliability rating indicating that hot data, warm data, cold data, or any combination thereof, may not be programmed into the memory string.

[0075] However, embodiments are not so limited. For example, the select gates of a particular memory string may have different select gate reliability ratings. When the select gates of a particular memory string have different select gate reliability ratings, the rating of the more degraded select gate is used to determine which type(s) of data, if any, can be programmed into the memory string. For example, the first select gate of a particular memory string may have a programmed reliability rating, while the second select gate of the particular memory string may have a first reliability rating. In this example, warm data and cold data, or any combination thereof (corresponding to the first reliability rating), can be programmed into the particular memory string, while hot data cannot be programmed into the particular memory string. Similarly, the first select gate of a particular memory string may have a first reliability rating, while the second select gate of the particular memory string may have a second reliability rating. In this example, cold data (corresponding to the second reliability rating) can be programmed into the particular memory string, while warm data cannot be programmed into the particular memory string. Furthermore, the first select gate of a particular memory string may have a second reliability rating, while the second select gate of the particular memory string may have a third reliability rating. In this example, hot data, warm data, cold data, or any combination thereof cannot be programmed into the memory string (corresponding to the third reliability rating).

[0076] Figure 4 is a flow chart corresponding to method 450 for select gate reliability operations according to some embodiments of the present disclosure. Method 540 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 450 is performed by Figure 1 The select gate reliability component 113 is executed. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0077]

[0066] The programmed threshold voltages of the select gates of the memory strings can be determined at operation 451. As an example, each of the select gates of each memory string can be programmed to a respective specific programmed threshold voltage.

[0078] At operation 452, the select gates can be assigned a programmed reliability level based on the programmed threshold voltage, where the programmed reliability level indicates that hot, warm, or cold data, or any combination thereof, can be programmed to the memory string.

[0079] At operation 453, a quality characteristic count may be incremented to a first verify voltage value. As described above, the quality characteristic may be based at least in part on the number of program-erase cycles (PECs) and / or the number of sensing operations (e.g., read operations) performed by the memory string associated with the select gate. The quality characteristic count may correspond to a value indicating a summary of one or more quality characteristics.

[0080] At operation 454, a first verified threshold voltage of the select gate may be determined at the first verify voltage value. The first verified threshold voltage value may be similar to Figure 3 The first calibration voltage value 343 is shown in FIG.

[0081] At operation 455, a first reliability level can be assigned to the select gate based on the first verified threshold voltage.The first reliability level indicates that warm data or cold data, or both, can be programmed to the memory string.

[0082] Method 450 may include one or more operations for incrementing a quality characteristic count to a second verify voltage value. When the quality characteristic count reaches the second voltage value, a second verified threshold voltage may be determined for the select gate. A second reliability level may be assigned to the select gate based on the second verified threshold voltage, wherein the second reliability level indicates that cold data can be programmed into the memory string.

[0083] Method 450 may include one or more operations for incrementing the quality characteristic count to a third verified voltage value. When the quality characteristic count reaches the third voltage value, a third verified threshold voltage may be determined for the select gate. A third reliability level may be assigned to the select gate based on the third verified threshold voltage, wherein the third reliability level indicates that hot data, warm data, or cold data, or any combination thereof, may not be programmed into the memory string.

[0084] Figure 5 is a block diagram of an example computer system 500 in which embodiments of the present disclosure may operate. For example, Figure 5 An example machine of a computer system 500 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to perform operations of the controller (for example, to execute an operating system to execute a corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0085] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0086] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0087] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may also include a network interface device 508 for communicating via a network 520.

[0088] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0089] In one embodiment, instructions 526 include instructions for implementing a method corresponding to a select gate reliability component (e.g., Figure 1 The invention also includes instructions for the functionality of the select gate reliability component 113 of the present invention. Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0090] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts can most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. An operation is one requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, it has proven convenient, primarily for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0091] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within computer system registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0092] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0093] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures for a variety of these systems will appear as described below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure described herein.

[0094] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, or the like.

[0095] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the specific example embodiments of the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method for selecting gate reliability, comprising: determining a programmed threshold voltage of a select gate of a memory string; assigning a programmed reliability level to the select gate based on the programmed threshold voltage, wherein the programmed reliability level indicates that hot data, warm data, or cold data, or any combination thereof, is capable of being programmed to the memory string; Incrementing the quality characteristic count to a first verification voltage value; determining a first verified threshold voltage of the select gate at the first verify voltage value; as well as The select gate is assigned a first reliability level based on the first verified threshold voltage, wherein the first reliability level indicates that the warm data or the cold data, or both, are capable of being programmed to the memory string.

2. The method according to claim 1, further comprising: Incrementing the quality characteristic count to a second verification voltage value; determining a second verified threshold voltage of the select gate at the second verified voltage value; as well as The select gate is assigned a second reliability level based on the second verified threshold voltage, wherein the second reliability level indicates that the cold data is capable of being programmed to the memory string.

3. The method according to claim 2, further comprising: incrementing the quality characteristic count to a third verified voltage value; determining a third verified threshold voltage of the select gate at the third verified voltage value; as well as The select gate is assigned a third reliability level based on the third verified threshold voltage, wherein the third reliability level indicates that the hot data, the warm data, or the cold data, or any combination thereof, cannot be programmed to the memory string. 4 . The method of claim 3 , wherein the first verified threshold voltage is greater than the programmed threshold voltage, the second verified threshold voltage is greater than the first verified threshold voltage, and the third verified threshold voltage is greater than the second verified threshold voltage.

5. The method of claim 3, wherein the first verified threshold voltage is less than the programmed threshold voltage, the second verified threshold voltage is less than the first verified threshold voltage, and the third verified threshold voltage is less than the second verified threshold voltage. 6 . The method of claim 1 , wherein the quality characteristic count is based at least in part on a quantity of program-erase cycles (PECs) and a quantity of sensing operations performed by the memory string. The method of claim 1 , wherein the select gate is programmable.

8. An apparatus for selecting gate reliability, comprising: a memory cell block comprising a plurality of memory strings; as well as a memory subsystem reliability component coupled to the memory cell block, wherein the memory subsystem reliability component is configured to: assigning respective first and second select gate programmed reliability levels to first and second select gates of a memory string of the plurality of memory strings based on respective programmed threshold voltages of the first and second select gates, wherein the programmed reliability levels indicate that hot data, warm data, or cold data, or any combination thereof, is capable of being programmed to the memory string; incrementing a quality characteristic count of the first select gate and the second select gate to a first verify voltage value; determining a first verified threshold voltage of a first select gate and a second verified threshold voltage of a second select gate at the first verify voltage value; comparing a first verified threshold voltage of the first select gate and a first verified threshold voltage of the second select gate to determine that the first select gate and the second select gate have a common first verified threshold voltage reliability; as well as The first select gate and the second select gate are assigned a first reliability level based on the first verified threshold voltage, wherein the first reliability level indicates that the warm data or the cold data or both are capable of being programmed to the memory string.

9. The apparatus of claim 8, wherein the first reliability level indicates that the first select gate and the second select gate of the memory string are degraded compared to the first select gate and the second select gate having the respective first select gate programmed reliability levels and the second select gate programmed reliability levels.

10. The apparatus of claim 8, wherein the memory subsystem reliability component is configured to incrementing the quality characteristic count of the first select gate and the second select gate to a second verify voltage value; determining a first select gate second verified threshold voltage and a second select gate second verified threshold voltage at the second verified voltage value; comparing a second verified threshold voltage of the first select gate and a second verified threshold voltage of the second select gate to determine that the first select gate and the second select gate have a common second verified threshold voltage reliability; as well as The first and second select gates are assigned a second reliability level based on the second verified threshold voltage, wherein the second reliability level indicates that the cold data is capable of being programmed to the memory string.

11. The apparatus of claim 10, wherein the second reliability level indicates that the first and second select gates of the memory string are degraded compared to the first and second select gates having the first reliability level.

12. The apparatus of claim 10, wherein the memory subsystem reliability component is configured to: incrementing the quality characteristic count of the first select gate and the second select gate to a third verified voltage value; determining a first select gate third verified threshold voltage and a second select gate third verified threshold voltage at the third verified voltage value; comparing a third verified threshold voltage of the first select gate and a third verified threshold voltage of the second select gate to determine that the first select gate and the second select gate have a common third verified threshold voltage reliability; as well as The first and second select gates are assigned a third reliability level based on the third verified threshold voltage, wherein the third reliability level indicates that the hot data, the warm data, or the cold data, or any combination thereof, cannot be programmed to the memory string.

13. The apparatus of claim 12, wherein the third reliability level indicates that the first and second select gates of the memory string are degraded compared to the first and second select gates having the second reliability level.

14. The apparatus of claim 8, wherein the first select gate and the second select gate are connected in series.

15. The apparatus of claim 8, wherein the quality characteristic count is based at least in part on a combination of a number of program-erase cycles (PECs) and a number of sensing operations performed by the memory string.

16. A system for selecting gate reliability, comprising: a memory cell block comprising a plurality of memory strings; as well as a processor coupled to the memory unit block, wherein the processor is configured to: assigning respective first select gate programmed reliability levels, second select gate programmed reliability levels to first select gates and second select gates of memory strings of the plurality of memory strings based on respective programmed threshold voltages of the first select gates and the second select gates, wherein the programmed reliability levels indicate that hot data, warm data, or cold data, or any combination thereof, is capable of being programmed to the memory strings; incrementing a quality characteristic count of the first select gate and the second select gate to a first verify voltage value; determining a first verified threshold voltage of a first select gate and a second verified threshold voltage of a second select gate at the first verify voltage value; comparing a first verified threshold voltage of the first select gate and a first verified threshold voltage of the second select gate to determine that the first select gate and the second select gate do not have a common first verified threshold voltage reliability; as well as The first select gate or the second select gate is assigned a first reliability grade based on a lower first verified threshold voltage reliability, wherein the first reliability grade indicates that the warm data or the cold data, or both, are capable of being programmed to the memory string.

17. The system of claim 16, wherein the processor is configured to incrementing the quality characteristic count of the first select gate and the second select gate to a second verify voltage value; determining a first select gate second verified threshold voltage and a second select gate second verified threshold voltage at the second verified voltage value; comparing the first select gate second verified threshold voltage and the second select gate second verified threshold voltage to determine that the first select gate and the second select gate do not have a common second verified threshold voltage reliability; as well as The first select gate or the second select gate is assigned a second reliability level based on a lower second verified threshold voltage reliability, wherein the second reliability level indicates that the cold data is capable of being programmed to the memory string.

18. The system of claim 17, wherein the processor is configured to incrementing the quality characteristic count of the first select gate and the second select gate to a third verified voltage value; determining a first select gate third verified threshold voltage and a second select gate third verified threshold voltage at the third verified voltage value; comparing the first select gate third verified threshold voltage and the second select gate third verified threshold voltage to determine that the first select gate and the second select gate do not have a common third verified threshold voltage reliability; as well as The first select gate or the second select gate is assigned a third reliability level based on a lower third verified threshold voltage reliability, wherein the third reliability level indicates that the hot data, the warm data, or the cold data, or any combination thereof, cannot be programmed to the memory string.

19. The system of claim 16, wherein the first select gate and the second select gate of the memory string are connected in series.

20. The system of claim 16 , wherein the processor is to assign a first reliability grade to the first select gate or the second select gate of another memory string based on a lower first verified threshold voltage reliability of the first select gate or the second select gate of the other memory string, wherein the first reliability grade indicates that the warm data or the cold data or both are capable of being programmed to the other memory string.

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