A common-source common-gate gallium nitride device and a preparation method and chip thereof

Abstract

The application belongs to the technical field of semiconductors, and provides a common-source common-gate gallium nitride device and a preparation method and a chip thereof. A first N-type heavily doped region, a second N-type heavily doped region, a P-type heavily doped region, a source metal layer, a contact metal layer, an isolation layer and a first gate metal layer are formed on a P-type semiconductor substrate, and then a MOS device is formed. An HEMT device is formed by the contact metal layer, a drain metal layer, a drift layer, a barrier layer, a cap layer and a second gate metal layer. A fast recovery diode is formed between the source metal layer and the second gate metal layer. The PN junction and the active region of the MOS device are isolated by the isolation layer. A gate resistor for linking the source metal layer and the second gate metal layer is formed between the fast recovery diode and the isolation layer. Thus, the turn-on loop and the turn-off loop of the driving circuit of the HEMT are separated, the turn-on speed of the HEMT device is ensured, and the electromagnetic effect caused by too fast voltage change can be eliminated.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, and in particular relates to a common-source common-gate gallium nitride device and its fabrication method and chip. Background Technology

[0002] The common-source common-gate gallium nitride (GaN cascode) device is a device that combines a low-voltage silicon-oxygen-semiconductor field-effect transistor (MOSFET) with a high-voltage gallium nitride high electron mobility transistor (GaN HEMT). This GaN cascode device integrates the high voltage and high mobility of HEMT and the high reliability of low-voltage MOSFET, making it very popular in the current high-voltage application market for GaN.

[0003] However, a problem with current GaN cascode devices is that they cannot effectively control the rate of voltage change (dv / dt), which leads to electromagnetic interference (EMI) effects, increases switching losses, and limits the application scenarios of GaN cascodes. Summary of the Invention

[0004] This application provides a common-source, common-gate gallium nitride device and its fabrication method and chip, aiming to solve the problem of electromagnetic interference (EMI) effect in current GaN cascode devices.

[0005] To address the aforementioned technical problems, a first aspect of this application provides a common-source, common-gate gallium nitride device, comprising:

[0006] P-type semiconductor substrate;

[0007] A first N-type heavily doped region, a second N-type heavily doped region, and a P-type heavily doped region are respectively formed on a first predetermined region on the P-type semiconductor substrate; wherein, the P-type heavily doped region and the second N-type heavily doped region are located on opposite sides of the first N-type heavily doped region, and the first N-type heavily doped region and the second N-type heavily doped region do not contact each other.

[0008] An L-shaped buffer layer is formed on the P-type semiconductor substrate, wherein the horizontal portion and the vertical portion of the L-shaped buffer layer are respectively located in the first preset region and the second preset region on the P-type semiconductor substrate;

[0009] An isolation layer is formed in a portion of the first heavily doped N-type region, the second heavily doped N-type region, and the P-type semiconductor substrate; wherein the isolation layer is in contact with the L-shaped buffer layer;

[0010] A source metal layer is formed in the first via of the isolation layer and is in contact with the P-type heavily doped region and the first N-type heavily doped region;

[0011] A first gate metal layer is formed within the isolation layer and is located at the center line position between the first heavily doped N-type region and the second heavily doped N-type region;

[0012] A drift layer and a barrier layer are stacked sequentially on the L-shaped buffer layer, and the shape of the drift layer is the same as that of the L-shaped buffer layer.

[0013] A capping layer and a second gate metal layer are sequentially stacked on the barrier layer, with the capping layer located between the second gate metal layer and the drift layer;

[0014] P-type gallium nitride doped regions and N-type gallium nitride doped regions are formed on the drift layer, and the N-type gallium nitride doped region is located between the P-type gallium nitride doped region and the second gate metal layer;

[0015] A second via is formed on the isolation layer and contacts the second N-type heavily doped region and the barrier layer;

[0016] A drain metal layer is formed on the barrier layer and is located on both sides of the second gate metal layer, respectively, along with the contact metal layer.

[0017] In one embodiment, the isolation layer is further used to isolate the first gate metal layer from the drift layer.

[0018] In one embodiment, the P-type heavily doped region is in contact with the first N-type heavily doped region.

[0019] In one embodiment, the source metal layer, the second gate metal layer, the first N-type heavily doped region, the second N-type heavily doped region, and the P-type heavily doped region have the same length; the source metal layer is in contact with the P-type gallium nitride doped region.

[0020] In one embodiment, neither the N-type gallium nitride doped region nor the P-type gallium nitride doped region is in contact with the isolation layer.

[0021] In one embodiment, the P-type gallium nitride doped region and the N-type gallium nitride doped region are not in contact with each other.

[0022] In one embodiment, the second gate metal layer is not in contact with the N-type gallium nitride doped region.

[0023] In one embodiment, the barrier layer is located on the vertical portion of the drift layer, and the N-type gallium nitride doped region and the P-type gallium nitride doped region are located on the horizontal portion of the drift layer.

[0024] A second aspect of this application also provides a method for fabricating a common-source, common-gate gallium nitride device, the method comprising:

[0025] A first N-type heavily doped region, a second N-type heavily doped region, and a P-type heavily doped region are formed in a first predetermined region of a P-type semiconductor substrate; wherein the P-type heavily doped region and the second N-type heavily doped region are located on opposite sides of the first N-type heavily doped region, and the first N-type heavily doped region and the second N-type heavily doped region do not contact each other;

[0026] An L-shaped buffer layer is formed on the P-type semiconductor substrate; wherein the horizontal portion and the vertical portion of the L-shaped buffer layer are respectively located in the first preset region and the second preset region on the P-type semiconductor substrate;

[0027] An isolation layer is formed on a portion of the first N-type heavily doped region, the second N-type heavily doped region, and the P-type semiconductor substrate; wherein the isolation layer is in contact with the L-shaped buffer layer;

[0028] A source metal layer is formed within the first via of the isolation layer; wherein the source metal layer is in contact with the P-type heavily doped region and the first N-type heavily doped region;

[0029] A first gate metal layer is formed on the isolation layer, and an isolation material is formed on the first gate metal layer so that the isolation layer encapsulates the first gate metal layer; wherein the first gate metal layer is located at the center line position between the first heavily doped N-type region and the second heavily doped N-type region;

[0030] A drift layer and a barrier layer are sequentially formed on the L-shaped buffer layer; wherein the shape of the drift layer is the same as the shape of the L-shaped buffer layer.

[0031] A capping layer and a second gate metal layer are formed on the barrier layer; wherein the capping layer is located between the second gate metal layer and the drift layer;

[0032] A P-type gallium nitride doped region and an N-type gallium nitride doped region are formed on the drift layer; wherein the N-type gallium nitride doped region is located between the P-type gallium nitride doped region and the second gate metal layer;

[0033] A second via is formed on the isolation layer to form a contact metal layer; wherein the contact metal layer is in contact with the second N-type heavily doped region and the barrier layer;

[0034] A drain metal layer is formed on the barrier layer; wherein the drain metal layer and the contact metal layer are located on opposite sides of the second gate metal layer.

[0035] A third aspect of this application also provides a chip, including a common-source gallium nitride device as described in any of the above embodiments; or including a common-source gallium nitride device prepared by the preparation method described in the above embodiments.

[0036] The beneficial effects of the embodiments in this application compared with the prior art are:

[0037] A MOS device is formed by forming a first N-type heavily doped region, a second N-type heavily doped region, a P-type heavily doped region, a source metal layer, a contact metal layer, an isolation layer, and a first gate metal layer on a P-type semiconductor substrate. A HEMT structure is formed by the contact metal layer, drain metal layer, drift layer, barrier layer, capping layer, and second gate metal layer. A fast recovery diode is formed between the source metal layer and the second gate metal layer through P-type and N-type doping. An isolation layer isolates the fast recovery diode from the active region of the MOS device. A gate resistor is formed between the fast recovery diode and the isolation layer to link the source metal layer and the second gate metal layer. This clamps the gate of the gallium nitride HEMT device with a fast recovery diode, achieving the separation of the turn-on and turn-off circuits of the HEMT's drive circuit. This ensures the turn-on speed of the HEMT device and eliminates electromagnetic effects caused by rapid voltage changes, enhancing the performance and stability of the cascode gallium nitride device. Attached Figure Description

[0038] Figure 1 A schematic diagram of the structure of the common-source, common-gate gallium nitride device provided in an embodiment of this application is shown;

[0039] Figure 2 It shows Figure 1 A cross-sectional diagram at the position of the dashed line AA';

[0040] Figure 3 It shows Figure 1 A cross-sectional diagram at the position of the dashed line BB';

[0041] Figure 4 It shows Figure 1 A cross-sectional view at the position of the dashed line CC';

[0042] Figure 5 A schematic diagram of the equivalent circuit structure of the common-source, common-gate gallium nitride device provided in an embodiment of this application is shown;

[0043] Figure 6 This illustration shows a schematic diagram of the fabrication process of the common-source, common-gate gallium nitride device provided in the embodiments of this application. Detailed Implementation

[0044] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0045] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0046] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0047] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0048] The common-source common-gate gallium nitride (GaN cascode) device is a device that combines a low-voltage silicon-oxygen-semiconductor field-effect transistor (MOSFET) with a high-voltage gallium nitride high electron mobility transistor (GaN HEMT). This GaN cascode device integrates the high voltage and high mobility of HEMT and the high reliability of low-voltage MOSFET, making it very popular in the current high-voltage application market for GaN.

[0049] However, a problem with current GaN cascode devices is that they cannot effectively control the rate of voltage change (dv / dt), which leads to electromagnetic interference (EMI) effects, increases switching losses, and limits the application scenarios of GaN cascodes.

[0050] In related technologies, MOS devices typically use gate resistance Rg to reduce dv / dt, thereby eliminating EMI effects. GaN cascode devices are formed by combining MOSFET and GaN HEMT, and the gate of GaN HEMT is connected to the source of Si MOS. Controlling Rg of a single MOS device cannot significantly change the dv / dt of GaN cascode.

[0051] To address the aforementioned technical problems, this application provides a common-source, common-gate gallium nitride device, see [link to relevant documentation]. Figure 1 As shown, the common-source, common-gate gallium nitride device in this embodiment includes: a P-type semiconductor substrate 100, a first N-type heavily doped region 110, a second N-type heavily doped region 120, a P-type heavily doped region 130, an L-shaped buffer layer 200, an isolation layer 300, a source metal layer 310, a first gate metal layer 320, a drift layer 410, a barrier layer 420, a capping layer 440, a second gate metal layer 430, a P-type gallium nitride doped region 510, an N-type gallium nitride doped region 520, a contact metal layer 450, and a drain metal layer 460.

[0052] Specifically, the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type heavily doped region 130 are respectively formed in the first predetermined region on the P-type semiconductor substrate 100.

[0053] In this embodiment, as Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the P-type heavily doped region 130 and the second N-type heavily doped region 120 are located on both sides of the first N-type heavily doped region 110, and the first N-type heavily doped region 110 and the second N-type heavily doped region 120 do not contact each other.

[0054] An L-shaped buffer layer 200 is formed on a P-type semiconductor substrate 100, with the horizontal and vertical portions of the L-shaped buffer layer 200 located in a first preset region and a second preset region on the P-type semiconductor substrate 100, respectively.

[0055] An isolation layer 300 is formed in a portion of the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type semiconductor substrate 100; wherein the isolation layer 300 is in contact with the L-shaped buffer layer 200; a source metal layer 310 is formed in the first via of the isolation layer 300, and the source metal layer 310 is in contact with the P-type heavily doped region 130 and the first N-type heavily doped region 110; a first gate metal layer 320 is formed in the isolation layer 300, and the first gate metal layer 320 is located at the center line position between the first N-type heavily doped region 110 and the second N-type heavily doped region 120.

[0056] A drift layer 410 and a barrier layer 420 are stacked sequentially on an L-shaped buffer layer 200, and the shape of the drift layer 410 is the same as that of the L-shaped buffer layer 200; a cap layer 440 and a second gate metal layer 430 are stacked sequentially on a barrier layer 420, and the cap layer 440 is located between the second gate metal layer 430 and the drift layer 410.

[0057] P-type gallium nitride doped region 510 and N-type gallium nitride doped region 520 are formed on drift layer 410, and N-type gallium nitride doped region 520 is located between P-type gallium nitride doped region 510 and second gate metal layer 430. Contact metal layer 450 is formed on second via on isolation layer 300 and contacts second N-type heavily doped region 120 and barrier layer 420. Drain metal layer 460 is formed on barrier layer 420 and is located on both sides of second gate metal layer 430, respectively, along with contact metal layer 450.

[0058] In this embodiment, a MOS device is formed by forming a first N-type heavily doped region 110, a second N-type heavily doped region 120, a P-type heavily doped region 130, a source metal layer 310, a contact metal layer 450, an isolation layer 300, and a first gate metal layer 320 on a P-type semiconductor substrate 100. A HEMT structure is formed by the contact metal layer 450, drain metal layer 460, drift layer 410, barrier layer 420, capping layer 440, and second gate metal layer 430. P-type and N-type doping are applied between the source metal layer 310 and the second gate metal layer 430. A fast recovery diode is formed in a manner that isolates the fast recovery diode from the active region of the MOS device by an isolation layer 300. A gate resistor is then formed between the fast recovery diode and the isolation layer to link the source metal layer 310 and the second gate metal layer 430. This clamps the link resistor on the gate of the gallium nitride HEMT device based on the fast recovery diode, thereby separating the turn-on and turn-off circuits of the HEMT drive circuit. This ensures the turn-on speed of the HEMT device and eliminates the electromagnetic effect caused by rapid voltage changes, enhancing the performance and stability of the cascode gallium nitride device.

[0059] Specifically, such as Figure 1, Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, in the embodiments of this application, the common-source cascode gallium nitride device is constructed by forming a source-drain connected GaN HEMT and MOS in the region where the dashed line AA' is located, and a resistive region R in the region where the gate of the GaN HEMT and the source (S) of the MOS are connected is formed. H In the region located at the dashed line CC', a fast recovery diode region D with unidirectional conduction characteristics is formed, where the gate of a GaN HEMT is connected to the source of a MOS transistor. H To realize the fast recovery diode-based D-factor on the gate of GaNHEMT H Clamping external gate resistor R H This separates the turn-on and turn-off circuits of the GaN HEMT drive circuit in the GaN cascode, allowing the drive circuit to use a fast recovery diode when the GaN cascode is turned on and a gate resistor when it is turned off. This ensures both the turn-on speed of the GaN cascode and eliminates the EMI effect caused by excessively fast dv / dt.

[0060] In one embodiment, the heavily doped P-type region 130 can be formed by implanting P-type dopant ions (e.g., P-type impurities, aluminum ions, etc.) into the P-type semiconductor substrate 100, and the source metal layer 310 is in contact with the heavily doped P-type region 130.

[0061] In one embodiment, the source metal layer 310, the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type heavily doped region 130 are arranged in parallel.

[0062] In one embodiment, the isolation layer 300 may employ shallow trench isolation (STI) technology to form a shallow trench isolation structure between the first gate metal layer 320 and the drift layer 410, thereby isolating the first gate metal layer 320 from the drift layer 410. In one embodiment, the P-type heavily doped region 130 is adjacent to the first N-type heavily doped region 110.

[0063] In one embodiment, the P-type heavily doped region 130 is in contact with the first N-type heavily doped region 110.

[0064] In one embodiment, the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type heavily doped region 130 have the same thickness.

[0065] In one embodiment, the first N-type heavily doped region 110 and the second N-type heavily doped region 120 have the same doping concentration.

[0066] In one embodiment, the source metal layer 310, the second gate metal layer 430, the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type heavily doped region 130 have the same length.

[0067] In one embodiment, the P-type gallium nitride doped region 510 can be formed by implanting impurity magnesium or magnesium ions into the drift layer 410, and the source metal layer 310 is in contact with the P-type gallium nitride doped region 510.

[0068] In one embodiment, the N-type gallium nitride doped region 520 can be formed by implanting impurity silicon into the drift layer 410.

[0069] In one embodiment, a P-type gallium nitride doped region 510 and an N-type gallium nitride doped region 520 are formed on the drift layer 410, and the N-type gallium nitride doped region 520 is located between the P-type gallium nitride doped region 510 and the second gate metal layer 430, thereby forming a PN junction between the source metal layer 310 and the second gate metal layer 430, forming a fast recovery diode connected between the source metal layer 310 and the second gate metal layer 430.

[0070] In one embodiment, the isolation layer 300 isolates the fast recovery diode from the active region of the MOS device and forms a gate resistor between the fast recovery diode and the isolation layer.

[0071] In one embodiment, both the N-type gallium nitride doped region 520 and the P-type gallium nitride doped region 510 are not in contact with the isolation layer 300.

[0072] In one embodiment, the P-type gallium nitride doped region 510 and the N-type gallium nitride doped region 520 are not in contact with each other.

[0073] In one embodiment, the barrier layer 420 is located on the vertical portion of the drift layer 410, and the N-type gallium nitride doped region 520 and the P-type gallium nitride doped region 510 are located on the horizontal portion of the drift layer 410.

[0074] In one embodiment, the isolation layer 300 may be silicon oxide.

[0075] In one embodiment, the drift layer 410 may be GaN.

[0076] In one embodiment, the barrier layer 420 may be AlGaN.

[0077] In one specific application embodiment, the capping layer 440 can be aluminum oxide.

[0078] This application also provides a method for fabricating a common-source, common-gate gallium nitride device, which is used to fabricate the aforementioned common-source, common-gate gallium nitride device.

[0079] See Figure 6 As shown, the preparation method in this embodiment includes steps S100 to S910.

[0080] In step S100, a first N-type heavily doped region 110, a second N-type heavily doped region 120, and a P-type heavily doped region 130 are formed in a first preset region of the P-type semiconductor substrate 100.

[0081] In this embodiment, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, in the fabrication process of the common-source common-gate gallium nitride device, a first N-type heavily doped region 110, a second N-type heavily doped region 120, and a P-type heavily doped region 130 can be formed in a first preset region of the P-type semiconductor substrate 100.

[0082] For example, a first N-type heavily doped region 110, a second N-type heavily doped region 120, and a P-type heavily doped region 130 can be formed in a first predetermined region of a P-type semiconductor substrate 100 by ion implantation.

[0083] The P-type heavily doped region 130 and the second N-type heavily doped region 120 are located on both sides of the first N-type heavily doped region 110, and the first N-type heavily doped region 110 and the second N-type heavily doped region 120 do not contact each other.

[0084] In one embodiment, the P-type heavily doped region 130 is adjacent to the first N-type heavily doped region 110.

[0085] In one embodiment, the P-type heavily doped region 130 is in contact with the first N-type heavily doped region 110.

[0086] In one embodiment, the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type heavily doped region 130 have the same thickness.

[0087] In one embodiment, the first N-type heavily doped region 110 and the second N-type heavily doped region 120 have the same doping concentration.

[0088] In step S200, an L-shaped buffer layer 200 is formed on the P-type semiconductor substrate 100.

[0089] In this embodiment, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the horizontal portion of the L-shaped buffer layer 200 is located in a first preset region on the P-type semiconductor substrate 100, and the vertical portion of the L-shaped buffer layer 200 is located in a second preset region on the P-type semiconductor substrate 100.

[0090] In step S300, an isolation layer 300 is formed on a portion of the first N-type heavily doped region 110, the second N-type heavily doped region 120, and the P-type semiconductor substrate 100.

[0091] In this embodiment, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the isolation layer 300 is in contact with the L-shaped buffer layer 200. The isolation layer 300 is located on a portion of the P-type semiconductor substrate 100 and is in contact with the L-shaped buffer layer 200.

[0092] In one embodiment, the isolation layer 300 may be silicon oxide.

[0093] In step S400, a source metal layer 310 is formed in the first via of the isolation layer 300.

[0094] For example, a first via is now formed on the isolation layer 300, and then a source metal layer 310 is formed in the first via.

[0095] In this embodiment, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the source metal layer 310 is in contact with the P-type heavily doped region 130 and the first N-type heavily doped region 110.

[0096] In step S500, a first gate metal layer 320 is formed on the isolation layer 300, and an isolation material is formed on the first gate metal layer 320 so that the isolation layer 300 encapsulates the first gate metal layer 320.

[0097] In this embodiment, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the first gate metal layer 320 is located at the center line position between the first N-type heavily doped region 110 and the second N-type heavily doped region 120. The first gate metal layer 320 is wrapped in the isolation layer 300. The first gate metal layer 320 is located at the center line position between the first N-type heavily doped region 110 and the second N-type heavily doped region 120.

[0098] In step S600, a drift layer 410 and a barrier layer 420 are sequentially formed on the L-shaped buffer layer.

[0099] In this embodiment, the shape of the drift layer 410 is the same as that of the L-shaped buffer layer 200.

[0100] In one embodiment, the drift layer 410 may be GaN.

[0101] In one embodiment, the barrier layer 420 may be AlGaN.

[0102] In step S700, a capping layer 440 and a second gate metal layer 430 are formed on the barrier layer 420.

[0103] In this embodiment, combined with Figure 1 and Figure 2 As shown, the capping layer 440 is located between the second gate metal layer 430 and the drift layer 410. The capping layer 440 and the second gate metal layer 430 can be formed on the barrier layer 420, and a portion of the capping layer 440 and the second gate metal layer 430 can be etched away, while the capping layer 440 and the second gate metal layer 430 in the central region of the surface of the barrier layer 420 are retained.

[0104] In one specific application embodiment, the capping layer 440 can be aluminum oxide.

[0105] In step S800, a P-type gallium nitride doped region 510 and an N-type gallium nitride doped region 520 are formed on the drift layer 410.

[0106] In this embodiment, combined with Figure 1 and Figure 2 As shown, the N-type gallium nitride doped region 520 is located between the P-type gallium nitride doped region 510 and the second gate metal layer 430.

[0107] In one embodiment, both the N-type gallium nitride doped region 520 and the P-type gallium nitride doped region 510 are not in contact with the isolation layer 300.

[0108] In one embodiment, the P-type gallium nitride doped region 510 and the N-type gallium nitride doped region 520 are not in contact with each other.

[0109] In one embodiment, the barrier layer 420 is located on the vertical portion of the drift layer 410, and the N-type gallium nitride doped region 520 and the P-type gallium nitride doped region 510 are located on the horizontal portion of the drift layer 410.

[0110] In one embodiment, a P-type gallium nitride doped region 510 and an N-type gallium nitride doped region 520 are formed on the drift layer 410, and the N-type gallium nitride doped region 520 is located between the P-type gallium nitride doped region 510 and the second gate metal layer 430, thereby forming a PN junction between the source metal layer 310 and the second gate metal layer 430, forming a fast recovery diode connected between the source metal layer 310 and the second gate metal layer 430.

[0111] In one embodiment, a P-type gallium nitride doped region 510 can be formed by implanting impurity magnesium or magnesium ions into the drift layer 410.

[0112] In one embodiment, an N-type gallium nitride doped region 520 can be formed by implanting impurity silicon into the drift layer 410.

[0113] In step S900, a contact metal layer 450 is formed in the second through hole on the isolation layer 300.

[0114] In this embodiment, combined with Figure 1 and Figure 2 As shown, the contact metal layer 450 is in contact with the second N-type heavily doped region 120 and the barrier layer 420.

[0115] Combination Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, in one embodiment, the contact metal layer 450 and the drift layer 410 do not contact each other.

[0116] In one embodiment, the contact metal layer 450 and the buffer layer do not contact each other.

[0117] In step S910, a drain metal layer 460 is formed on the barrier layer 420.

[0118] In this embodiment, combined with Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the drain metal layer 460 and the contact metal layer 450 are located on both sides of the second gate metal layer 430. Specifically, the drain metal layer 460 can be formed on the barrier layer 420 by depositing ohmic metal material.

[0119] In one embodiment, the device can also be encapsulated and protected by depositing an insulating dielectric material to form an encapsulation layer, and then the source electrode, drain electrode, and first gate electrode can be led out through contact holes respectively.

[0120] In one embodiment, the isolation layer 300 may employ shallow trench isolation (STI) technology to form a shallow trench isolation structure between the first gate metal layer 320 and the drift layer 410 to isolate the first gate metal layer 320 from the drift layer 410.

[0121] In one embodiment, the isolation layer 300 isolates the fast recovery diode from the active region of the MOS device and forms a gate resistor between the fast recovery diode and the isolation layer for linking the source metal layer 310 and the second gate metal layer 430.

[0122] This application also provides a chip, including a common-source, common-gate gallium nitride device as described in any of the above embodiments.

[0123] In one embodiment, the chip in this embodiment includes a common-source, common-gate gallium nitride device fabricated by the fabrication method of any of the above embodiments.

[0124] The beneficial effects of the embodiments in this application compared with the prior art are:

[0125] A MOS device is formed by forming a first N-type heavily doped region, a second N-type heavily doped region, a P-type heavily doped region, a source metal layer, a contact metal layer, an isolation layer, and a first gate metal layer on a P-type semiconductor substrate. A HEMT structure is formed by the contact metal layer, drain metal layer, drift layer, barrier layer, capping layer, and second gate metal layer. A fast recovery diode is formed between the source metal layer and the second gate metal layer through P-type and N-type doping. An isolation layer isolates the fast recovery diode from the active region of the MOS device. A gate resistor is formed between the fast recovery diode and the isolation layer to connect the source metal layer and the second gate metal layer. This clamps the gate of the gallium nitride HEMT device with a fast recovery diode, achieving the separation of the turn-on and turn-off circuits of the HEMT's drive circuit. This ensures the turn-on speed of the HEMT device and eliminates electromagnetic effects caused by rapid voltage changes, enhancing the performance and stability of the cascode gallium nitride device.

[0126] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A common-source, common-gate gallium nitride device, characterized in that, The common-source, common-gate gallium nitride device includes: P-type semiconductor substrate; A first N-type heavily doped region, a second N-type heavily doped region, and a P-type heavily doped region are respectively formed on a first predetermined region on the P-type semiconductor substrate; wherein, the P-type heavily doped region and the second N-type heavily doped region are located on opposite sides of the first N-type heavily doped region, and the first N-type heavily doped region and the second N-type heavily doped region do not contact each other. An L-shaped buffer layer is formed on the P-type semiconductor substrate, wherein the horizontal portion and the vertical portion of the L-shaped buffer layer are respectively located in the first preset region and the second preset region on the P-type semiconductor substrate; An isolation layer is formed in a portion of the first heavily doped N-type region, the second heavily doped N-type region, and the P-type semiconductor substrate; wherein the isolation layer is in contact with the L-shaped buffer layer; A source metal layer is formed in the first via of the isolation layer and is in contact with the P-type heavily doped region and the first N-type heavily doped region; A first gate metal layer is formed within the isolation layer and is located at the center line position between the first heavily doped N-type region and the second heavily doped N-type region; A drift layer and a barrier layer are stacked sequentially on the L-shaped buffer layer, and the shape of the drift layer is the same as that of the L-shaped buffer layer. A capping layer and a second gate metal layer are sequentially stacked on the barrier layer, with the capping layer located between the second gate metal layer and the drift layer; P-type gallium nitride doped regions and N-type gallium nitride doped regions are formed on the drift layer, and the N-type gallium nitride doped region is located between the P-type gallium nitride doped region and the second gate metal layer; A second via is formed on the isolation layer and contacts the second N-type heavily doped region and the barrier layer; A drain metal layer is formed on the barrier layer and is located on both sides of the second gate metal layer, respectively, along with the contact metal layer.

2. The common-source, common-gate gallium nitride device according to claim 1, characterized in that, The isolation layer is also used to isolate the first gate metal layer from the drift layer.

3. The common-source, common-gate gallium nitride device according to claim 1, characterized in that, The P-type heavily doped region is in contact with the first N-type heavily doped region.

4. The common-source, common-gate gallium nitride device according to claim 3, characterized in that, The source metal layer, the second gate metal layer, the first N-type heavily doped region, the second N-type heavily doped region, and the P-type heavily doped region have the same length; The source metal layer is in contact with the P-type gallium nitride doped region.

5. The common-source, common-gate gallium nitride device according to claim 4, characterized in that, Both the N-type gallium nitride doped region and the P-type gallium nitride doped region are not in contact with the isolation layer.

6. The common-source, common-gate gallium nitride device according to any one of claims 1-5, characterized in that, The P-type gallium nitride doped region and the N-type gallium nitride doped region are not in contact with each other.

7. The common-source, common-gate gallium nitride device according to any one of claims 1-5, characterized in that, The second gate metal layer is not in contact with the N-type gallium nitride doped region.

8. The common-source, common-gate gallium nitride device according to any one of claims 1-5, characterized in that, The barrier layer is located on the vertical portion of the drift layer, and the N-type gallium nitride doped region and the P-type gallium nitride doped region are located on the horizontal portion of the drift layer.

9. A method for fabricating a common-source, common-gate gallium nitride device, characterized in that, The preparation method includes: A first N-type heavily doped region, a second N-type heavily doped region, and a P-type heavily doped region are formed in a first predetermined region of a P-type semiconductor substrate; wherein the P-type heavily doped region and the second N-type heavily doped region are located on opposite sides of the first N-type heavily doped region, and the first N-type heavily doped region and the second N-type heavily doped region do not contact each other; An L-shaped buffer layer is formed on the P-type semiconductor substrate; wherein the horizontal portion and the vertical portion of the L-shaped buffer layer are respectively located in the first preset region and the second preset region on the P-type semiconductor substrate; An isolation layer is formed on a portion of the first N-type heavily doped region, the second N-type heavily doped region, and the P-type semiconductor substrate; wherein the isolation layer is in contact with the L-shaped buffer layer; A source metal layer is formed within the first via of the isolation layer; wherein the source metal layer is in contact with the P-type heavily doped region and the first N-type heavily doped region; A first gate metal layer is formed on the isolation layer, and an isolation material is formed on the first gate metal layer so that the isolation layer encapsulates the first gate metal layer; wherein the first gate metal layer is located at the center line position between the first heavily doped N-type region and the second heavily doped N-type region; A drift layer and a barrier layer are sequentially formed on the L-shaped buffer layer; wherein the shape of the drift layer is the same as the shape of the L-shaped buffer layer. A capping layer and a second gate metal layer are formed on the barrier layer; wherein the capping layer is located between the second gate metal layer and the drift layer; A P-type gallium nitride doped region and an N-type gallium nitride doped region are formed on the drift layer; wherein the N-type gallium nitride doped region is located between the P-type gallium nitride doped region and the second gate metal layer; A second via is formed on the isolation layer to form a contact metal layer; wherein the contact metal layer is in contact with the second N-type heavily doped region and the barrier layer; A drain metal layer is formed on the barrier layer; wherein the drain metal layer and the contact metal layer are located on opposite sides of the second gate metal layer.

10. A chip, characterized in that, Includes the common-source cascode gallium nitride device as described in any one of claims 1-8; or includes the common-source cascode gallium nitride device prepared by the preparation method described in claim 9.

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