Inter-chip delay and on / off detection circuit

Abstract

This invention relates to integrated circuit technology and includes a fixed wide pulse production unit, a detection unit, and a calculation unit. The detection unit comprises an oscillation signal output terminal, a first delay unit, and a second delay unit. The first delay unit includes at least two delay units connected in series at its beginning and end. One series connection point is connected to the oscillation signal output terminal. The end unit is connected to the output terminal of the second delay unit via a second detection interface, and the beginning unit is connected to the output terminal of the second delay unit via the first detection interface. A first switch is provided between the beginning and end of the first delay unit, and a second switch is provided between the input and output terminals of the second delay unit. This invention features low power consumption and a small area.

Description

Technical Field

[0001] This invention relates to integrated circuit technology. Background Technology

[0002] In 2D, 2.5D, and 3D multi-die packaging, the essence is to package the interconnects between dies into a smaller space using technologies such as dielectric layers or micro-solder balls (ubumps).

[0003] At this point, some problems arise: first, whether the interconnects between the chips are reliable and conducting normally; and second, what is the delay of the interconnects between the chips.

[0004] The first problem affects the overall functionality of the chip; the second problem affects the performance between individual chips, especially in some circuits with strict timing requirements, where the uncertainty of delay can lead to many problems.

[0005] If the delay of the interconnects between the chips is known precisely, circuit performance can be optimized through software or hardware compensation.

[0006] Chinese invention patent application CN111983423A provides a chip trace delay built-in detection circuit and detection method. The detection circuit includes a sampling clock circuit, a pulse generation circuit, and a counter. It is only used for internal chip delay detection and cannot determine the abnormality of the detection circuit or the continuity between chips. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a chip-to-chip delay and on / off detection circuit that can accurately detect the on / off state and delay between chips.

[0008] The technical solution adopted by the present invention to solve the aforementioned technical problem is an inter-chip delay and on / off detection circuit, comprising a fixed-width pulse production unit (100), a detection unit (110), and a calculation unit (116). The output terminals of the fixed-width pulse production unit (100) and the detection unit (110) are respectively connected to the calculation unit (116). The detection unit (110) is a ring oscillator, and a detection interface is provided on the loop of the ring oscillator. The detection interface is used to connect the object to be detected to the ring oscillator. The calculation unit is used to calculate the frequency of the output signal of the detection unit based on the pulse width and the output of the detection unit. The invention is characterized in that...

[0009] The detection unit (110) includes an oscillation signal output terminal (d1), a first delay unit (111), and a second delay unit (112).

[0010] The first delay unit (111) includes at least two delay units, each of which is connected in series at the beginning and end. One series connection point is connected to the oscillation signal output terminal (d1). The end is connected to the output terminal of the second delay unit (112) through the second inter-core trace delay circuit (107) accessed by the second detection interface. The beginning is connected to the input terminal of the second delay unit (112) through the first inter-core trace delay circuit (106) accessed by the first detection interface. The first inter-core trace delay circuit (106) and the second inter-core trace delay circuit (107) are the detection objects.

[0011] A first switch (108) is provided between the beginning and end of the first delay unit (111), and a second switch (109) is provided between the input and output of the second delay unit (112).

[0012] Furthermore, at least one delay unit is provided between the input and output of the second delay unit (112).

[0013] The computing unit includes:

[0014] An AND gate (113) has two input terminals as input terminals of the computation unit;

[0015] A k counter, the input of which is connected to the output of an AND gate (113).

[0016] It also includes a data processing unit for calculating the delay and on / off state of the detected object based on the frequency.

[0017] The object of detection is the connection circuit between core particles; more specifically, the object of detection is the connection circuit between stacked core particles, at least two layers deep.

[0018] This invention has a simple structure and achieves the detection of inter-chip delay at minimal cost, and features low power consumption and small area. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of the present invention.

[0020] Figure 2 This is a schematic diagram of the structure of Embodiment 1 of the present invention.

[0021] Figure 3 This is a schematic diagram of the structure of Embodiment 2 of the present invention.

[0022] Figure 4 This is a flowchart of the working algorithm of the present invention. Detailed Implementation

[0023] See Figure 1The detection circuit of the present invention is divided into three parts: a fixed wide pulse production unit (100), a detection unit (110), and a calculation unit (116).

[0024] An external reference clock clk with period T is input to the m counter (101). After m counts by the m counter (101), a clock with period mT is obtained and input to the digital comparator (102).

[0025] The reference threshold of comparator (102) can be set to N.

[0026] When m≤N, the output reset1 of comparator (102) is logic "0"; when m>N, the output reset1 of comparator (102) is logic "1".

[0027] If the reset signal reset1 of the D flip-flop (103) is logic "1", then it will be reset.

[0028] When the output reset1 is logic "0", the D flip-flop (103) works normally; when the output reset1 is logic "1", the D flip-flop (103) enters the reset state.

[0029] The D terminal of the D flip-flop (103) is connected to logic "1". When the enable signal en of the D flip-flop (103) is logic "1" and reset1 is logic "0", the D flip-flop (103) is in normal working state and the output Q is always logic "1".

[0030] At this time, the logic "1" width w of the output Q of the D flip-flop (103) is equal to N reference clock cycles clk.

[0031] The D terminal of the D flip-flop (103) is connected to logic "1". When the enable signal en of the D flip-flop (103) is logic "1" and reset1 is logic "1", the D flip-flop (103) is in the reset state and the output Q is always logic "0".

[0032] Therefore, the fixed pulse width generation module (100) generates a pulse with a fixed time width w, the width of which is equal to N reference clock clk cycles (NT), and the signal output of the fixed time width w pulse is denoted as width.

[0033] The ring oscillator circuit (110) consists of a first delay unit (111), a second delay unit (112), a first inter-core trace delay circuit (106), and a second inter-core trace delay circuit (107).

[0034] The first delay unit (111) consists of multiple inverters (104) with a total delay of dly0.

[0035] The second delay unit (112) consists of multiple inverters (105) with a total delay of dly1.

[0036] The first inter-chip trace delay circuit (106), that is, the trace between TX1 of the first delayer (111) and RX2 of the second delayer (112), has a delay of dly2.

[0037] The second inter-core trace delay circuit (107), that is, the trace between RX1 of the first delayer (111) and TX2 of the second delayer (112), has a delay of dly3.

[0038] The output clock frequency (osc) of the ring oscillator circuit (110) is inversely proportional to the sum of the delays of the first delay unit (111), the second delay unit (112), the first inter-chip trace delay circuit (106), and the second inter-chip trace delay circuit (107). That is:

[0039] (Formula 1)

[0040] Signal SW1 controls the on and off of the first switch (108), and signal SW2 controls the on and off of the second switch (109).

[0041] Specifically, when dly2 and dly3 are equal, and when the SW2 control switch (109) is turned on (i.e., dly1=0), Equation 1 can be simplified to:

[0042] (Formula 2)

[0043] When used to determine whether the detection circuit is working properly, the first switch (108) can also be turned on by controlling SW1, and Formula 2 can be further simplified to:

[0044] (Formula 3)

[0045] The ring oscillator circuit (110) generates a period of The clock signal osc, but the period It is much smaller than the fixed pulse width w.

[0046] The computing unit (116) consists of an AND logic (113), a k counter (114), and a data processing unit (115).

[0047] The AND logic (113) extracts the clock signal osc within the pulse signal width and outputs the signal k as the input of the k counter (114), while the clock signal osc outside the pulse signal width is ignored.

[0048] The k counter (114) counts the clock signal osc within the pulse signal width and uses the counting result as the output t.

[0049] The intuitive meaning of output t is the total number of clock cycles generated by the multi-stage ring oscillator circuit (110) within a fixed time w. ) number.

[0050] Data processing unit (115) executes Figure 4 The detection algorithm can determine the inter-chip delay, whether the continuity detection circuit is normal, whether the inter-chip wiring is properly connected, and the delay value when the connection is normal. Example

[0051] See Figure 2 This embodiment is an example of the present invention used in PCB design and 2D and 2.5D packaging.

[0052] A detection circuit (202) is located inside core 1 (201), in which a switch (203) is listed separately and controlled by a control signal SW1.

[0053] Similarly, another detection circuit (209) is located inside core 2 (208), in which switch (210) is listed separately and controlled by control signal SW2.

[0054] Core 1 (201), core 2 (208) and dielectric layer (205) are connected by ubump or solder ball (204).

[0055] The TX1 of the detection circuit (202) is connected to the RX2 of the detection circuit (209) via the trace (206).

[0056] The RX1 of the detection circuit (202) is connected to the TX2 of the detection circuit (209) via the trace (207).

[0057] The detection circuit (202) includes Figure 1 The fixed wide pulse generator (100), oscillator (111), and computing circuit (115) are included.

[0058] If a modular design is adopted, the detection circuit (209) may also include the same modules as the detection circuit (202), and the two (202 and 209) are symmetrically connected when in use.

[0059] To simplify the circuit, the detection circuit (209) can also include only... Figure 1 The second delay unit (112) in the middle.

[0060] To further simplify the circuit, the second delay unit (112) in the detection circuit (209) can be completely omitted, leaving only the inverter chain. Figure 1 The switch (109) and control signal SW2 are in the middle.

[0061] In special cases, the detection circuit (209) can be completely replaced by a wire directly connected between TX2 and RX2.

[0062] The dielectric layer (205) is the carrier of core 1 (201) and core 2 (208), and also the carrier of other signal interconnects between cores.

[0063] When chip 1 (201) and chip 2 (208) are independently packaged chips, the dielectric layer (205) can be a printed circuit board;

[0064] When chip 1 (201) and chip 2 (208) are 2D packaged chips, the dielectric layer (205) can be the substrate of the chip package;

[0065] When core 1 (201) and core 2 (208) pass through the dielectric layer (interposer), the dielectric layer (205) can be a TSV dielectric layer (TSVInterposer), an Embedded Multi-die Interconnect Bridge (EMIB) dielectric layer, an organic dielectric layer (Organic Interposer), a glass dielectric layer (Glass Interposer), or other dielectric layers.

[0066] The detection circuit (209) in core 2 (208) is not necessary, but is used to facilitate the repeated use of this circuit modular design.

[0067] After omitting the inter-chip delay and on / off detection circuit (209), the switch (210) is closed to conduct, or it is simplified to a looping wire, that is, TX2 and RX2 are directly connected, which has the same effect as the present invention.

[0068] Separate traces (206) and (207) can be added to the detection circuit.

[0069] However, the detection circuit can also reuse the traces (206) and (207) with other interconnections between the chips, and the two are selected by a switch. Example

[0070] See Figure 3In this embodiment, the 3D stacked cores 1 (301), 2 (302), 3 (303), and 4 (304) are connected by ubump solder balls (307) and TSV conductive tubes (306).

[0071] Conductor 308 loops back and connects the TX and RX traces.

[0072] The detection circuit (310) is located inside the core 5 (305), in which the switch (309) is listed separately and controlled by the control signal SW1.

[0073] The 3D stacked core layer shown in this embodiment is 4+1 layers, but the present invention does not limit the number of 3D stacked core layers, so... Figure 2 The 3D stacked chips shown can all use the delay and on / off detection circuit of the present invention.

[0074] Figure 4 This is a flowchart of the algorithm used in this invention to determine the continuity of connections between chips and to calculate the delay between chips. This invention can be enabled or disabled by an enable switch to save power.

[0075] When this circuit (401) is enabled, proceed to step (402).

[0076] m represents the number of times the detection circuit restarts if an abnormality occurs.

[0077] The algorithm flowchart initializes m=3, but it can also be set to other values.

[0078] First, set the control signal SW1 of the switch to 1, which means closing the switch. Then, read the output at this time and proceed to step (403).

[0079] Step (403) determines whether the output is equal to 0. If the output is 0, proceed to step (404).

[0080] Output=0 indicates that no rising edge of the clock was detected within the pulse width W, meaning that the ring oscillator has no frequency output, indicating that there is an abnormality in the detection circuit.

[0081] Step (404) compares whether the value of m is 0, which is used to control the number of times the detection circuit is restarted, so as not to fall into an infinite loop.

[0082] When m is not 0, proceed to step (405);

[0083] When m is 0, proceed to step (411) and end the process.

[0084] Step (405) indicates that there is an abnormality in the detection circuit, so the circuit is restarted and m is set to m-1 to reduce the restart opportunity by one.

[0085] If the output read in step (403) is not 0, the detection circuit is normal, and the process proceeds to step (406).

[0086] Step (406) sets the control signals of the switches SW1=0 and SW2=0, reads the output value and converts it into time t1, and proceeds to step (407).

[0087] exist Figure 2 In the middle, time

[0088] t1 = dly0 + dly1 + dly2 + dly3; (Equation 1)

[0089] in,

[0090] dly0 is the delay of the detection circuit (202);

[0091] dly1 is the delay of the detection circuit (209);

[0092] dly2 is the delay for trace (206);

[0093] dly3 is the delay for the trace (207).

[0094] Step (407) determines whether the output is 0.

[0095] If the output is 0, then jump to step (408), indicating that there is a break in the connection between the cores. Then jump to step (411) and end the process.

[0096] If the output is not 0, then jump to step (409).

[0097] Step (409) First, set the control signals of the switch SW1=0 and SW2=1, read the output value, and convert it into time t2;

[0098] Then set the control signals of the switches SW1=1 and SW2=0, read the output value, and convert it into time t3;

[0099] exist Figure 2 In the middle, time:

[0100] t2 = dly0 + dly2 + dly3; (Equation 2)

[0101] time:

[0102] t3 = dly1 + dly2 + dly3; (Equation 3)

[0103] Proceed to step (410).

[0104] Step (410) can be deduced and calculated based on equations 1, 2, and 3:

[0105] dly2 + dly3 = t2 + t3 - t1, (Equation 4)

[0106] That is, the total delay of the trace between the two cores;

[0107] If, when designing traces (206) and (207), the trace lengths and positions are specifically designed to be basically equal, i.e., using differential trace matching, then dly2 = dly3 can be considered. In this case, we have:

[0108] dly2=dly3=(t2+t3-t1) / 2, (Equation 5)

[0109] This yields the accurate delay value for the single-sided trace between the core particles.

Claims

1. A chip-to-chip delay and on / off detection circuit, comprising a fixed-width pulse production unit (100), a detection unit (110), and a calculation unit (116), wherein the output terminals of the fixed-width pulse production unit (100) and the detection unit (110) are respectively connected to the calculation unit (116); the detection unit (110) is a ring oscillator, and a detection interface is provided on the loop of the ring oscillator, the detection interface being used to connect the object to be detected to the ring oscillator; the calculation unit is used to calculate the frequency of the output signal of the detection unit based on the pulse width and the output of the detection unit; characterized in that, The detection unit (110) includes an oscillation signal output terminal (d1), a first delay unit (111), and a second delay unit (112). The first delay unit (111) includes at least two delay units, each of which is connected in series at the beginning and end. One series connection point is connected to the oscillation signal output terminal (d1). The end is connected to the output terminal of the second delay unit (112) through the second inter-core trace delay circuit (107) accessed by the second detection interface. The beginning is connected to the input terminal of the second delay unit (112) through the first inter-core trace delay circuit (106) accessed by the first detection interface. The first inter-core trace delay circuit (106) and the second inter-core trace delay circuit (107) are the detection objects. A first switch (108) is provided between the beginning and end of the first delay unit (111), and a second switch (109) is provided between the input and output of the second delay unit (112).

2. The inter-chip delay and on / off detection circuit as described in claim 1, characterized in that, At least one delay unit is also provided between the input and output of the second delay unit (112).

3. The inter-chip delay and on / off detection circuit as described in claim 1, characterized in that, The computing unit includes: An AND gate (113) has two input terminals as input terminals of the computation unit; A k counter, the input of which is connected to the output of an AND gate (113).

4. The inter-chip delay and on / off detection circuit as described in claim 1 or claim 2, characterized in that, The calculation unit (116) further includes a data processing unit for calculating the delay and on / off state of the detected object based on the frequency.

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