Display substrate and display panel

Abstract

A display substrate and a display panel belong to the field of display technology. The display substrate disclosed in the present invention comprises: a base substrate (10), a plurality of gate lines (GL), a plurality of data lines (DL), and a plurality of sub-pixels (P) arranged on the base substrate (10); the plurality of sub-pixels (P) form a plurality of first pixel groups (P10) arranged side by side along a first direction (X) and a plurality of second pixel groups (P20) arranged side by side along a second direction (Y); a first region (Q11) is defined between any two adjacent first pixel groups (P10), and a second region (Q12) is defined between any two adjacent second pixel groups (P20). A second area (Q12); a common electrode line (CL) is also arranged in at least part of the first area (Q11), and the common electrode line (CL) and the data line (DL) are located in different first areas (Q11); the common electrode line (CL) includes a plurality of common electrode line segments (101), and a boss (102) connected between two common electrode line segments (101), and the width of the boss (102) in any direction is greater than the width of the common electrode line segment (101) in the first direction (X); the boss (102) is located in the second area (Q12).

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display panel. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) is an important flat panel display device. With the development of display technology, high resolution, high transmittance, large size, low power consumption and low cost have become the development direction of the future display field. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a display substrate and a display panel.

[0004] The embodiment of the present disclosure provides a display substrate, which includes: a base substrate, a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels arranged on the base substrate; the plurality of sub-pixels form a plurality of first pixel groups arranged side by side along a first direction and a plurality of second pixel groups arranged side by side along a second direction; each of the plurality of first pixel groups includes a plurality of sub-pixels arranged side by side along the second direction; each of the plurality of second pixels includes a plurality of sub-pixels arranged side by side along the first direction; a gate line is respectively arranged on both sides of each second pixel group in the second direction; for two adjacent sub-pixels in any of the second pixel groups, the gate line connected to one of them is located at the The gate line connected to one of the two sides of the sub-pixel in the second direction is located on the other side of the two sides of the sub-pixel in the second direction; each of the sub-pixels in every two adjacent first pixel groups is connected to the same data line, and each of the sub-pixels connected to the same data line is connected to different gate lines; wherein a first area is defined between any two adjacent first pixel groups, and a second area is defined between any two adjacent second pixel groups; a common electrode line is further provided in at least part of the first area, and the common electrode line and the data line are located in different first areas;

[0005] The common electrode line includes a plurality of common electrode line segments and a boss connected between two of the common electrode line segments, and the width of the boss in any direction is greater than the width of the common electrode line segment in the first direction; the boss is located in the second area.

[0006] Wherein, a thin film transistor and a pixel electrode are arranged in the sub-pixel; the gate of the thin film transistor is connected to the gate line, the source is connected to the data line, and the drain is connected to the pixel electrode;

[0007] The pixel electrodes in the same second pixel group constitute a pixel electrode group, and the thin film transistors in any two adjacent sub-pixels in the same second pixel group are respectively located at two opposite sides of the pixel electrode group in the second direction.

[0008] Among them, for any two thin film transistors connected to the same data line and located in sub-pixels of two adjacent first pixel groups, the connection node between one of them and the data line is a first node, and the connection node between the other and the data line is a second node. With the midpoint of the first node and the second node as the center of symmetry, the two thin film transistors are centrally symmetrical.

[0009] Among them, the data line includes multiple data line segments, and a connecting line segment connecting two adjacent data line segments; the connecting line segment includes a first sub-connecting line segment and a second sub-connecting line, the first sub-connecting line is connected to the data line segment through the second sub-connecting line segment; the first sub-connecting line segment is located in the second area; the source of the thin film transistor is connected to the first sub-connecting line segment; the angle between the extension direction of the data line segment and the first direction is 5° to 10°; the angle formed by the second sub-connecting line segment and the data line segment is 100° to 130°.

[0010] A common electrode is also provided in the pixel area; one of the pixel electrode and the common electrode is a slit electrode, and the other is a plate electrode; the extension direction of the slit of the slit electrode is the same as the extension direction of the data line segment.

[0011] Wherein, the extension direction of the common electrode line segment is the same as the extension direction of the data line segment.

[0012] Wherein, the display substrate comprises a first metal layer arranged on the base substrate; the first metal layer comprises the data line, the common electrode line, and the source and drain of the thin film transistor.

[0013] Wherein, the display substrate comprises a second metal layer arranged on the base substrate; the second metal layer comprises the gate line and the gate of the thin film transistor.

[0014] The display substrate includes a second metal layer, a first interlayer insulating layer, a semiconductor layer, a first transparent conductive layer, a first metal layer, a second interlayer insulating layer, and a second transparent conductive layer, which are sequentially arranged in a direction away from the base substrate;

[0015] The first metal layer includes the data line, the common electrode line, the source and drain of the thin film transistor;

[0016] The second metal layer includes the gate line and the gate of the thin film transistor;

[0017] The first transparent conductive layer includes the pixel electrode;

[0018] The second transparent conductive layer includes a common electrode.

[0019] Wherein, the data lines and the common electrode lines are alternately arranged in the first direction.

[0020] Wherein, the orthographic projection of the gate of the thin film transistor on the base substrate covers the orthographic projection of the semiconductor active layer on the base substrate; Wherein,

[0021] The orthographic projection of the gate on the base substrate includes a first side and a second side that are oppositely arranged along the first direction, and a third side and a fourth side that are oppositely arranged along the second direction; the orthographic projection of the semiconductor active layer on the base substrate includes a fifth side and a sixth side that are oppositely arranged along the first direction, and a seventh side and an eighth side that are oppositely arranged along the second direction;

[0022] The fourth side is connected to the orthographic projection of the gate line on the substrate;

[0023] The first side is opposite to the fifth side, and the distance between them is S1; the second side is opposite to the sixth side, and the distance between them is S2; the third side is opposite to the seventh side, and the distance between them is S3; at least one of S1, S2, and S3 is less than 3μm. The width of any of the bosses in any direction is greater than the width of the common electrode line segment in the first direction; and the bosses have the same size.

[0024] An embodiment of the present disclosure provides a display panel, which includes the above-mentioned display substrate.

[0025] The display panel further comprises an opposing substrate arranged opposite to the display substrate, and a spacer located between the display substrate and the opposing substrate; an orthographic projection of one of the spacers on the base substrate is located within an orthographic projection of one of the bosses on the base substrate.

[0026] The spacer includes a first spacer and a second spacer; the height of the first spacer is greater than the height of the second spacer; and two ends of the first spacer are respectively against the display substrate and the counter substrate.

[0027] The first spacers and the second spacers are evenly arranged in the display panel, and the ratio of the arrangement density of the first spacers to the arrangement density of the second spacers is 1:30 to 1:70. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional view of an exemplary display panel.

[0029] Figure 2 for Figure 1 A top view of an array substrate in a display panel.

[0030] Figure 3 for Figure 2 The layout of the array substrate is shown.

[0031] Figure 4 for Figure 2 Equivalent circuit diagram of a sub-pixel in an array substrate.

[0032] Figure 5 This is a layout of an array substrate according to an embodiment of the present disclosure.

[0033] Figure 6 Schematic diagram of common electrode lines in an array substrate according to an embodiment of the present disclosure.

[0034] Figure 7 The figure is a schematic diagram of a display panel using the array substrate according to an embodiment of the present disclosure.

[0035] Figure 8 Schematic diagram of data lines in an array substrate according to an embodiment of the present disclosure.

[0036] Fig. 9 This is the layout of the second metal layer in the array substrate of the embodiment of the present disclosure.

[0037] Fig.10 This is a layout of the semiconductor layer in the array substrate of the embodiment of the present disclosure.

[0038] Fig.11 The invention relates to a layout for forming a semiconductor layer on a base substrate on which a first insulating layer is formed.

[0039] Fig.12 This is the layout of the first transparent conductive layer in the array substrate of the embodiment of the present disclosure.

[0040] Fig.13 This is the layout of the first metal layer in the array substrate of the embodiment of the present disclosure.

[0041] Fig.14 The invention is a layout for forming a first metal layer on a base substrate for forming a first transparent conductive layer.

[0042] Fig.15 This is the layout of the second transparent conductive layer in the array substrate of the embodiment of the present disclosure.

[0043] Fig.16 Schematic diagram of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] Figure 1 is a cross-sectional view of an exemplary display panel; Figure 1As shown, the display panel includes a display substrate and an opposing substrate arranged opposite to each other, and a liquid crystal layer arranged between the display substrate and the opposing substrate. The display substrate and the opposing substrate are matched (i.e., a liquid crystal box is formed) by a sealing glue arranged in the peripheral area Q2, and the matching of the liquid crystal box is maintained by a spacer PS arranged in the display area Q1. Among them, the display substrate can be an array substrate, and the opposing substrate can be a color filter substrate; of course, the display substrate can also be a COA (Color On Array; the color filter layer is arranged on the array substrate) substrate, in which case the color filter layer will not be arranged on the opposing substrate. In the disclosed embodiment, the display substrate is an array substrate, and the opposing substrate is a color filter substrate as an example for explanation. Among them, the array substrate includes a base substrate 10, and sub-pixels are arranged on the base substrate 10. The sub-pixels include a thin film transistor TFT, a pixel electrode 12 and a common electrode 14, wherein a first interlayer insulating layer 11 is arranged between the gate of the thin film transistor TFT and the semiconductor active layer, and a second interlayer insulating layer 12 is arranged between the layer where the source and drain of the thin film transistor TFT are located and the layer where the common electrode is located. The color filter substrate includes a base substrate 10' and a color filter layer disposed on the base substrate 10'. The color filter layer includes a color filter and a black matrix. The black matrix BM is used for shielding and is disposed corresponding to the position of the non-light-transmitting element such as the thin film transistor TFT on the array substrate. The color filter is used for color display and corresponds to the position of the pixel electrode 12. Figure 1 Only the red filter R is illustrated in the figure, and the actual display panel may also include a green filter and a blue filter, so as to realize color display of the display panel.

[0047] Figure 2 for Figure 1 A top view of an array substrate in a display panel; Figure 3 for Figure 2 The layout of the array substrate shown in FIG. Figure 2 and 3As shown, the array substrate is a dual gate array substrate, which may include a substrate 10, and a plurality of sub-pixels P arranged on the substrate 10; the sub-pixels P on the substrate 10 form a plurality of first pixel groups P10 arranged side by side along a first direction X and a plurality of second pixel groups P20 arranged side by side along a second direction Y; each first pixel group P10 includes a plurality of sub-pixels P arranged side by side along the second direction Y; each second pixel group P20 includes a plurality of sub-pixels P arranged side by side along the first direction X. A gate line GL is respectively arranged on both sides of each second sub-pixel P group in the second direction Y. For two adjacent sub-pixels P in any second pixel group P20, the gate line GL connected to one of them is located on one side of the two opposite sides of the sub-pixel P in the second direction Y, and the gate line GL connected to the other is located on the other side of the two opposite sides of the sub-pixel P in the second direction Y; each sub-pixel P in each two adjacent first pixel groups P10 is connected to the same data line DL, and each sub-pixel P connected to the same data line DL is connected to different gate lines GL.

[0048] Figure 4 for Figure 2 An equivalent circuit diagram of a sub-pixel in an array substrate; Figure 3 As shown, the equivalent circuit includes a thin film transistor TFT, a storage capacitor Cst, and a liquid crystal capacitor Clc; the first electrode of the thin film transistor TFT is connected to the data line DL, the second electrode of the thin film transistor TFT is connected to the first electrode plate of the storage capacitor Cst and the first electrode plate of the liquid crystal capacitor Clc, and the control electrode of the thin film transistor TFT is connected to the gate line GL; the second electrode plate of the storage capacitor Cst is connected to the reference voltage terminal Vref; the second electrode plate of the liquid crystal capacitor Clc is connected to the common voltage signal. When the gate line GL is written with a working level signal, the thin film transistor TFT is selected, and the display of the corresponding gray scale is realized through the data line DL voltage signal written on the data line DL.

[0049] In addition, the transistors used in the embodiments of the present disclosure may be thin film transistors TFT or field effect transistors or other switching devices with the same characteristics, and the thin film transistors TFT may include oxide semiconductor thin film transistors TFT, amorphous silicon thin film transistors TFT or polycrystalline silicon thin film transistors TFT, etc. For each transistor, it includes a first electrode, a second electrode and a control electrode; wherein the control electrode serves as the gate of the transistor, one of the first electrode and the second electrode serves as the source of the transistor, and the other serves as the drain of the transistor; and the source and drain of the transistor may be symmetrical in structure, so the source and drain thereof may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate serving as the control electrode, the first electrode is directly described as the source and the second electrode is the drain, so the source and drain of all or part of the transistors in the embodiments of the present disclosure may be interchangeable as needed.

[0050] Figure 3 for Figure 2 The layout of the array substrate shown; combined Figure 1 and 3 As shown, the array substrate includes a base substrate 10, a second metal layer 20, a first interlayer insulating layer 11, a semiconductor layer 30, a first transparent conductive layer 40, a first metal layer 50, a second interlayer dielectric layer and a second transparent conductive layer 60 which are sequentially arranged on the base substrate 10. The second metal layer 20 includes a gate line GL and a gate of a thin film transistor TFT in each sub-pixel P, and the gate of the thin film transistor TFT in each sub-pixel P in the same second pixel and the gate line GL connected thereto are an integrally formed structure. The semiconductor layer 30 includes a semiconductor active layer of a thin film transistor TFT in each sub-pixel P, and the semiconductor active layer in each thin film transistor TFT and its gate have at least partially overlapped orthographic projections on the base substrate 10. The first transparent electrode layer includes a pixel electrode 12 in each sub-pixel P. The second metal layer 20 includes a data line DL, a common electrode line CL, and a source and a drain of a thin film transistor TFT in each sub-pixel P. The drain of each thin film transistor TFT is overlapped with the pixel electrode 12; the data line DL and the source of each thin film transistor TFT connected thereto are an integral structure. The second transparent electrode layer includes a common electrode 14 in each sub-pixel P. Since the common electrode 14 is located on the side of the pixel electrode 12 away from the base substrate 10, the common electrode 14 is a slit electrode.

[0051] Continuing with reference to 4, the thin film transistor TFT in the sub-pixel P in the second pixel group P20 connected to the same data line DL and adjacently arranged is located between the two gate lines GL between the two adjacent second pixel groups P20. When the array substrate is applied to the display panel, the spacer is located exactly at the position corresponding to the thin film transistor TFT, and the end of the slit of the slit electrode has a corner. When the number of pixels per inch (English: Pixels Per Inch; abbreviated: PPI) reaches more than 300, that is, the size of the sub-pixel P is less than or equal to 25.6μm, according to Figure 4 The pixel layout design will reduce the aperture ratio by more than 6% compared to conventional display panels.

[0052] Figure 5 A layout of an array substrate according to an embodiment of the present disclosure; Figure 6 is a schematic diagram of a common electrode line in an array substrate according to an embodiment of the present disclosure; Figure 5 and 6 As shown, the embodiment of the present disclosure provides an array substrate and Figure 1 The array substrate shown is similar to a dual-gate array substrate, which may specifically include a base substrate 10, on which a plurality of sub-pixels P, a plurality of gate lines GL, and a plurality of data lines DL are arranged. The sub-pixels P are arranged as shown in FIG. Figure 2As shown, a plurality of sub-pixels P form a plurality of first pixel groups P10 arranged side by side along a first direction X, and a plurality of second pixel groups P20 arranged side by side along a second direction Y. Each first pixel group P10 includes a plurality of sub-pixels P arranged side by side along the second direction Y; each second pixel group P20 includes a plurality of sub-pixels P arranged side by side along the first direction X. A gate line GL is respectively arranged on both sides of each second pixel group P20 in the second direction Y, and two gate lines GL are arranged between any two adjacent second pixel groups P20. For two adjacent sub-pixels P in any second pixel group P20, the gate line GL connected to one of them is located on one of the two opposite sides of the sub-pixel P in the second direction Y, and the gate line GL connected to the other is located on the other side of the two opposite sides of the sub-pixel P in the second direction Y; each sub-pixel P in every two adjacent first pixel groups P10 is connected to the same data line DL, and each sub-pixel P connected to the same data line DL is connected to different gate lines GL; wherein, a first area Q11 is defined between any two adjacent first pixel groups P10, and a second area Q12 is defined between any two adjacent second pixel groups P20; a common electrode line CL is also provided in at least part of the first area Q11, and the common electrode line CL and the data line DL are located in different first areas Q11; that is, if the data line DL is provided between two adjacent first pixel groups P10, then the common electrode line CL is no longer provided between the two adjacent first pixel groups P10. In the embodiment of the present disclosure, the common electrode line CL includes a plurality of common electrode line segments 101 and a boss 102 connected between two common electrode line segments 101, and the width of at least one boss 102 in any direction is greater than the width of the common electrode line segment 101 in the first direction X; the boss 102 is located in the second area Q12.

[0053] It should be noted that Figure 7 is a schematic diagram of a display panel using an array substrate according to an embodiment of the present disclosure; Figure 7 As shown, the display panel includes an array substrate 200 and a color filter substrate 300 arranged opposite to each other, and a spacer arranged between the two. The array substrate 200 is the array substrate in the embodiment of the present disclosure. Figure 7It is only an exemplary figure, and does not illustrate the specific structure of each film layer. When the array substrate in the embodiment of the present disclosure is applied to the display panel, the spacer PS that maintains the box thickness of the display panel and the boss whose width in any direction is greater than the width of the common electrode line segment 101 in the first direction X are arranged correspondingly, that is, the orthographic projection of a spacer on the base substrate 10 is located within the orthographic projection of a boss 102 on the base substrate 10. Usually, the spacer PS in the display panel is divided into a first spacer PS1 and a second spacer PS2, wherein the first spacer PS1 is higher than the second spacer PS2, and the orthographic projection area of ​​the first spacer PS1 on the base substrate 10 is greater than the orthographic projection area of ​​the second spacer PS2 on the base substrate 10. At this time, the first spacer PS1 is used as the main spacer to maintain the box thickness of the display panel; the second spacer PS2 is used as the auxiliary spacer to play a buffering role when an external force acts on the display panel. In the embodiment of the present disclosure, by forming the boss 102 on the common electrode line CL and disposing the spacer at the position corresponding to the boss 102 , the problem of uneven aperture ratio of each sub-pixel P due to different sizes of the spacer can be effectively avoided.

[0054] In some examples, continue to refer to Figure 6 The shape of the boss 102 can be any shape such as polygon, circle, ellipse, etc., and the shape of the boss 102 is not limited in the embodiment of the present disclosure. Figure 6 In the figure, only the boss 102 is taken as an example that the boss 102 is a circular boss 102 .

[0055] In some examples, the width of all the bosses 102 on any common electrode line CL in any direction is greater than the width of the common electrode line segment 101 in the first direction X. Furthermore, all the bosses 102 have the same size. In this case, when the common electrode line CL is made of non-light-transmitting material, that is, the bosses 102 are non-light-transmitting areas, the aperture ratio of the display substrate can be ensured to be consistent, thereby improving display uniformity. In the embodiments of the present disclosure, the consistent size of each boss 102 is used as an example for explanation, but this does not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0056] In some examples, continue to refer to Figure 5 , a thin film transistor TFT and a pixel electrode 12 are arranged in each sub-pixel P, the gate of the thin film transistor TFT is connected to the gate line GL, the source of the thin film transistor TFT is connected to the data line DL, and the drain of the thin film transistor TFT is connected to the pixel electrode 12. In the same way, each pixel electrode 12 in any second pixel group P20 constitutes a pixel electrode group, and the thin film transistors TFT in any two adjacent sub-pixels P in the same second pixel group P20 are respectively located at two opposite sides of the pixel electrode group in the second direction Y. For example: Figure 5As shown, for any two adjacent thin film transistors TFT in the same second pixel group P20, one is located on the upper side of the pixel electrode group, and the other is located on the lower side. Figure 5 It can be seen that the thin film transistor TFT in each sub-pixel P is located on the side of the gate line GL close to the pixel electrode 12, so compared with Figure 2 In the array substrate shown, the distance between two thin film transistors TFT located in the adjacent second pixel group P20 and connected to the same data line DL is enlarged, so the risk of short circuit between the source and drain of the two thin film transistors TFT can be effectively reduced.

[0057] Of course, each sub-pixel P includes not only a pixel electrode 12 but also a common electrode 14. When the pixel electrode 12 is arranged closer to the side of the substrate 10 than the common electrode 14, the pixel electrode 12 is a plate-shaped electrode and the common electrode 14 is a slit electrode; when the common electrode 14 is arranged closer to the side of the substrate 10 than the pixel electrode 12, the common electrode 14 is a plate-shaped electrode and the pixel electrode 12 is a slit electrode. In the following description of the embodiments of the present disclosure, the pixel electrode 12 is a plate-shaped electrode and the common electrode 14 is a slit electrode as an example, but this does not constitute a limitation on the protection scope of the embodiments of the present disclosure. Furthermore, the extension direction of the slits in each common electrode 14 is a single direction, that is, there are no corners at both ends of each slit, and this method is used to ensure that the aperture ratio of each sub-pixel P is uniform. For example: the extension direction of the slit is substantially the same as, or even completely consistent with, the extension direction of the common electrode line segment 101. The extending direction of the slits is substantially the same as the extending direction of the common electrode line segment 101, which means that the angle between the extending directions of the two and the first direction X is within 5°. Of course, each slit may not be a straight opening, but may be a zigzag opening. The opening direction of the slits does not constitute a limitation on the protection scope of the embodiments of the present disclosure.

[0058] In some examples, continue to refer to Figure 5In the array substrate, the thin film transistors TFT connected to the same data line DL and located in the sub-pixels P of the two adjacent first pixel groups P10 are centrally symmetrical. That is to say, for any two thin film transistors TFT connected to the same data line and located in the sub-pixels P of the two adjacent first pixel groups P10, the connection node of one of them with the data line DL is the first node a, and the connection node of the other with the data line DL is the second node b. With the midpoint c of the first node a and the second node b as the symmetry center, the two thin film transistors TFT are centrally symmetrical. For example: two thin film transistors TFT connected to the same data line DL and located in diagonal positions are centrally symmetrical. Of course, in the sub-pixels P connected to the same data line DL and located in the two adjacent first pixel groups P10, not only the thin film transistors TFT are centrally symmetrical, but also the pixel electrodes 12 and the common electrodes 14 are centrally symmetrical. This setting method is used to ensure the consistency of the aperture ratio of each sub-pixel P.

[0059] In some examples, Figure 8 is a schematic diagram of a data line in an array substrate according to an embodiment of the present disclosure; Figure 8As shown, any data line DL includes a plurality of data line segments 201 and a connecting line segment 202 connecting two adjacent data line segments 201. The connecting line segment 202 includes a first sub-connecting line segment 202a and two second sub-connecting line segments 202b. The two ends of the first sub-connecting line segment 202a are respectively connected to a second sub-connecting line segment 202b, and the data line segment 201 is connected through the second sub-connecting line segment 202b. The data line segment 201 is located in the first area Q11, the first sub-connecting line segment 202a is located in the second area Q12, and the second sub-connecting line segment 202b can be located in the first area Q11 or in the second area Q12, or can be partially located in the first area Q11 and partially located in the second area Q12. The extension lines of the data line segments 201 located in odd numbers overlap, and the extension lines of the data line segments 201 located in even numbers overlap, and the extension lines of the data line segments 201 located in odd numbers are parallel to the extension lines of the data line segments 201 located in even numbers. The source of the thin film transistor TFT in each sub-pixel P is connected to the first sub-connection line segment 202a, and the angle between the extension direction of the data line segment 201 and the second direction Y is about 5° to 10°; the angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is about 100° to 130°. For example: when the angle between the extension direction of the data line segment 201 and the second direction Y is 10°, the angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 125°. For another example: when the angle between the extension direction of the data line segment 201 and the second direction Y is 5°, the angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 130°. For another example: when the angle between the extension direction of the data line segment 201 and the second direction Y is 7°, the angle θ formed by the second sub-connection line segment 202b and the data line segment 201 connected thereto is 132°. That is, the data line DL has a corner at the position where the thin film transistor TFT is connected, and this arrangement can increase the opening of each sub-pixel P. In the embodiment of the present disclosure, the angle between the extension direction of the data line segment 201 and the second direction Y is preferably 10°, and the angle θ formed by the second sub-connecting line segment 202b and the data line segment 201 connected thereto is 125°. It has been experimentally verified that when the angle between the extension direction of the data line segment 201 and the second direction Y is 10°, and the angle θ formed by the second sub-connecting line segment 202b and the data line segment 201 connected thereto is 125°, compared with the angle between the extension direction of the data line segment 201 and the second direction Y being 5°, the pixel aperture ratio when the angle θ formed by the second sub-connecting line segment 202b and the data line segment 201 connected thereto is 130° can be increased by 2.29%; compared with the angle between the extension direction of the data line segment 201 and the second direction Y being 7°, the pixel aperture ratio when the angle θ formed by the second sub-connecting line segment 202b and the data line segment 201 connected thereto is 130° can be increased by 1.76%.

[0060] Furthermore, the data lines DL and the common electrode lines CL are arranged alternately, and the extension direction of the data line segments 201 and the common electrode line segments 101 is the same. That is, one of the adjacent first regions Q11 is provided with the data lines DL, and the other is provided with the common electrode lines CL. In this way, the arrangement of the sub-pixels P in the array substrate can be regular, so that the transmittance of each sub-pixel P can be guaranteed to be uniform.

[0061] In some examples, the array substrate in the embodiment of the present disclosure may include a first metal layer 50, which includes common electrode lines CL and data lines DL, and the source and drain of the thin film transistor TFT; that is, the common electrode lines CL and data lines DL in the array substrate, and the source and drain of the thin film transistor TFT are arranged in the same layer and made of the same material. In this case, a pattern including the common electrode lines CL and data lines DL, and the source and drain of the thin film transistor TFT can be formed by a single patterning process. Among them, since the source of each thin film transistor TFT needs to be connected to the data line DL, the source of the thin film transistor TFT can be an integrated structure with the data line DL connected thereto.

[0062] In some examples, the array substrate in the embodiment of the present disclosure may include a second metal layer 20, and the second metal layer 20 includes a gate line GL and a gate of each thin film transistor TFT. In this case, a pattern including the gate line GL and the gate of each thin film transistor TFT can be formed by a single patterning process. Since the gate of each thin film transistor TFT needs to be connected to the gate line GL, the gate of the thin film transistor TFT can be integrally formed with the gate line GL connected thereto.

[0063] In order to make the array substrate structure in the embodiment of the present disclosure clearer, the following Figure 5 ,as well as Figure 5 The layout of each film layer of the array substrate shown is a detailed description of the array substrate in the embodiment of the present disclosure.

[0064] like Figure 5 As shown, the array substrate includes: a base substrate 10, a plurality of sub-pixels P arranged on the base substrate 10, a plurality of gate lines GL and a plurality of data lines DL. A thin film transistor TFT, a pixel electrode 12 and a common electrode 14 are arranged in each sub-pixel P. From the perspective of film layers, the array substrate includes a base substrate 10, a second metal layer 20, a first interlayer insulating layer 11, a semiconductor layer 30, a first transparent conductive layer 40, a first metal layer 50, a second interlayer insulating layer 13 and a second transparent conductive layer 60 are sequentially arranged on the base substrate 10. Next, the structure of each film layer is described.

[0065] Fig. 9is the layout of the second metal layer in the array substrate of the embodiment of the present disclosure; Fig. 9 As shown, the second metal layer 20 includes a gate line GL and a gate of a thin film transistor TFT in each sub-pixel P, and the gate line GL and the gate 301 of each thin film transistor TFT connected thereto are an integrally formed structure. In some examples, the material of the second metal layer 20 includes but is not limited to molybdenum Mo, molybdenum-niobium alloy, aluminum Al, aluminum-neodymium alloy, titanium Ti or copper Gu and other conductive materials to form the second metal layer 20, which can be a single-layer structure or a multi-layer structure, such as a Ti / Al / Ti three-layer structure.

[0066] In some examples, the first interlayer insulating layer 11 is used as a gate insulating layer and is disposed between the gate of each thin film transistor TFT and the semiconductor active layer. The material of the first interlayer insulating layer 11 can be made of a material similar to the lattice structure of Si, such as SixNy or SixOy: silicon nitride or silicon oxide. Specifically, it can be a single-layer structure of silicon nitride or silicon oxide, and of course, a composite film layer structure of silicon nitride or silicon oxide can also be used.

[0067] Fig.10 is a layout of the semiconductor layer in the array substrate of the embodiment of the present disclosure; Fig.10 As shown, the semiconductor layer 30 includes a semiconductor active layer 302 of the thin film transistor TFT in each sub-pixel P. Among them, the semiconductor active layer 302 includes an active layer pattern (channel region) and a doping region pattern (source-drain doping region) of the thin film transistor TFT of each sub-pixel P. For example, the semiconductor layer 30 can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities. Of course, the material of the semiconductor layer 30 can also include oxide semiconductors, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO) or gallium zinc oxide (GZO), etc. In the embodiment disclosed in the present invention, the material of the semiconductor layer 30 is low-temperature polycrystalline silicon as an example for explanation. Fig.11 A layout for forming a semiconductor layer on a substrate substrate on which a first insulating layer is formed; Fig.11As shown, the orthographic projections of a semiconductor active layer and a gate on the substrate 10 overlap. In the embodiment of the present disclosure, the orthographic projection of the gate of the thin film transistor on the substrate covers the orthographic projection of the active layer on the substrate; wherein, the orthographic projection of the gate on the substrate includes a first side (left) and a second side (right) arranged opposite to each other along a first direction, and a third side (upper) and a fourth side (lower) arranged opposite to each other along a second direction; the orthographic projection of the semiconductor active layer on the substrate includes a fifth side (left) and a sixth side (right) arranged opposite to each other along the first direction, and a seventh side (upper) and an eighth side (lower) arranged opposite to each other along the second direction; the fourth side (lower) of the gate is connected to the orthographic projection of the gate line on the substrate (that is, the gate of the thin film transistor and the gate line connected thereto are an integral structure); the first side of the gate is opposite to the fifth side of the semiconductor active layer, and the spacing therebetween is S1; the second side of the gate is opposite to the sixth side of the semiconductor active layer, and the spacing therebetween is S2; the third side of the gate is opposite to the seventh side of the semiconductor active layer, and the spacing therebetween is S3; at least one of S1, S2, and S3 is less than 3μm. In some examples, S1=S2=S3=2.75μm. However, it should be understood that the values ​​of S1, S2, and S3 can be specifically set according to the display panel size and the pixel aperture ratio requirements. In the disclosed embodiment, at least one of S1, S2, and S3 is less than 3μm, which helps the display panel to achieve a high PPI design and can increase the pixel aperture ratio. When S1=S2=S3=2.75μm, the pixel aperture ratio can be increased by more than 6.5%.

[0068] Fig.12 is a layout of the first transparent conductive layer in the array substrate of the embodiment of the present disclosure; Fig.10 As shown, the first transparent conductive layer 40 includes a pixel electrode 12 in each sub-pixel P. In some examples, the material of the first transparent conductive layer 40 includes a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0069] Fig.13 is a layout of the first metal layer in the array substrate of the embodiment of the present disclosure; Fig.14 A layout for forming a first metal layer on a base substrate on which a first transparent conductive layer is formed; Fig.13 and 14As shown, the first metal layer 50 includes a data line DL, a common electrode line CL, and a source and a drain 303 of a thin film transistor TFT in each sub-pixel P. The source of each thin film transistor TFT and the data line DL connected thereto are an integrally formed structure, the source and the drain 303 of the thin film transistor TFT are respectively connected to the source region and the drain region of the semiconductor active layer, and the drain 303 of the thin film transistor TFT is also electrically connected to the pixel electrode 12. In some examples, the first metal layer 50 includes but is not limited to a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack, such as a three-layer metal stack of titanium, aluminum, and titanium (Al / Ti / Al), etc.

[0070] In some examples, the second interlayer insulating layer 13 is formed on a side of the first metal layer 50 away from the substrate 10. The second interlayer insulating layer 13 may be a passivation layer (PVX), which may be formed of materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0071] Fig.15 is a layout of the second transparent conductive layer in the array substrate of the embodiment of the present disclosure; Figure 5 and 15 As shown, the second transparent conductive layer 60 includes a common electrode 14 in each sub-pixel P, and the second transparent conductive layer 60 is electrically connected to the common electrode line CL through a via hole penetrating the second interlayer insulating layer 13. In some examples, the material of the second transparent conductive layer 60 can be the same as that of the first transparent conductive layer 40. This completes the introduction of the array substrate in the embodiment of the present disclosure.

[0072] Fig.16 is a layout of a display panel according to an embodiment of the present disclosure; Fig.16 As shown, the embodiment of the present disclosure also provides a display panel, which includes the above-mentioned array substrate, and an opposing substrate arranged opposite to the array substrate. The opposing substrate can be a color filter substrate, and in the embodiment of the present disclosure, the opposing substrate is described as a color filter substrate. Of course, the array substrate also includes a liquid crystal layer arranged between the array substrate and the color filter substrate, and a spacer PS for maintaining the thickness of the cell. The orthographic projection of a spacer PS on the base substrate 10 is located within the orthographic projection of a protrusion on the common electrode line CL on the base substrate 10.

[0073] In some examples, you can also refer to Figure 7, the spacers in the display panel are divided into a first spacer PS1 and a second spacer PS2, wherein the first spacer PS1 is higher than the second spacer PS2, and the area of ​​the orthographic projection of the first spacer PS1 on the base substrate 10 is larger than the area of ​​the orthographic projection of the second spacer PS2 on the base substrate 10. At this time, the first spacer PS1 is used as a main spacer to maintain the box thickness of the display panel; the second spacer PS2 is used as a secondary spacer to play a buffering role when an external force acts on the display panel. In the embodiment of the present disclosure, by forming a boss 102 on the common electrode line CL and setting the spacer at the position corresponding to the boss 102, the problem of uneven aperture ratio of each sub-pixel P due to different sizes of spacers can be effectively avoided.

[0074] Further, in the embodiment of the present disclosure, the first spacer PS1 and the second spacer PS2 may both be formed on the color filter substrate 300, in which case there is a certain distance between the second spacer PS2 and the array substrate 200. Of course, the first spacer PS1 and the second spacer PS2 may both be formed on the array substrate 200, in which case there is a certain distance between the second spacer PS2 and the color filter substrate 200.

[0075] In some examples, the first spacer PS1 and the second spacer PS2 in the display panel are evenly arranged, and the arrangement density ratio of the first spacer PS1 to the second spacer PS2 is about 1:30 to 1:70, for example: the arrangement density of the first spacer PS1 is 1 / 108, the arrangement density of the second spacer PS2 is 52 / 108, and the arrangement density ratio of the first spacer PS1 to the second spacer PS2 is 1:52. For another example: the arrangement density of the first spacer PS1 is 1 / 72, the arrangement density of the second spacer PS2 is 34:72, and the arrangement density ratio of the first spacer PS1 to the second spacer PS2 is 1:34. It should be noted that the arrangement density of the first spacer PS1 and the arrangement density of the second spacer PS2 depends on the size of the display panel, and the arrangement density of the first spacer PS1 and the orthographic projection area of ​​the second spacer PS2 on the base substrate 10 and other parameter factors. Since the display panel in the embodiment of the present disclosure includes the above-mentioned array substrate, it can achieve a PPI of more than 300, which is particularly suitable for projector projects.

[0076] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising: A base substrate, a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels arranged on the base substrate; The plurality of sub-pixels form a plurality of first pixel groups arranged side by side in a first direction and a plurality of second pixel groups arranged side by side in a second direction; each of the plurality of first pixel groups includes a plurality of sub-pixels arranged side by side in the second direction; each of the plurality of second pixel groups includes a plurality of sub-pixels arranged side by side in the first direction; a gate line is respectively arranged on both sides of each second pixel group in the second direction; for two adjacent sub-pixels in any of the second pixel groups, the gate line connected to one of them is located on one side of the two opposite sides of the sub-pixel in the second direction, and the gate line connected to the other is located on the other side of the two opposite sides of the sub-pixel in the second direction; each of the sub-pixels in every two adjacent first pixel groups is connected to the same data line, and each of the sub-pixels connected to the same data line is connected to different gate lines; wherein a first region is defined between any two adjacent first pixel groups, and a second region is defined between any two adjacent second pixel groups; a common electrode line is also arranged in at least part of the first region, and the common electrode line and the data line are located in different first regions; The common electrode line includes a plurality of common electrode line segments and a boss connected between two of the common electrode line segments, and a width of at least one of the bosses in any direction is greater than a width of the common electrode line segment in the first direction; the boss is located in the second area; A thin film transistor and a pixel electrode are arranged in the sub-pixel; the gate of the thin film transistor is connected to the gate line, the source is connected to the data line, and the drain is connected to the pixel electrode; The pixel electrodes in the same second pixel group constitute a pixel electrode group, and the thin film transistors in any two adjacent sub-pixels in the same second pixel group are respectively located at two opposite sides of the pixel electrode group in the second direction; The data line includes a plurality of data line segments, and a connecting line segment connecting two adjacent data line segments; the connecting line segment includes a first sub-connecting line segment and a second sub-connecting line segment, the first sub-connecting line segment is connected to the data line segment through the second sub-connecting line segment; the first sub-connecting line segment is located in the second area; the source of the thin film transistor is connected to the first sub-connecting line segment; the angle between the extension direction of the data line segment and the second direction is 5°~10°; the angle formed by the second sub-connecting line segment and the data line segment is 100°~130°.

2. The display substrate according to claim 1, wherein: For any two thin film transistors connected to the same data line and located in sub-pixels of two adjacent first pixel groups, the connection node between one of them and the data line is a first node, and the connection node between the other and the data line is a second node. With the midpoint of the first node and the second node as the center of symmetry, the two thin film transistors are centrally symmetrical.

3. The display substrate according to claim 1, wherein: A common electrode is also arranged in the sub-pixel; one of the pixel electrode and the common electrode is a slit electrode, and the other is a plate electrode; the extension direction of the slit of the slit electrode is the same as the extension direction of the data line segment.

4. The display substrate according to claim 1, wherein: An extending direction of the common electrode line segment is the same as an extending direction of the data line segment.

5. The display substrate according to any one of claims 1 to 4, wherein: The display substrate includes a first metal layer disposed on the base substrate; the first metal layer includes the data line, the common electrode line, and the source and drain of the thin film transistor.

6. The display substrate according to any one of claims 1 to 4, wherein: The display substrate includes a second metal layer disposed on the base substrate; the second metal layer includes the gate line and the gate of the thin film transistor.

7. The display substrate according to any one of claims 1 to 4, wherein: The display substrate comprises a second metal layer, a first interlayer insulating layer, a semiconductor layer, a first transparent conductive layer, a first metal layer, a second interlayer insulating layer, and a second transparent conductive layer which are arranged in sequence in a direction away from the base substrate; The first metal layer includes the data line, the common electrode line, the source and drain of the thin film transistor; The second metal layer includes the gate line and the gate of the thin film transistor; The first transparent conductive layer includes the pixel electrode; The second transparent conductive layer includes a common electrode.

8. The display substrate according to any one of claims 1 to 4, wherein: The data lines and the common electrode lines are alternately arranged in the first direction.

9. The display substrate according to any one of claims 1 to 4, wherein: The orthographic projection of the gate electrode of the thin film transistor on the substrate covers the orthographic projection of the semiconductor active layer on the substrate; wherein, The orthographic projection of the gate on the base substrate includes a first side and a second side that are oppositely arranged along the first direction, and a third side and a fourth side that are oppositely arranged along the second direction; the orthographic projection of the semiconductor active layer on the base substrate includes a fifth side and a sixth side that are oppositely arranged along the first direction, and a seventh side and an eighth side that are oppositely arranged along the second direction; The fourth side is connected to the orthographic projection of the gate line on the substrate; The first side is opposite to the fifth side, and the distance between the two is S1; the second side and the sixth side are opposite to each other, and the distance between the two is S2; the third side and the seventh side are opposite to each other, and the distance between the two is S3; at least one of S1, S2, and S3 is less than 3μm.

10. The display substrate according to claim 1, wherein: The width of any of the bosses in any direction is greater than the width of the common electrode line segment in the first direction; and the bosses have the same size.

11. A display panel comprising the display substrate according to any one of claims 1 to 10.

12. The display panel according to claim 11, wherein: It also includes an opposing substrate disposed opposite to the display substrate, and a spacer located between the display substrate and the opposing substrate; An orthographic projection of one of the spacers on the base substrate is located within an orthographic projection of one of the bosses on the base substrate.

13. The display panel according to claim 12, wherein: The spacer includes a first spacer and a second spacer; the height of the first spacer is greater than the height of the second spacer; and two ends of the first spacer are respectively against the display substrate and the opposite substrate.

14. The display panel according to claim 13, wherein: The first spacers and the second spacers are uniformly arranged in the display panel, and the ratio of the arrangement density of the first spacers to the arrangement density of the second spacers is 1:30-1:70.

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