Verification method, electronic device and computer-readable storage medium

Abstract

The present disclosure provides a verification method, an electronic device, and a computer-readable storage medium. The verification method is used to perform LVS verification of the consistency of the layout and schematic diagram of the first non-device layer and the second non-device layer in a semiconductor structure; the semiconductor structure includes a first non-device layer, a second non-device layer, and a first connection layer; the verification method includes: obtaining a merged layout based on the layout of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer in the merged layout as a capacitor; obtaining a circuit netlist based on the circuit netlist of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor based on the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist; and determining whether the first non-device layer and the second non-device layer pass the LVS verification based on the layout and circuit netlist of the capacitor.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a verification method, an electronic device, and a computer-readable storage medium. Background Art

[0002] As the integration density of integrated circuits increases, the development of integrated circuit technology, following Moore's Law, slows, and the importance of packaging technology becomes increasingly prominent. The 2.5D packaging structure has become a major technological highlight in the evolution of semiconductor products from two-dimensional to three-dimensional, and has become an essential tool for applications such as supercomputers and artificial intelligence. The 2.5D packaging structure is an advanced heterogeneous chip packaging structure that enables high-density wiring connections across multiple chips, integrating multiple chips into a single package. The 2.5D packaging structure offers numerous advantages, including reduced chip size, increased bandwidth, lower power consumption, and the ability to integrate heterogeneous chips.

[0003] While 2.5D packaging structures can continue, expand, and even surpass Moore's Law, they place higher demands on integration and packaging technologies. Furthermore, utilizing electronic design automation (EDA) tools to verify the consistency of 2.5D packaging layouts and schematics (Layout Versus Schematics, LVS) presents new challenges, particularly in LVS verification of interposers within 2.5D packaging structures. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a verification method, an electronic device, and a computer-readable storage medium.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a verification method for performing LVS verification of the consistency of a layout and a schematic diagram on a first non-device layer and a second non-device layer in a semiconductor structure; the semiconductor structure includes the first non-device layer, the second non-device layer, and a first connection layer electrically connecting the first non-device layer and the second non-device layer; the verification method includes:

[0007] Obtaining a merged layout according to the layouts of the first non-device layer, the second non-device layer, and the first connection layer;

[0008] Setting the first connection layer in the merged layout as a capacitor;

[0009] Obtaining a circuit netlist according to the circuit netlists of the first non-device layer, the second non-device layer, and the first connection layer;

[0010] According to the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist, setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor;

[0011] According to the layout and circuit netlist of the capacitor, it is determined whether the first non-device layer and the second non-device layer pass LVS verification.

[0012] In some embodiments, the first connection layer includes: micro-bumps;

[0013] The step of setting the first connection layer in the merged layout as a capacitor includes:

[0014] According to the merged layout, a layout netlist is obtained;

[0015] The micro-bumps in the layout netlist are set as capacitors.

[0016] In some embodiments, the micro-bumps include: a first bump and a second bump; the first non-device layer includes: a first wiring layer and a second wiring layer;

[0017] The second non-device layer includes: a first interconnect structure, the first bump electrically connecting the first wiring layer and the first interconnect structure;

[0018] The step of setting the micro-bumps in the layout netlist as capacitors comprises:

[0019] The first bump in the layout netlist is set as a capacitor; wherein the first wiring layer is set as a first electrode plate of the capacitor, and the first interconnect structure is set as a second electrode plate of the capacitor.

[0020] In some embodiments, the second non-device layer further includes: a second interconnect structure, the second bump electrically connecting the second wiring layer and the second interconnect structure;

[0021] The step of setting the micro-bumps in the layout netlist as capacitors comprises:

[0022] The second bump in the layout netlist is set as a capacitor; wherein the second wiring layer is set as a first electrode plate of the capacitor, and the second interconnect structure is set as a second electrode plate of the capacitor.

[0023] In some embodiments, determining whether the first non-device layer and the second non-device layer pass LVS verification based on the layout and circuit netlist of the capacitor includes:

[0024] Determining whether the first non-device layer and the second non-device layer pass LVS verification according to the layout netlist and the circuit netlist of the capacitor;

[0025] If the layout netlist and the circuit netlist of the capacitor set by the first bump and the capacitor set by the second bump are consistent, it is determined that the first non-device layer and the second non-device layer pass the LVS verification;

[0026] If the layout netlist and circuit netlist of the capacitor defined by the first bump and / or the capacitor defined by the second bump are inconsistent, it is determined that the first non-device layer and the second non-device layer have failed LVS verification.

[0027] In some embodiments, obtaining a merged layout according to the layouts of the first non-device layer, the second non-device layer, and the first connection layer includes:

[0028] Converting coordinate parameters of the layout of the first non-device layer and the second non-device layer according to the layout of the first non-device layer and the second non-device layer and the text labels of the micro-bumps so that the coordinate systems corresponding to the coordinate parameters of the layout of the first non-device layer and the second non-device layer are the same;

[0029] The layouts of the first non-device layer and the second non-device layer are merged according to the converted coordinate parameters of the layouts of the first non-device layer and the second non-device layer to obtain a merged layout.

[0030] In some embodiments, the semiconductor structure further comprises:

[0031] a substrate, wherein the second non-device layer is located between the substrate and the first non-device layer;

[0032] A second connection layer electrically connects the substrate and the second non-device layer.

[0033] In some embodiments, the first non-device layer includes: a redistribution layer; and the second non-device layer includes: an interposer.

[0034] In a second aspect, an embodiment of the present disclosure provides an electronic device, the electronic device comprising:

[0035] Memory;

[0036] A processor coupled to the memory; wherein the memory stores a computer program, and when the processor executes the computer program, the verification method described in the above technical solution is implemented.

[0037] In a third aspect, an embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, the verification method described in the above technical solution is implemented.

[0038] The present disclosure provides a verification method, an electronic device, and a computer-readable storage medium. The verification method is used to perform LVS verification of the consistency of the layout and the schematic diagram of the first non-device layer and the second non-device layer in the semiconductor structure; the semiconductor structure includes the first non-device layer, the second non-device layer, and a first connection layer electrically connecting the first non-device layer and the second non-device layer; the verification method includes: obtaining a merged layout based on the layout of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer in the merged layout as a capacitor; obtaining a circuit netlist based on the circuit netlist of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor based on the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist; and determining whether the first non-device layer and the second non-device layer pass the LVS verification based on the layout and circuit netlist of the capacitor. In the embodiment of the present disclosure, the first connection layer electrically connecting the first non-device layer and the second non-device layer is set as a capacitor, and LVS verification is performed on the capacitor to determine whether the first non-device layer and the second non-device layer have passed the LVS verification. This not only reduces the amount of data for LVS verification, thereby reducing the pressure of LVS verification on machine resources, but also saves time for each LVS verification and improves the efficiency of LVS verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the packaging structure provided for the relevant technical solution;

[0040] Figure 2 A flowchart of the verification method provided for the relevant technical solution;

[0041] Figure 3 A flowchart of a verification method provided in an embodiment of the present disclosure;

[0042] Figure 4 Schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 1 ;

[0043] Figure 5 Schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 2 ;

[0044] Figure 6 Schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 3 ;

[0045] Figure 7 A schematic diagram of a semiconductor structure provided for a specific example;

[0046] Figure 8 A flowchart of a verification method provided for a specific example;

[0047] Figure 9 A schematic diagram of a semiconductor structure is provided for another specific example;

[0048] Figure 10 A block diagram of an electronic device provided for an embodiment of the present disclosure;

[0049] Figure 11 A block diagram of a computer-readable storage medium provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0051] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0052] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0053] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0054] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0055] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0056] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0057] refer to Figure 1 , Figure 1 Schematic diagram of the packaging structure provided by the relevant technical solution. Figure 1 As shown, the packaging structure includes: a substrate (Circuit Board) 160; an interposer (Interposer) 140 arranged on the substrate 160; a first semiconductor chip 110 and a second semiconductor chip 120 arranged on the interposer 140; wherein the interposer 140 can be used to achieve electrical connection between the first semiconductor chip 110 and the second semiconductor chip 120, or, electrical connection between the first semiconductor chip 110 and the substrate 160, or, electrical connection between the second semiconductor chip 120 and the substrate 160.

[0058] It should be understood that in order to clearly illustrate each layer structure in the figure, the size ratio relationship of each layer structure may be inconsistent with the actual structure.

[0059] Here, the first semiconductor chip 110 and the second semiconductor chip 120 can be arranged side by side on the interposer 140. Of course, the embodiment of the present disclosure has no particular limitation on the number of semiconductor chips arranged on the interposer 140. At least two semiconductor chips can be arranged on the interposer 140, and the semiconductor chips are arranged side by side in a direction parallel to the surface of the interposer 140, that is, the bottom surfaces of the semiconductor chips are in the same plane and the plane is parallel to the surface of the interposer 140.

[0060] Here, the first semiconductor chip 110 may include: a system on chip (SOC); the second semiconductor chip may include: an on-chip memory. Among them, the system on chip refers to a system formed by combining multiple integrated circuits with specific functions on a semiconductor chip. The system on chip reduces the size, power consumption, system functionality and cost by shrinking each node with different functions. The storage particles in the on-chip memory are stacked and integrated in the form of dies. The on-chip memory may include at least one of the following: High Bandwidth Memory (HBM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Magnetic Random Access Memory (MRAM) and Flash Memory.

[0061] Still Figure 1 As shown, the packaging structure also includes: a micro bump 130, which is arranged between the first semiconductor chip 110 (or the second semiconductor chip 120) and the interposer 140; wherein the micro bump 130 is used to achieve an electrical connection between the first semiconductor chip 110 (or the second semiconductor chip 120) and the interposer 140, or, an electrical connection between the first semiconductor chip 110 and the second semiconductor chip 120; a bump 150, which is arranged between the interposer 140 and the substrate 160; wherein the bump 150 is used to achieve an electrical connection between the interposer 140 and the substrate 160.

[0062] Here, microbumps 130 can connect the first semiconductor chip 110 (or the second semiconductor chip 120) and the interposer 140 to form a 2.5D package structure. Bumps 150 can be controlled-collapse chip connection bumps (C4 Bumps), for example, copper pillar bumps used to connect the interposer 140 and the substrate 160.

[0063] Still Figure 1As shown, the interposer 140 includes: a through silicon via (TSV) 141 that passes through the interposer 140, and the through silicon via 141 can be used to achieve electrical connection between the micro-bump 130 and the bump 150; a first conductive wire 142, and the first conductive wire 142 can be used to achieve electrical connection between the two micro-bumps 130 of the first semiconductor chip 110 and the second semiconductor chip 120; and a second conductive wire 143 can be used to achieve electrical connection between the two micro-bumps 130 of the first semiconductor chip 110.

[0064] Here, one end of the through-silicon via 141 is connected to the microbump 130 of the second semiconductor chip 120, and the other end of the through-silicon via 141 is connected to the bump 150. The through-silicon via 141 can be used to achieve an electrical connection between the second semiconductor chip 120 and the substrate 160. One end of the first conductive wire 142 is connected to the microbump 130 of the first semiconductor chip 110, and the other end of the first conductive wire 142 is connected to the microbump 130 of the second semiconductor chip 120. The first conductive wire 142 can be used to achieve an electrical connection between the first semiconductor chip 110 and the second semiconductor chip 120. The two ends of the second conductive wire 143 are respectively connected to the two microbumps 130 of the first semiconductor chip 110. The second conductive wire 143 can be used to achieve an electrical connection between the two microbumps 130 of the first semiconductor chip 110.

[0065] Still Figure 1 As shown, taking the first semiconductor chip 110 as an example, the first semiconductor chip 110 may include: a substrate 111; a device layer 112 disposed on the substrate 111; a metal layer 113 disposed on the device layer 112; a redistribution layer (RDL) 114 disposed on the metal layer 113; a passivation layer 115 disposed on the redistribution layer 114, and connection pads 116 disposed within the passivation layer 115. The first semiconductor chip 110 is flipped over and disposed on the interposer 140. The first semiconductor chip 110 is electrically connected to the microbumps 130 via the connection pads 116.

[0066] Here, the passivation layer 115 can cover the redistribution layer 114 to protect the redistribution layer 114 and other layers of structures within the first semiconductor chip 110. After the passivation layer 115 covering the redistribution layer 114 is formed, an opening can be etched to form a conductive material within the opening to form a connection pad 116. The surface of the passivation layer 115 is substantially flush with the surface of the connection pad 116. The connection pad 116 can be used to achieve electrical connection between the redistribution layer 114 and the microbump 130 within the first semiconductor chip 110.

[0067] For the above-mentioned packaging structure, the process of integrated circuit design usually includes: specification definition, specific circuit design, circuit simulation, layout design, physical verification, parasitic parameter extraction and simulation, and export of tape-out data and testing. Among them, the physical verification stage usually includes: Design Rule Check (DRC) and LVS verification. Design rule check is used to ensure the feasibility of the layout in the process. Based on the given design rules, process restrictions such as minimum line width, minimum pattern spacing, hole size, minimum overlap area of gate and source and drain regions are checked. LVS verification is used to ensure the matching of layout design and its circuit design. EDA tools (for example, Calibre) can be used to extract a layout netlist including electrical connection properties and size from the layout of the integrated circuit, and then compare the layout netlist with the circuit netlist obtained from the schematic diagram. By comparing whether the layout netlist and the circuit netlist are consistent, it is determined whether the integrated circuit has passed the LVS verification.

[0068] Specifically, comparing the layout netlist and circuit netlist for consistency includes comparing for inconsistent points and comparing for mismatched devices. Inconsistent points include node inconsistencies and device inconsistencies. Node inconsistencies refer to nodes in the layout netlist and circuit netlist that are similar but not identical in their connected devices. Device inconsistencies refer to devices in the layout netlist and circuit netlist that are identical and connected to similar but not identical nodes. Mismatched devices refer to devices that are present in the circuit netlist but not in the layout netlist, or devices that are present in the layout netlist but not in the circuit netlist. Therefore, the essence of LVS verification requires device extraction and connection relationship extraction.

[0069] In the above-mentioned packaging structure, the interposer is used to realize the electrical connection between each semiconductor chip or the electrical connection between each semiconductor chip and the substrate. The interposer only includes, for example, through-silicon vias, first conductive wires and second conductive wires, and no actual devices (for example, transistors) are set in the interposer. Therefore, it is impossible to use mainstream EDA tools for sign-off checks (for example, Calibre) to perform separate LVS verification on the layout netlist and circuit netlist of the completed interposer.

[0070] In order to use the Calibre tool to perform LVS verification on the layout netlist and circuit netlist of the completed interposer, it is necessary to combine the data of the interposer and each semiconductor chip to perform LVS verification on the interposer.

[0071] refer to Figure 2 , Figure 2 A flowchart of the verification method provided for the relevant technical solution, Figure 2 Indicate the right Figure 1The flowchart of LVS verification of the interposer in the package structure is shown in FIG. Figure 2 As shown, a top-level layout is obtained based on the layout of the first semiconductor chip, the layout of the second semiconductor chip, the layout of the interposer, the layout of the micro-bumps, and the layout of the bumps; a top-level circuit netlist is obtained based on the circuit netlist of the first semiconductor chip, the circuit netlist of the second semiconductor chip, and the circuit netlist of the interposer; and the top-level layout and the top-level circuit netlist are compared to determine whether the interposer has passed LVS verification.

[0072] Here, the top-level layout refers to the layout obtained by merging the layouts of the first semiconductor chip, the second semiconductor chip, the interposer, the micro-bumps, and the bumps; the top-level circuit netlist refers to the circuit netlist obtained by merging the circuit netlists of the first semiconductor chip, the second semiconductor chip, and the interposer.

[0073] It should be noted that after obtaining the top-level layout, it is necessary to perform netlist conversion on the top-level layout to obtain the top-level layout netlist, so that the data format of the layout data (i.e., the top-level layout netlist) and the schematic data (i.e., the top-level circuit netlist) are the same. In this way, it is possible to determine whether the interposer has passed the LVS verification based on the top-level layout netlist and the top-level circuit netlist.

[0074] by Figure 2 Taking the flowchart of the verification method shown as an example, to determine whether the interposer has passed the LVS verification, it is necessary to combine the circuit netlists of the first semiconductor chip, the second semiconductor chip and the interposer, create a top-level circuit netlist including the above three parts of the circuit netlist, and merge the layouts of the first semiconductor chip, the second semiconductor chip and the interposer, as well as the layouts of the micro-bumps and bumps, to create a top-level layout. By comparing the top-level layout and the top-level circuit netlist, it is determined whether the interposer has passed the LVS verification.

[0075] like Figure 2As shown, the process of performing LVS verification on the interposer, combining the data of the interposer and each semiconductor chip, is extremely lengthy and complex. Firstly, the total layout data of the semiconductor chip is extremely large, and multiple semiconductor chips can be placed on the interposer. This results in a very large amount of layout data required for LVS verification, requiring a significant amount of time to prepare. Each LVS verification of the interposer is lengthy and places high demands on machine resources. In extreme cases, the sheer volume of layout data can even cause the signoff tool to crash, preventing LVS verification results from being obtained. Secondly, before LVS verification of the interposer is performed, LVS verification must first be performed on each semiconductor chip placed on the interposer, and a determination must be made that each semiconductor chip has passed LVS verification. LVS verification of each semiconductor chip is typically performed near the end of a project, placing LVS verification of the interposer very late in the project cycle. Furthermore, the interposer design typically requires repeated iterations, which undoubtedly lengthens the project cycle and is highly inefficient.

[0076] In view of this, embodiments of the present disclosure provide a verification method, electronic device, and computer-readable storage medium. In the embodiments of the present disclosure, a first connection layer electrically connecting a first non-device layer and a second non-device layer is set as a capacitor. LVS verification is performed on the capacitor to determine whether the first non-device layer and the second non-device layer have passed LVS verification. This not only reduces the amount of data required for LVS verification, thereby reducing the pressure on machine resources during LVS verification, but also saves time during each LVS verification, thereby improving the efficiency of LVS verification.

[0077] refer to Figure 3 and Figure 4 , Figure 3 A flow chart of a verification method provided in an embodiment of the present disclosure is provided. Figure 4 Schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 1 .like Figure 3 and Figure 4 As shown, an embodiment of the present disclosure provides a verification method for performing LVS verification on a first non-device layer 210 and a second non-device layer 220 in a semiconductor structure; the semiconductor structure includes the first non-device layer 210, the second non-device layer 220, and a first connection layer 230 electrically connecting the first non-device layer 210 and the second non-device layer 220; the verification method includes:

[0078] Step S301: obtaining a merged layout according to the layouts of the first non-device layer, the second non-device layer, and the first connection layer;

[0079] Step S302: setting the first connection layer in the merged layout as a capacitor;

[0080] Step S303: obtaining a circuit netlist according to the circuit netlists of the first non-device layer, the second non-device layer, and the first connection layer;

[0081] Step S304: according to the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist, setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor;

[0082] Step S305: determining whether the first non-device layer and the second non-device layer pass LVS verification based on the layout and circuit netlist of the capacitor.

[0083] Here, no actual devices are provided in the first non-device layer 210 and the second non-device layer 220. More specifically, no devices such as transistors, resistors, capacitors, or inductors are provided in the first non-device layer 210 and the second non-device layer 220. The first non-device layer 210 and the second non-device layer 220 only include, for example, through-silicon vias (TSVs) or interconnects.

[0084] In the embodiment of the present disclosure, LVS verification is performed on the first non-device layer and the second non-device layer, and the first connection layer electrically connecting the first non-device layer and the second non-device layer is set as a capacitor. In this way, the first non-device layer and the second non-device layer are respectively set as the two electrode plates of the capacitor. By performing LVS verification on the capacitor, it can be determined whether the first non-device layer and the second non-device layer have passed the LVS verification. In the embodiment of the present disclosure, it is not necessary to obtain all the layout data of the semiconductor chip. On the one hand, the amount of data for LVS verification can be reduced to reduce the pressure of LVS verification on machine resources; on the other hand, it can also save time for each LVS verification and improve the efficiency of LVS verification. In addition, there is no need to wait until the end of the project to obtain all the layout data of each semiconductor chip. LVS verification can be performed on the first non-device layer and the second non-device layer at the beginning of the project. On the premise that the first non-device layer and the second non-device layer can pass the LVS verification at the beginning of the project, repeated communication and iteration of the layout design of the first non-device layer and the second non-device layer can greatly speed up the project progress.

[0085] In the embodiment of the present disclosure, it is precisely because no devices are set in the first non-device layer and the second non-device layer that LVS verification cannot be performed on the first non-device layer or the second non-device layer separately. As mentioned above, the essence of LVS verification is to extract devices and extract connection relationships. If the first connection layer electrically connecting the first non-device layer and the second non-device layer is set as a capacitor, then the semiconductor structure is equivalent to having a device (i.e., a capacitor), and the connection relationship between the capacitor and its two electrode plates can be extracted for LVS verification.

[0086] refer to Figure 5 , Figure 5Schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 2 .like Figure 5 As shown, the first connection layer may include micro-bumps 240 ; the first non-device layer 210 and the second non-device layer 220 may be electrically connected via the micro-bumps 240 .

[0087] In the embodiment of the present disclosure, in step S302, setting the first connection layer in the merged layout as a capacitor includes:

[0088] According to the merged layout, the layout netlist is obtained;

[0089] Set the micro-bumps in the layout netlist as capacitors.

[0090] Here, you can perform a netlist conversion on the merged layout, converting it into a layout netlist. The microbumps in the layout netlist can be configured as capacitors. The first and second non-device layers, connected to the ends of the microbumps, can then be configured as the two electrode plates of the capacitor. LVS verification of the capacitor can be performed to determine whether the first and second non-device layers have passed LVS verification.

[0091] The netlist conversion process generally includes: first, extracting devices and their connection ports; then, generating textual information on the corresponding connection relationships between the connection ports of the devices based on the connection relationships between the connection ports of the devices.

[0092] In the embodiment of the present disclosure, in step S301, a merged layout is obtained according to the layouts of the first non-device layer, the second non-device layer, and the first connection layer, including:

[0093] Converting coordinate parameters of the layout of the first non-device layer and / or the second non-device layer according to the layouts of the first non-device layer and the second non-device layer and the text labels of the micro-bumps so that the coordinate systems corresponding to the coordinate parameters of the layouts of the first non-device layer and the second non-device layer are the same;

[0094] The layouts of the first non-device layer and the second non-device layer are merged according to the converted coordinate parameters of the layouts of the first non-device layer and the second non-device layer to obtain a merged layout.

[0095] Here, in the process of designing the layout of the first non-device layer and the second non-device layer, the layout of the first non-device layer corresponds to the first coordinate system, and the layout of the second non-device layer corresponds to the second coordinate system. Before merging the layout of the first non-device layer and the layout of the second non-device layer, it is necessary to make the layouts of the first non-device layer and the second non-device layer correspond to the same coordinate system. Among them, the layout of the first non-device layer corresponds to the first coordinate system means that the coordinate parameters of each layer in the layout of the first non-device layer are determined based on the first coordinate system. The layout of the second non-device layer corresponds to the second coordinate system means that the coordinate parameters of each layer in the layout of the second non-device layer are determined based on the second coordinate system. Therefore, the coordinate parameters of the layout of the first non-device layer can be converted so that the layouts of the first non-device layer and the second non-device layer both correspond to the second coordinate system, that is, after the coordinate parameters are converted, the coordinate parameters of each layer in the layout of the first non-device layer and the second non-device layer are determined based on the second coordinate system; or, the coordinate parameters of the layout of the second non-device layer can be converted so that the layouts of the first non-device layer and the second non-device layer both correspond to the first coordinate system, that is, after the coordinate parameters are converted, the coordinate parameters of each layer in the layout of the first non-device layer and the second non-device layer are determined based on the first coordinate system; or, the coordinate parameters of the layout of the first non-device layer and the second non-device layer can be converted so that the layouts of the first non-device layer and the second non-device layer both correspond to the third coordinate system, that is, after the coordinate parameters are converted, the coordinate parameters of each layer in the layout of the first non-device layer and the second non-device layer are determined based on the third coordinate system.

[0096] It should be noted that if the first connection layer (for example, micro-bumps) is provided on the second non-device layer, then the relative positional relationship between the first connection layer and the second non-device layer is fixed, and in the process of converting the coordinate parameters of the layout of the first non-device layer and / or the second non-device layer, the coordinate system corresponding to the first connection layer and the second non-device layer is always the same. Therefore, when the coordinate systems corresponding to the coordinate parameters of the layouts of the first non-device layer and the second non-device layer are the same, the first non-device layer, the second non-device layer and the first connection layer all correspond to the same coordinate system. The text label of the micro-bump includes: name and location information; wherein the location information includes the layout layer number and coordinate parameters in which it is located.

[0097] refer to Figure 6 , Figure 6 Schematic diagram of the semiconductor structure provided by the embodiment of the present disclosure Figure 3 .like Figure 6The first non-device layer 210 includes: a first wiring layer 211 and a second wiring layer 212; the micro-bumps 240 include: a first bump 241 and a second bump 242; the second non-device layer 220 includes: a first interconnect structure 221, wherein the first bump 241 electrically connects the first wiring layer 211 and the first interconnect structure 221; and a second interconnect structure 222, wherein the second bump 242 electrically connects the second wiring layer 212 and the second interconnect structure 222.

[0098] Still Figure 6 As shown, the semiconductor structure further includes: a substrate 260; a second non-device layer 220 located between the substrate 260 and the first non-device layer 210; and a second connection layer electrically connecting the substrate 260 and the second non-device layer 220; wherein the second connection layer may include a bump 250. Specifically, one end of a first interconnect structure 221 within the second non-device layer 220 is connected to a first bump 241, and the other end of the first interconnect structure 221 is connected to the bump 250. The first interconnect structure 221 penetrates the second non-device layer 220, and the first bump 241 and the bump 250 are respectively arranged on opposite sides of the second non-device layer 220. The second interconnect structure 222 within the second non-device layer 220 has one end connected to a second bump 242, and the other end of the second interconnect structure 222 is connected to another second bump 242. The second interconnect structure 222 does not penetrate the second non-device layer 220, and the two second bumps 242 are arranged on the same side of the second non-device layer 220.

[0099] In the embodiment of the present disclosure, the micro-bumps in the layout netlist are set as capacitors, including:

[0100] The first bump in the layout netlist is set as a capacitor; wherein the first wiring layer is set as a first electrode plate of the capacitor, and the first interconnect structure is set as a second electrode plate of the capacitor.

[0101] In the embodiment of the present disclosure, the micro-bumps in the layout netlist are set as capacitors, including:

[0102] The second bump in the layout netlist is set as a capacitor; wherein the second wiring layer is set as a first electrode plate of the capacitor, and the second interconnect structure is set as a second electrode plate of the capacitor.

[0103] Here, the second non-device layer 220 may include a first interconnect structure 221 and a second interconnect structure 222. The first interconnect structure 221 and the second interconnect structure 222 have different electrical connection relationships. The two ends of the first interconnect structure 221 are respectively connected to the first bumps 241 and the bumps 250 located on opposite sides of the second non-device layer 220; and the two ends of the second interconnect structure 222 are respectively connected to the two second bumps 242 located on the same side of the second non-device layer 220.

[0104] Here, the micro bump 240 may include a first bump 241 and a second bump 242. The electrical connection relationship between the first bump 241 and the second bump 242 is different. The two ends of the first bump 241 are respectively connected to the first wiring layer 211 and the first interconnection structure 221; the two ends of the second bump 242 are respectively connected to the second wiring layer 212 and the second interconnection structure 222.

[0105] Here, if the first bump 241 is set as a capacitor, then the first wiring layer 211 and the first interconnect structure 221 connected at both ends of the first bump 241 can be set as the first electrode plate and the second electrode plate of the capacitor, respectively. If the second bump 242 is set as a capacitor, then the second wiring layer 212 and the second interconnect structure 222 connected at both ends of the second bump 242 can be set as the first electrode plate and the second electrode plate of the capacitor, respectively.

[0106] It should be noted that the term "first bump" refers to a microbump that can be used to achieve electrical connection between the first wiring layer and the first interconnect structure; the term "second bump" refers to a microbump that can be used to achieve electrical connection between the second wiring layer and the second interconnect structure. Microbumps are divided into first and second bumps based on their different connection relationships, rather than based on their electrical connection to different semiconductor chips. Therefore, a first bump can be electrically connected to both the first and second semiconductor chips; a second bump can be electrically connected to both the first and second semiconductor chips. Similarly, the first non-device layer is divided into a first wiring layer and a second wiring layer based on their different connection relationships, rather than based on their belonging to different semiconductor chips. Therefore, a first wiring layer can belong to either the first or second semiconductor chip; a second wiring layer can belong to either the first or second semiconductor chip.

[0107] During the specific implementation process, it is necessary to distinguish and define each first bump according to the design requirements so as to obtain the connection relationship between each first bump and the first wiring layer and the first interconnection structure. The distinction can be made by defining the name of each capacitor. For example, the micro-bump includes three first bumps, and the three first bumps are set as capacitors C1, C2 and C3 respectively. The design requirements include: the three first bumps correspond to the first wiring layer a, the first wiring layer b and the first wiring layer c in the first non-device layer, and the three first bumps correspond to the first interconnection structure A, the first interconnection structure B and the first interconnection structure C in the second non-device layer. In other words, the first wiring layer a is set as the first electrode plate of capacitor C1, and the first interconnection structure A is set as the second electrode plate of capacitor C1; the first wiring layer b is set as the first electrode plate of capacitor C2, and the first interconnection structure B is set as the second electrode plate of capacitor C2; the first wiring layer c is set as the first electrode plate of capacitor C3, and the first interconnection structure C is set as the second electrode plate of capacitor C2.

[0108] The three first bumps are set as capacitors C1, C2 and C3 respectively. According to the names of the set capacitors (for example, C1, C2 and C3) and the connection relationship between the first electrode plate and the second electrode plate, it is distinguished which first wiring layer in the first non-device layer each first bump specifically corresponds to, and it is distinguished which first interconnect structure in the second non-device layer each first bump specifically corresponds to.

[0109] It should be noted that the first interconnect structure and the bump have a one-to-one correspondence, and therefore, setting the first interconnect structure as the second electrode plate of the capacitor is equivalent to setting the bump as the second electrode plate of the capacitor.

[0110] During the specific implementation process, it is necessary to distinguish and define each second bump according to the design requirements so as to obtain the connection relationship between each second bump and the second wiring layer and the second interconnect structure. The distinction can be made by defining the name of each capacitor. For example, the micro bump includes 3 second bumps, and the 3 second bumps are set as capacitors C4, C5 and C6 respectively. The design requirements include: the 3 second bumps correspond to the second wiring layer d, the second wiring layer e and the second wiring layer f in the second non-device layer, and the 3 second bumps correspond to the second interconnect structure D, the second interconnect structure E and the second interconnect structure F in the second non-device layer. In other words, the second wiring layer d is set as the first electrode plate of capacitor C4, and the second interconnect structure D is set as the second electrode plate of capacitor C4; the second wiring layer e is set as the first electrode plate of capacitor C5, and the second interconnect structure E is set as the second electrode plate of capacitor C5; the second wiring layer f is set as the first electrode plate of capacitor C6, and the second interconnect structure F is set as the second electrode plate of capacitor C6.

[0111] The above-mentioned three second bumps are set as capacitors C4, C5 and C6 respectively. According to the names of the set capacitors (for example, C4, C5 and C6) and the connection relationship between the first electrode plate and the second electrode plate, it is distinguished which second wiring layer in the first non-device layer each second bump specifically corresponds to, and it is distinguished which second interconnect structure in the second non-device layer each second bump specifically corresponds to.

[0112] In the embodiment of the present disclosure, in step S303, a circuit netlist is obtained based on the circuit netlist of the first non-device layer, the second non-device layer and the first connection layer; in step S304, based on the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist, the first connection layer between the first non-device layer and the second non-device layer is set as a capacitor.

[0113] In a specific implementation, since there are no actual devices in the first non-device layer and the second non-device layer, the first non-device layer and the second non-device layer may include, for example, interconnects. The first connection layer is set as a capacitor, and different capacitors are distinguished by their names to facilitate the connection relationship between each capacitor and the first non-device layer and the second non-device layer.

[0114] In the embodiment of the present disclosure, in step S305, determining whether the first non-device layer and the second non-device layer pass LVS verification based on the layout and circuit netlist of the capacitor includes:

[0115] Determine whether the first non-device layer and the second non-device layer pass LVS verification based on the layout netlist and circuit netlist of the capacitor;

[0116] If the layout netlist and circuit netlist of the capacitor set by the first bump and the capacitor set by the second bump are consistent, it is determined that the first non-device layer and the second non-device layer pass the LVS verification;

[0117] If the layout netlist and the circuit netlist of the capacitor defined by the first bump and / or the capacitor defined by the second bump are inconsistent, it is determined that the first non-device layer and the second non-device layer fail the LVS verification.

[0118] Here, the layout netlist and circuit netlist of the capacitor defined by the first bump are compared, the first wiring layer is defined as the first electrode plate of the capacitor, and the first interconnect structure is defined as the second electrode plate of the capacitor. Based on whether the connection relationship between the first electrode plate and the second electrode plate of the capacitor defined by the first bump meets the design requirements, it is determined whether the layout netlist and circuit netlist of the capacitor defined by the first bump are consistent. Based on whether the layout netlist and circuit netlist of the capacitor defined by the first bump are consistent, it is determined whether the first wiring layer and the first interconnect structure have passed LVS verification.

[0119] Here, the layout netlist and circuit netlist of the capacitor defined by the second bump are compared, the second wiring layer is defined as the first electrode plate of the capacitor, and the second interconnect structure is defined as the second electrode plate of the capacitor. Based on whether the connection relationship between the first electrode plate and the second electrode plate of the capacitor defined by the second bump meets the design requirements, it is determined whether the layout netlist and circuit netlist of the capacitor defined by the second bump are consistent. Based on whether the layout netlist and circuit netlist of the capacitor defined by the second bump are consistent, it is determined whether the second wiring layer and the second interconnect structure have passed LVS verification.

[0120] In the embodiment of the present disclosure, only when the first wiring layer and the first interconnect structure pass the LVS verification, and the second wiring layer and the second interconnect structure pass the LVS verification, can it be determined that the first non-device layer and the second non-device layer pass the LVS verification. If the first wiring layer and the first interconnect structure fail to pass the LVS verification, or the second wiring layer and the second interconnect structure fail to pass the LVS verification, or the first wiring layer and the first interconnect structure fail to pass the LVS verification and the second wiring layer and the second interconnect structure fail to pass the LVS verification, then it is determined that the first non-device layer and the second non-device layer fail to pass the LVS verification.

[0121] In the embodiment of the present disclosure, the first non-device layer includes: a redistribution layer; the second non-device layer includes: an intermediate layer.

[0122] Here, the first non-device layer and the second non-device layer are electrically connected via the first connection layer, that is, the redistribution layer and the interposer are electrically connected via micro-bumps. Determine whether the first non-device layer and the second non-device layer have passed LVS verification, that is, determine whether the redistribution layer and the interposer have passed LVS verification. To speed up and increase the efficiency of LVS verification of the interposer, the layout data of the junction of the semiconductor chip and the interposer is used to replace the entire layout data of the semiconductor chip, and the layout layer number of the micro-bump is set as a capacitor. The layout is merged using the concepts of the first electrode plate and the second electrode plate of the capacitor, and then compared with the circuit netlist, thereby reducing comparison time, lowering machine load, and shortening the project iteration cycle.

[0123] Due to the high machine resource requirements and extended project cycles for LVS verification of the interposer, the verification method provided by the disclosed embodiments can use a smaller machine load. This ensures consistency between the interposer layout and schematics at the beginning of the project, allowing for repeated communication and iteration with the packaging team on the interposer layout design, greatly accelerating the project progress.

[0124] refer to Figure 7 , Figure 7 A schematic diagram of a semiconductor structure is provided for a specific example. Figure 7As shown, the package structure includes: a substrate 360; an interposer 340 disposed on the substrate 360; a first semiconductor chip 310 and a second semiconductor chip 320 disposed on the interposer 340; wherein the interposer 340 and the substrate 360 are electrically connected via bumps 350; the second semiconductor chip 320 and the interposer 340 are electrically connected via microbumps 330 and through-silicon vias 341 within the interposer 340; the second semiconductor chip 320 and the first semiconductor chip 310 are electrically connected via the microbumps 330 and a first conductive line 342 within the interposer 340; and the two microbumps 330 of the first semiconductor chip 310 can be electrically connected via a second conductive line 343 within the interposer 340. The first semiconductor chip 310 and the second semiconductor chip 320 can both be SOC chips.

[0125] Still Figure 7 As shown, taking the first semiconductor chip 310 as an example, the first semiconductor chip 310 includes: a substrate 311 ; a device layer 312 disposed on the substrate 311 ; and a redistribution layer 313 disposed on the device layer 312 .

[0126] for Figure 7 In the specific example shown, the first non-device layer may be a redistribution layer 313 within the first semiconductor chip (or the second semiconductor chip), the second non-device layer may be an intermediate layer 340 , and the first connection layer may be a micro-bump 330 .

[0127] Figure 7 The package structure shown is a 2.5D package structure. Since there are no actual devices in the interposer, the interposer cannot be independently verified by LVS. However, the data of the first semiconductor chip, the second semiconductor chip and the interposer are combined to perform LVS verification on the interposer. The data is too large, the machine resources are high and it takes a long time. Therefore, the verification method provided by the embodiment of the present disclosure selects the layout data of the redistribution layer at the junction of the semiconductor chip and the interposer. Without waiting for the entire layout data of the semiconductor chip and without increasing manpower and machine costs, the consistency of the layout and schematic diagram of the interposer of the package structure can be verified. This can solve the problem that the amount of data for LVS verification of the interposer by combining the data of the semiconductor chip and the interposer in the 2.5D package structure is too large and the machine time cost is huge, effectively shortening the design cycle and improving the efficiency of sign-off inspection.

[0128] An embodiment of the present disclosure provides an automated script plug-in, which needs to be used in a chip back-end design process. During use, the plug-in can implement the verification method provided by the embodiment of the present disclosure.

[0129] refer to Figure 8 , Figure 8 A flowchart of a verification method provided for a specific example, Figure 8 Indicate the right Figure 7 The flowchart of LVS verification of the interposer in the semiconductor structure is shown in FIG. Figure 8 As shown, the verification method provided by the embodiment of the present disclosure includes the following steps: in step S801, based on the layout and routing data of the semiconductor chip, the layout of the rewiring layer is extracted using script 1; in step S802, based on the layout and routing data of the semiconductor chip, the text labels of the micro-bumps used to connect the rewiring layer and the interposer are captured using script 2; in step S803, based on the layout and routing data of the interposer, the layout of the interposer is extracted using script 3; in step S804, based on the layout and routing data of the interposer, the text labels of the bumps connecting the interposer and the substrate are captured using script 4; in step S805, the layouts of the rewiring layers of different semiconductor chips are translated and merged according to the relative coordinates of the layout of the interposer using script 5, thereby forming layout data that can be used for LVS verification; from step S801 to step S805, the layout data for LVS verification can be obtained. The layout data is converted into a netlist to obtain a layout netlist. In step S807, script 7 is used to set the layout layer number corresponding to the micro-bump as a capacitor, and the layout of the rewiring layer and the layout of the interposer layer are respectively set as the two electrode plates of the capacitor.

[0130] Script 2 captures the text labels for microbumps, and script 4 captures the text labels for bumps. The microbumps and bumps are placed on opposite sides of the interposer. The text labels include a name and location information; the location information includes the layout layer number and coordinate parameters.

[0131] In addition, the verification method provided by the embodiment of the present disclosure also includes the following steps: based on the circuit netlist of the semiconductor chip, extracting the circuit netlist of the rewiring layer and the circuit netlist of the interposer to obtain circuit netlist data; in step S806, using script 6 to add the theoretical connection relationship of the capacitor to the circuit netlist based on the connection relationship between the rewiring layer and the interposer. Finally, the layout data and the circuit netlist data are compared to determine whether the interposer has passed the LVS verification. In this way, the connection relationship within the layout of each capacitor and the theoretical connection relationship within the circuit netlist can be compared, and the design of the layout of the interposer is also a process of designing the connection of each micro-bump. This LVS verification satisfies both sufficiency and necessity, and can reflect the correctness of the layout design of the interposer. According to this process, the time for LVS verification of the layout design of the interposer can be greatly shortened, the communication and iteration efficiency between the back-end team and the packaging team can be accelerated, and the project development cycle can be accelerated.

[0132] refer to Figure 9 , Figure 9 A schematic diagram of a semiconductor structure is provided as another specific example. Figure 9As shown, the package structure includes: a substrate 460; an interposer 440 disposed on the substrate 460; a first semiconductor chip 410 and a second semiconductor chip 420 disposed on the interposer 440; wherein the interposer 440 and the substrate 460 are electrically connected via bumps 450, and the first semiconductor chip 410, the second semiconductor chip 420, and the interposer 440 are electrically connected via micro-bumps 430. The first semiconductor chip 410 may be a SOC chip, and the second semiconductor chip 420 may be an HBM chip.

[0133] for Figure 9 In the specific example shown, the first non-device layer may be a redistribution layer 413 within the first semiconductor chip (or the second semiconductor chip), the second non-device layer may be an intermediate layer 440 , and the first connection layer may be a micro-bump 430 .

[0134] The verification method provided in the embodiments of the present disclosure can be used for LVS verification of the interposer in a 2.5D packaged chip using any combination of chip types. The packaging structure may include but is not limited to SOC chips and SOC chips, or SOC chips and HBM chips.

[0135] The verification method provided by the disclosed embodiments, on the one hand, completes LVS verification at the fastest speed during the design phase of a 2.5D packaged chip, significantly improving the efficiency of communication and iteration between back-end and packaging engineers, avoiding the impact of interposer layout iteration on the project cycle, and reducing the pressure on machine resources caused by this verification. Furthermore, the verification method provided by the disclosed embodiments can be easily extended to LVS verification of interposers within any form of 2.5D packaged chip.

[0136] refer to Figure 10 , Figure 10 A block diagram of an electronic device provided in an embodiment of the present disclosure. Figure 10As shown, an embodiment of the present disclosure further provides an electronic device 500, which includes: a memory 510; a processor 520 coupled to the memory 510; wherein the memory 510 stores a computer program 511, and when the processor 520 executes the computer program 511, it implements the verification method provided in the above embodiments, the verification method is used to perform LVS verification on a first non-device layer and a second non-device layer in a semiconductor structure; the semiconductor structure includes a first non-device layer, a second non-device layer, and a first connection layer electrically connected to the first non-device layer and the second non-device layer. For example, the verification method includes: obtaining a merged layout based on the layout of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer in the merged layout as a capacitor; obtaining a circuit netlist based on the circuit netlist of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor based on the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist; and determining whether the first non-device layer and the second non-device layer pass the LVS verification based on the layout and circuit netlist of the capacitor.

[0137] refer to Figure 11 , Figure 11 A block diagram of a computer-readable storage medium provided in an embodiment of the present disclosure. Figure 11 As shown, the embodiment of the present disclosure also provides a computer-readable storage medium 600, on which a computer program 610 is stored. When the computer program 610 is executed, the verification method provided in the above embodiments is implemented, and the verification method is used to perform LVS verification on the first non-device layer and the second non-device layer in the semiconductor structure; the semiconductor structure includes a first non-device layer, a second non-device layer, and a first connection layer electrically connected to the first non-device layer and the second non-device layer. For example, the verification method includes: obtaining a merged layout based on the layout of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer in the merged layout as a capacitor; obtaining a circuit netlist based on the circuit netlist of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor based on the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist; and determining whether the first non-device layer and the second non-device layer pass the LVS verification based on the layout and circuit netlist of the capacitor.

[0138] In the embodiments of the present disclosure, the computer-readable storage medium may include: random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, read-only compact disks (CD-ROMs), or any other form of program code medium known in the technical field.

[0139] The present disclosure provides a verification method, an electronic device, and a computer-readable storage medium. The verification method is used to perform LVS verification on a first non-device layer and a second non-device layer in a semiconductor structure; the semiconductor structure includes the first non-device layer, the second non-device layer, and a first connection layer electrically connecting the first non-device layer and the second non-device layer; the verification method includes: obtaining a merged layout based on the layout of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer in the merged layout as a capacitor; obtaining a circuit netlist based on the circuit netlist of the first non-device layer, the second non-device layer, and the first connection layer; setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor based on the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist; and determining whether the first non-device layer and the second non-device layer pass the LVS verification based on the layout and circuit netlist of the capacitor. In the embodiment of the present disclosure, the first connection layer electrically connecting the first non-device layer and the second non-device layer is set as a capacitor, and LVS verification is performed on the capacitor to determine whether the first non-device layer and the second non-device layer have passed the LVS verification. This not only reduces the amount of data for LVS verification, thereby reducing the pressure of LVS verification on machine resources, but also saves time for each LVS verification, thereby shortening the project cycle and speeding up the project progress.

[0140] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0141] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A verification method, characterized in that: The verification method is used to perform LVS verification on the consistency of the layout and the schematic diagram of the first non-device layer and the second non-device layer in the semiconductor structure; the semiconductor structure includes the first non-device layer, the second non-device layer and a first connection layer electrically connecting the first non-device layer and the second non-device layer, and the first connection layer includes: micro bumps; the verification method includes: Obtaining a merged layout based on the layouts of the first non-device layer, the second non-device layer, and the first connection layer, including: converting coordinate parameters of the layouts of the first non-device layer and / or the second non-device layer based on the layouts of the first non-device layer and the second non-device layer and the text labels of the micro-bumps so that the coordinate systems corresponding to the coordinate parameters of the layouts of the first non-device layer and the second non-device layer are the same; and merging the layouts of the first non-device layer and the second non-device layer based on the converted coordinate parameters of the layouts of the first non-device layer and the second non-device layer to obtain a merged layout; Setting the first connection layer in the merged layout as a capacitor; Obtaining a circuit netlist according to the circuit netlists of the first non-device layer, the second non-device layer, and the first connection layer; According to the connection relationship between the first non-device layer and the second non-device layer in the circuit netlist, setting the first connection layer between the first non-device layer and the second non-device layer as a capacitor; According to the layout and circuit netlist of the capacitor, it is determined whether the first non-device layer and the second non-device layer pass LVS verification.

2. The verification method according to claim 1, wherein: The step of setting the first connection layer in the merged layout as a capacitor includes: According to the merged layout, a layout netlist is obtained; The micro-bumps in the layout netlist are set as capacitors.

3. The verification method according to claim 2, wherein: The micro-bumps include: a first bump and a second bump; the first non-device layer includes: a first wiring layer and a second wiring layer; The second non-device layer includes: a first interconnect structure, the first bump electrically connecting the first wiring layer and the first interconnect structure; The step of setting the micro-bumps in the layout netlist as capacitors comprises: The first bump in the layout netlist is set as a capacitor; wherein the first wiring layer is set as a first electrode plate of the capacitor, and the first interconnect structure is set as a second electrode plate of the capacitor.

4. The verification method according to claim 3, wherein: The second non-device layer further includes: a second interconnect structure, the second bump electrically connecting the second wiring layer and the second interconnect structure; The step of setting the micro-bumps in the layout netlist as capacitors comprises: The second bump in the layout netlist is set as a capacitor; wherein the second wiring layer is set as a first electrode plate of the capacitor, and the second interconnect structure is set as a second electrode plate of the capacitor.

5. The verification method according to claim 4, characterized in that: The determining, based on the layout and circuit netlist of the capacitor, whether the first non-device layer and the second non-device layer pass LVS verification includes: Determining whether the first non-device layer and the second non-device layer pass LVS verification according to the layout netlist and the circuit netlist of the capacitor; If the layout netlist and the circuit netlist of the capacitor set by the first bump and the capacitor set by the second bump are consistent, it is determined that the first non-device layer and the second non-device layer pass the LVS verification; If the layout netlist and circuit netlist of the capacitor defined by the first bump and / or the capacitor defined by the second bump are inconsistent, it is determined that the first non-device layer and the second non-device layer have failed LVS verification.

6. The verification method according to claim 1, wherein: The semiconductor structure further comprises: a substrate, wherein the second non-device layer is located between the substrate and the first non-device layer; A second connection layer electrically connects the substrate and the second non-device layer.

7. The verification method according to claim 6, characterized in that: The first non-device layer includes a redistribution layer; the second non-device layer includes an intermediate layer.

8. An electronic device, characterized in that: The electronic device comprises: Memory; A processor coupled to the memory; wherein a computer program is stored on the memory, and when the processor executes the computer program, the verification method according to claims 1 to 7 is implemented.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which implements the verification method according to claims 1 to 7 when executed.

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